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Tue, 24 Sep 2024 23:00:00 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 48OMxxe7024998 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 24 Sep 2024 22:59:59 GMT Received: from jesszhan-linux.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 24 Sep 2024 15:59:59 -0700 From: Jessica Zhang Date: Tue, 24 Sep 2024 15:59:36 -0700 Subject: [PATCH v2 20/22] drm/msm/dpu: Skip trigger flush and start for CWB Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20240924-concurrent-wb-v2-20-7849f900e863@quicinc.com> References: <20240924-concurrent-wb-v2-0-7849f900e863@quicinc.com> In-Reply-To: <20240924-concurrent-wb-v2-0-7849f900e863@quicinc.com> To: Rob Clark , Dmitry Baryshkov , , Sean Paul , Marijn Suijten , "David Airlie" , Daniel Vetter , "Maarten Lankhorst" , Maxime Ripard , Thomas Zimmermann CC: , , , , , Rob Clark , =?utf-8?q?Ville_Syrj=C3=A4l=C3=A4?= , "Jessica Zhang" X-Mailer: b4 0.15-dev-99b12 X-Developer-Signature: v=1; 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Return early for trigger start and trigger flush for the concurrent writeback encoders. Signed-off-by: Jessica Zhang Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/= msm/disp/dpu1/dpu_encoder.c index ac3ff13b65c3..87eaaf1196c2 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -1488,6 +1488,7 @@ static void dpu_encoder_off_work(struct work_struct *= work) static void _dpu_encoder_trigger_flush(struct drm_encoder *drm_enc, struct dpu_encoder_phys *phys, uint32_t extra_flush_bits) { + struct dpu_encoder_virt *dpu_enc =3D to_dpu_encoder_virt(drm_enc); struct dpu_hw_ctl *ctl; int pending_kickoff_cnt; u32 ret =3D UINT_MAX; @@ -1505,6 +1506,15 @@ static void _dpu_encoder_trigger_flush(struct drm_en= coder *drm_enc, =20 pending_kickoff_cnt =3D dpu_encoder_phys_inc_pending(phys); =20 + /* Return early if encoder is writeback and in clone mode */ + if (drm_enc->encoder_type =3D=3D DRM_MODE_ENCODER_VIRTUAL && + dpu_enc->cwb_mask) { + DPU_DEBUG("encoder %d skip flush for concurrent writeback encoder\n", + DRMID(drm_enc)); + return; + } + + if (extra_flush_bits && ctl->ops.update_pending_flush) ctl->ops.update_pending_flush(ctl, extra_flush_bits); =20 @@ -1527,6 +1537,8 @@ static void _dpu_encoder_trigger_flush(struct drm_enc= oder *drm_enc, */ static void _dpu_encoder_trigger_start(struct dpu_encoder_phys *phys) { + struct dpu_encoder_virt *dpu_enc =3D to_dpu_encoder_virt(phys->parent); + if (!phys) { DPU_ERROR("invalid argument(s)\n"); return; @@ -1537,6 +1549,12 @@ static void _dpu_encoder_trigger_start(struct dpu_en= coder_phys *phys) return; } =20 + if (phys->parent->encoder_type =3D=3D DRM_MODE_ENCODER_VIRTUAL && + dpu_enc->cwb_mask) { + DPU_DEBUG("encoder %d CWB enabled, skipping\n", DRMID(phys->parent)); + return; + } + if (phys->ops.trigger_start && phys->enable_state !=3D DPU_ENC_DISABLED) phys->ops.trigger_start(phys); } --=20 2.34.1