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Tue, 24 Sep 2024 23:00:00 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 48OMxwBX027335 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 24 Sep 2024 22:59:58 GMT Received: from jesszhan-linux.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 24 Sep 2024 15:59:58 -0700 From: Jessica Zhang Date: Tue, 24 Sep 2024 15:59:34 -0700 Subject: [PATCH v2 18/22] drm/msm/dpu: Adjust writeback phys encoder setup for CWB Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20240924-concurrent-wb-v2-18-7849f900e863@quicinc.com> References: <20240924-concurrent-wb-v2-0-7849f900e863@quicinc.com> In-Reply-To: <20240924-concurrent-wb-v2-0-7849f900e863@quicinc.com> To: Rob Clark , Dmitry Baryshkov , , Sean Paul , Marijn Suijten , "David Airlie" , Daniel Vetter , "Maarten Lankhorst" , Maxime Ripard , Thomas Zimmermann CC: , , , , , Rob Clark , =?utf-8?q?Ville_Syrj=C3=A4l=C3=A4?= , "Jessica Zhang" X-Mailer: b4 0.15-dev-99b12 X-Developer-Signature: v=1; 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ot_params.width =3D phys_enc->cached_mode.hdisplay; ot_params.height =3D phys_enc->cached_mode.vdisplay; - ot_params.is_wfd =3D true; + ot_params.is_wfd =3D !dpu_encoder_helper_get_cwb(phys_enc); ot_params.frame_rate =3D drm_mode_vrefresh(&phys_enc->cached_mode); ot_params.vbif_idx =3D hw_wb->caps->vbif_idx; ot_params.rd =3D false; @@ -111,7 +111,7 @@ static void dpu_encoder_phys_wb_set_qos_remap( qos_params.vbif_idx =3D hw_wb->caps->vbif_idx; qos_params.xin_id =3D hw_wb->caps->xin_id; qos_params.num =3D hw_wb->idx - WB_0; - qos_params.is_rt =3D false; + qos_params.is_rt =3D dpu_encoder_helper_get_cwb(phys_enc); =20 DPU_DEBUG("[qos_remap] wb:%d vbif:%d xin:%d is_rt:%d\n", qos_params.num, @@ -174,6 +174,7 @@ static void dpu_encoder_phys_wb_setup_fb(struct dpu_enc= oder_phys *phys_enc, struct dpu_encoder_phys_wb *wb_enc =3D to_dpu_encoder_phys_wb(phys_enc); struct dpu_hw_wb *hw_wb; struct dpu_hw_wb_cfg *wb_cfg; + u32 cdp_usage; =20 if (!phys_enc || !phys_enc->dpu_kms || !phys_enc->dpu_kms->catalog) { DPU_ERROR("invalid encoder\n"); @@ -182,6 +183,10 @@ static void dpu_encoder_phys_wb_setup_fb(struct dpu_en= coder_phys *phys_enc, =20 hw_wb =3D phys_enc->hw_wb; wb_cfg =3D &wb_enc->wb_cfg; + if (dpu_encoder_helper_get_cwb(phys_enc)) + cdp_usage =3D DPU_PERF_CDP_USAGE_RT; + else + cdp_usage =3D DPU_PERF_CDP_USAGE_NRT; =20 wb_cfg->intf_mode =3D phys_enc->intf_mode; wb_cfg->roi.x1 =3D 0; @@ -199,7 +204,7 @@ static void dpu_encoder_phys_wb_setup_fb(struct dpu_enc= oder_phys *phys_enc, const struct dpu_perf_cfg *perf =3D phys_enc->dpu_kms->catalog->perf; =20 hw_wb->ops.setup_cdp(hw_wb, wb_cfg->dest.format, - perf->cdp_cfg[DPU_PERF_CDP_USAGE_NRT].wr_enable); + perf->cdp_cfg[cdp_usage].wr_enable); } =20 if (hw_wb->ops.setup_outaddress) --=20 2.34.1