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Tue, 24 Sep 2024 22:59:58 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 48OMxvN2007773 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 24 Sep 2024 22:59:57 GMT Received: from jesszhan-linux.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 24 Sep 2024 15:59:57 -0700 From: Jessica Zhang Date: Tue, 24 Sep 2024 15:59:29 -0700 Subject: [PATCH v2 13/22] drm/msm/dpu: Add CWB to msm_display_topology Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20240924-concurrent-wb-v2-13-7849f900e863@quicinc.com> References: <20240924-concurrent-wb-v2-0-7849f900e863@quicinc.com> In-Reply-To: <20240924-concurrent-wb-v2-0-7849f900e863@quicinc.com> To: Rob Clark , Dmitry Baryshkov , , Sean Paul , Marijn Suijten , "David Airlie" , Daniel Vetter , "Maarten Lankhorst" , Maxime Ripard , Thomas Zimmermann CC: , , , , , Rob Clark , =?utf-8?q?Ville_Syrj=C3=A4l=C3=A4?= , "Jessica Zhang" X-Mailer: b4 0.15-dev-99b12 X-Developer-Signature: v=1; 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=20 + topology.cwb_enabled =3D drm_crtc_in_clone_mode(crtc_state); + /* * Datapath topology selection * @@ -1189,9 +1191,9 @@ static struct msm_display_topology dpu_crtc_get_topol= ogy( * Add dspps to the reservation requirements if ctm is requested */ =20 - if (topology.num_intf =3D=3D 2) + if (topology.num_intf =3D=3D 2 && !topology.cwb_enabled) topology.num_lm =3D 2; - else if (topology.num_dsc =3D=3D 2) + else if (topology.num_dsc =3D=3D 2 && !topology.cwb_enabled) topology.num_lm =3D 2; else if (dpu_kms->catalog->caps->has_3d_merge) topology.num_lm =3D (mode->hdisplay > MAX_HDISPLAY_SPLIT) ? 2 : 1; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/d= isp/dpu1/dpu_rm.c index 96c80cf9f6ad..04df3056d75a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c @@ -371,8 +371,14 @@ static int _dpu_rm_reserve_ctls( int i =3D 0, j, num_ctls; bool needs_split_display; =20 - /* each hw_intf needs its own hw_ctrl to program its control path */ - num_ctls =3D top->num_intf; + /* + * For non-CWB mode, each hw_intf needs its own hw_ctl to program its + * control path. Hardcode num_ctls to 1 if CWB is enabled + */ + if (top->cwb_enabled) + num_ctls =3D 1; + else + num_ctls =3D top->num_intf; =20 needs_split_display =3D _dpu_rm_needs_split_display(top); =20 diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index 0d3adf398bc1..8a2a3705f117 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. * Copyright (C) 2013 Red Hat * Author: Rob Clark @@ -88,6 +89,7 @@ struct msm_display_topology { u32 num_dspp; u32 num_dsc; bool needs_cdm; + bool cwb_enabled; }; =20 /* Commit/Event thread specific structure */ --=20 2.34.1