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Signed-off-by: Liu Ying Signed-off-by: Laurentiu Mihalcea Reviewed-by: Krzysztof Kozlowski --- .../reset/nxp,imx8ulp-avd-sim-reset.yaml | 58 +++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/nxp,imx8ulp-avd= -sim-reset.yaml diff --git a/Documentation/devicetree/bindings/reset/nxp,imx8ulp-avd-sim-re= set.yaml b/Documentation/devicetree/bindings/reset/nxp,imx8ulp-avd-sim-rese= t.yaml new file mode 100644 index 000000000000..f6797966fd35 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/nxp,imx8ulp-avd-sim-reset.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/nxp,imx8ulp-avd-sim-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX8ULP System Integration Module Reset Controller + +maintainers: + - Liu Ying + +description: + Some instances of i.MX8ULP's SIM may offer control over the reset of some + components of a certain domain (example - AVD-SIM). + +properties: + compatible: + items: + - enum: + - nxp,imx8ulp-avd-sim-reset + - const: syscon + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + '#reset-cells': + const: 1 + + mux-controller: + $ref: /schemas/mux/reg-mux.yaml# + +required: + - compatible + - reg + - clocks + - '#reset-cells' + - mux-controller + +additionalProperties: false + +examples: + - | + #include + syscon@2da50000 { + compatible =3D "nxp,imx8ulp-avd-sim-reset", "syscon"; + reg =3D <0x2da50000 0x38>; + clocks =3D <&pcc5 IMX8ULP_CLK_AVD_SIM>; + #reset-cells =3D <1>; + + mux-controller { + compatible =3D "mmio-mux"; + #mux-control-cells =3D <1>; + mux-reg-masks =3D <0x8 0x00000200>; + }; + }; --=20 2.34.1 From nobody Fri Nov 29 08:40:16 2024 Received: from mail-wm1-f48.google.com (mail-wm1-f48.google.com [209.85.128.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 718062AE9F; Sun, 22 Sep 2024 17:43:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727027013; cv=none; b=Zpr6/Wi+kCjCIrh6hJOJb9L82NZ5p+/tARORf8ixp0FW3UJa8XEboZisTlH2x/FLBjBss5EJzlTzszGYfucvX1U8GEPX5HTzNghqhAtKCFYV2+9M+cOHBoI+3rLHAgY0+hbnm7ratJgYEzNmpL4qo6HNKhxH+m4nF4+wnXYj22g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727027013; 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charset="utf-8" From: Laurentiu Mihalcea Certain components can be reset via the SIM module. Add reset controller driver for the SIM module to allow drivers for said components to control the reset signal(s). Signed-off-by: Liu Ying Signed-off-by: Laurentiu Mihalcea --- drivers/reset/Kconfig | 7 ++ drivers/reset/Makefile | 1 + drivers/reset/reset-imx8ulp-sim.c | 106 ++++++++++++++++++++++++++++++ 3 files changed, 114 insertions(+) create mode 100644 drivers/reset/reset-imx8ulp-sim.c diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 5484a65f66b9..492081354d03 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -113,6 +113,13 @@ config RESET_IMX8MP_AUDIOMIX help This enables the reset controller driver for i.MX8MP AudioMix =20 +config RESET_IMX8ULP_SIM + tristate "i.MX8ULP SIM Reset Driver" + depends on ARCH_MXC + help + This enables the SIM (System Integration Module) reset driver + for i.MX8ULP SoC. + config RESET_INTEL_GW bool "Intel Reset Controller Driver" depends on X86 || COMPILE_TEST diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 4411a2a124d7..38354e701811 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -16,6 +16,7 @@ obj-$(CONFIG_RESET_GPIO) +=3D reset-gpio.o obj-$(CONFIG_RESET_HSDK) +=3D reset-hsdk.o obj-$(CONFIG_RESET_IMX7) +=3D reset-imx7.o obj-$(CONFIG_RESET_IMX8MP_AUDIOMIX) +=3D reset-imx8mp-audiomix.o +obj-$(CONFIG_RESET_IMX8ULP_SIM) +=3D reset-imx8ulp-sim.o obj-$(CONFIG_RESET_INTEL_GW) +=3D reset-intel-gw.o obj-$(CONFIG_RESET_K210) +=3D reset-k210.o obj-$(CONFIG_RESET_LANTIQ) +=3D reset-lantiq.o diff --git a/drivers/reset/reset-imx8ulp-sim.c b/drivers/reset/reset-imx8ul= p-sim.c new file mode 100644 index 000000000000..04ff11d41e10 --- /dev/null +++ b/drivers/reset/reset-imx8ulp-sim.c @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2024 NXP + */ + +#include +#include +#include +#include +#include +#include +#include + +#define IMX8ULP_SIM_RESET_MIPI_DSI_RST_DPI_N 0 +#define IMX8ULP_SIM_RESET_MIPI_DSI_RST_ESC_N 1 +#define IMX8ULP_SIM_RESET_MIPI_DSI_RST_BYTE_N 2 + +#define IMX8ULP_SIM_RESET_NUM 3 + +#define AVD_SIM_SYSCTRL0 0x8 + +struct imx8ulp_sim_reset { + struct reset_controller_dev rcdev; + struct regmap *regmap; +}; + +static const u32 imx8ulp_sim_reset_bits[IMX8ULP_SIM_RESET_NUM] =3D { + [IMX8ULP_SIM_RESET_MIPI_DSI_RST_DPI_N] =3D BIT(3), + [IMX8ULP_SIM_RESET_MIPI_DSI_RST_ESC_N] =3D BIT(4), + [IMX8ULP_SIM_RESET_MIPI_DSI_RST_BYTE_N] =3D BIT(5), +}; + +static inline struct imx8ulp_sim_reset * +to_imx8ulp_sim_reset(struct reset_controller_dev *rcdev) +{ + return container_of(rcdev, struct imx8ulp_sim_reset, rcdev); +} + +static int imx8ulp_sim_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct imx8ulp_sim_reset *simr =3D to_imx8ulp_sim_reset(rcdev); + const u32 bit =3D imx8ulp_sim_reset_bits[id]; + + return regmap_update_bits(simr->regmap, AVD_SIM_SYSCTRL0, bit, 0); +} + +static int imx8ulp_sim_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct imx8ulp_sim_reset *simr =3D to_imx8ulp_sim_reset(rcdev); + const u32 bit =3D imx8ulp_sim_reset_bits[id]; + + return regmap_update_bits(simr->regmap, AVD_SIM_SYSCTRL0, bit, bit); +} + +static const struct reset_control_ops imx8ulp_sim_reset_ops =3D { + .assert =3D imx8ulp_sim_reset_assert, + .deassert =3D imx8ulp_sim_reset_deassert, +}; + +static const struct of_device_id imx8ulp_sim_reset_dt_ids[] =3D { + { .compatible =3D "nxp,imx8ulp-avd-sim-reset", }, + { /* sentinel */ }, +}; + +static int imx8ulp_sim_reset_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct imx8ulp_sim_reset *simr; + int ret; + + simr =3D devm_kzalloc(dev, sizeof(*simr), GFP_KERNEL); + if (!simr) + return -ENOMEM; + + simr->regmap =3D syscon_node_to_regmap(dev->of_node); + if (IS_ERR(simr->regmap)) + return dev_err_probe(&pdev->dev, PTR_ERR(simr->regmap), + "failed to get regmap\n"); + + simr->rcdev.owner =3D THIS_MODULE; + simr->rcdev.nr_resets =3D IMX8ULP_SIM_RESET_NUM; + simr->rcdev.ops =3D &imx8ulp_sim_reset_ops; + simr->rcdev.of_node =3D dev->of_node; + + ret =3D devm_of_platform_populate(dev); + if (ret) + return ret; + + return devm_reset_controller_register(dev, &simr->rcdev); +} + +static struct platform_driver imx8ulp_sim_reset_driver =3D { + .probe =3D imx8ulp_sim_reset_probe, + .driver =3D { + .name =3D KBUILD_MODNAME, + .of_match_table =3D imx8ulp_sim_reset_dt_ids, + }, +}; +module_platform_driver(imx8ulp_sim_reset_driver); + +MODULE_AUTHOR("Liu Ying "); +MODULE_DESCRIPTION("NXP i.MX8ULP System Integration Module Reset driver"); +MODULE_LICENSE("GPL"); --=20 2.34.1 From nobody Fri Nov 29 08:40:16 2024 Received: from mail-wm1-f41.google.com (mail-wm1-f41.google.com [209.85.128.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5418F482E2; Sun, 22 Sep 2024 17:43:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727027016; cv=none; b=q73elEyDX6HeSI7yQ+7+D5RRIbAphlZ29TCc7vTnaU68lm0XgrRkZKccsEFFdV1jcWH0KRzlJRnOj3PkOwUnfXCeK6T5xmEIS7uYBthaI4y2pFYCbhdriqUTni+fegGkumEqJb1y8l7JyuX3LjMXlKSnIhT8Gqp2aQ/1mAxjEdE= ARC-Message-Signature: i=1; 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Sun, 22 Sep 2024 10:43:32 -0700 (PDT) From: Laurentiu Mihalcea To: Rob Herring , Krzysztof Kozlowski , Shawn Guo , Philipp Zabel , Liu Ying , Sascha Hauer , Conor Dooley Cc: devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 3/3] arm64: dts: imx8ulp: add AVD-SIM node Date: Sun, 22 Sep 2024 13:42:25 -0400 Message-Id: <20240922174225.75948-4-laurentiumihalcea111@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240922174225.75948-1-laurentiumihalcea111@gmail.com> References: <20240922174225.75948-1-laurentiumihalcea111@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Laurentiu Mihalcea Add node for imx8ulp's AVD-SIM module. This also includes its children. Signed-off-by: Liu Ying Signed-off-by: Laurentiu Mihalcea Reviewed-by: Daniel Baluta --- arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/d= ts/freescale/imx8ulp.dtsi index e32d5afcf4a9..1ffa4da23042 100644 --- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi @@ -614,6 +614,19 @@ per_bridge5: bus@2d800000 { #size-cells =3D <1>; ranges; =20 + avd_sim: syscon@2da50000 { + compatible =3D "nxp,imx8ulp-avd-sim-reset", "syscon"; + reg =3D <0x2da50000 0x38>; + clocks =3D <&pcc5 IMX8ULP_CLK_AVD_SIM>; + #reset-cells =3D <1>; + + mux: mux-controller { + compatible =3D "mmio-mux"; + #mux-control-cells =3D <1>; + mux-reg-masks =3D <0x8 0x00000200>; + }; + }; + cgc2: clock-controller@2da60000 { compatible =3D "fsl,imx8ulp-cgc2"; reg =3D <0x2da60000 0x10000>; --=20 2.34.1