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Signed-off-by: Md Sadre Alam --- Change in [v10] * No change=20 Change in [v9] * No change Change in [v8] * No change Change in [v7] * No change Change in [v6] * No change Change in [v5] * No change Change in [v4] * No change Change in [v3] * Updated gpio number as per pin control driver * Fixed alignment issue Change in [v2] * Added initial enablement for spi-nand=20 Change in [v1] * Posted as RFC patch for design review .../boot/dts/qcom/ipq9574-rdp-common.dtsi | 43 +++++++++++++++++++ arch/arm64/boot/dts/qcom/ipq9574.dtsi | 27 ++++++++++++ 2 files changed, 70 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi b/arch/arm64/= boot/dts/qcom/ipq9574-rdp-common.dtsi index 91e104b0f865..6429a6b3b903 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi @@ -139,6 +139,49 @@ gpio_leds_default: gpio-leds-default-state { drive-strength =3D <8>; bias-pull-up; }; + + qpic_snand_default_state: qpic-snand-default-state { + clock-pins { + pins =3D "gpio5"; + function =3D "qspi_clk"; + drive-strength =3D <8>; + bias-disable; + }; + + cs-pins { + pins =3D "gpio4"; + function =3D "qspi_cs"; + drive-strength =3D <8>; + bias-disable; + }; + + data-pins { + pins =3D "gpio0", "gpio1", "gpio2", "gpio3"; + function =3D "qspi_data"; + drive-strength =3D <8>; + bias-disable; + }; + }; +}; + +&qpic_bam { + status =3D "okay"; +}; + +&qpic_nand { + pinctrl-0 =3D <&qpic_snand_default_state>; + pinctrl-names =3D "default"; + status =3D "okay"; + + flash@0 { + compatible =3D "spi-nand"; + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <1>; + nand-ecc-engine =3D <&qpic_nand>; + nand-ecc-strength =3D <4>; + nand-ecc-step-size =3D <512>; + }; }; =20 &usb_0_dwc3 { diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qc= om/ipq9574.dtsi index 08a82a5cf667..65e70b33c587 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -330,6 +330,33 @@ tcsr: syscon@1937000 { reg =3D <0x01937000 0x21000>; }; =20 + qpic_bam: dma-controller@7984000 { + compatible =3D "qcom,bam-v1.7.0"; + reg =3D <0x7984000 0x1c000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QPIC_AHB_CLK>; + clock-names =3D "bam_clk"; + #dma-cells =3D <1>; + qcom,ee =3D <0>; + status =3D "disabled"; + }; + + qpic_nand: spi@79b0000 { + compatible =3D "qcom,spi-qpic-snand"; + reg =3D <0x79b0000 0x10000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&gcc GCC_QPIC_CLK>, + <&gcc GCC_QPIC_AHB_CLK>, + <&gcc GCC_QPIC_IO_MACRO_CLK>; + clock-names =3D "core", "aon", "iom"; + dmas =3D <&qpic_bam 0>, + <&qpic_bam 1>, + <&qpic_bam 2>; + dma-names =3D "tx", "rx", "cmd"; + status =3D "disabled"; + }; + sdhc_1: mmc@7804000 { compatible =3D "qcom,ipq9574-sdhci", "qcom,sdhci-msm-v5"; reg =3D <0x07804000 0x1000>, --=20 2.34.1