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Sun, 22 Sep 2024 01:14:30 -0500 From: Thippeswamy Havalige To: , , , , , , CC: , , , , , , Thippeswamy Havalige Subject: [PATCH v3 2/2] PCI: xilinx-cpm: Add support for Versal CPM5 Root Port controller 1 Date: Sun, 22 Sep 2024 11:43:18 +0530 Message-ID: <20240922061318.2653503-3-thippesw@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240922061318.2653503-1-thippesw@amd.com> References: <20240922061318.2653503-1-thippesw@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099D3:EE_|CH3PR12MB7547:EE_ X-MS-Office365-Filtering-Correlation-Id: 2b8dfd2b-545a-45ec-5f2b-08dcdacdd501 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|7416014|36860700013|376014|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?pHVU8h2oetBhjJH0AbWhVp8cjLvYqzwggKs/y1KDyhBzd1YmVIZm+ur6qsvJ?= =?us-ascii?Q?j8o9KGY2RAsHjUB95in5JsSppONg2Hvgdd0cRJY8PMHNEwNT4ERo0uESCDuB?= =?us-ascii?Q?znT62sDKNHbYMERuv7rFvmrAfCt8HS/g6GVIq1V0wRTnWhF27xKQS0QwcWIF?= =?us-ascii?Q?8DXVVlcSHxdedpPZ66XYB7PT6L74WOLQIQjrSnFRCF3j4ei7w6i5CIzzHCPd?= =?us-ascii?Q?Chj8Dsjasv6R7LMTA7Y3S+gjjOVeF8298KF9dH/dNEL3QdogHEKrF5a/wSsl?= =?us-ascii?Q?TsXCTd9Bjnp7iEfqulrgEqqYabnYOLQiZQM+dJrwCYF3zkX/pez/Ay9DcUSQ?= =?us-ascii?Q?XwRZMFeKcP3fzwxH9kfygrhH6gvyszUyQCbwHrBTPE1+d8ILLKixxeIx9E7j?= =?us-ascii?Q?sRYdpxKl6LBtGv80OMEWt/Oj6wshZHE23oLlBHtPehVpnVXpjMGAXEz9LeXw?= =?us-ascii?Q?s0Lsr6wsTaEbeA3//S1xDZlsQDfUrUivuKjskDgNNnkDOZMQRH+nA/xrYHTn?= =?us-ascii?Q?nfk+hxWmPwm+z4VC5uWtUufHh6dQyiZ0++KCfvzOe8wHylncBZI3p5x3Q+PR?= =?us-ascii?Q?c5MTfSrZB2P786pEwujgiNrXmxN4c1Jp8qL5AI7eVqLBhfpfCimnKYZ5Ahgg?= =?us-ascii?Q?y7R+sBJVOCiCZndYxIURnYwpmXaXWJMRNkSJHGwkfAGfdpooWE7Gfw3NmCiH?= =?us-ascii?Q?5MEHE144XVrRYwTSEl8N5hfVl56U8LblE2mTqbKqYpTpN3XqUMTiwda+a0QO?= =?us-ascii?Q?KYcf4bfEmCc+7Y/6ZrcI9FeAOLD9+FAwszgFcfqu25GFHRJuP4XNx6d0k3x5?= =?us-ascii?Q?OBaDAbZQUiSW/IjrKCOCIP26GhAbKi/msM3xXeA79cCXnGMPn3xcQAy6bvNe?= =?us-ascii?Q?d+ljK38BPSp4j8unLncWXfZhriKu1Z/4I315s6y1cEKP4Mtv6cTQhFkzl2Xu?= =?us-ascii?Q?+RAadJhLg92fXBmMrqgxfNG/c5Gsar5ILtIn/e69wM9MSnA+iRjQpVTXrKS8?= =?us-ascii?Q?ePoQKdtyg3QdTz6KY1mU+P5xeOVsqXK/5oMIZBgAu1iEtnuGumQtzNkkPqxM?= =?us-ascii?Q?fESZ08w1fUAYm2W1gZ9zemAJh53/Ps6pr4kzaqdiMbHv+WGqyprkoUaZjutR?= =?us-ascii?Q?5CF8yVScXoHl1hrQabE5qDkOD+6YPP2ReiuUBZeN5BqlxR1x/oBI9yJNW6hn?= =?us-ascii?Q?fapMmHdoils/Szu6n+p3rPiflKh8SOIKqCrrkmngWcs0sp43b60oV7pBYT6j?= =?us-ascii?Q?YIXZo5lU9Q3JO93iPUPmQ7EMgUpS7rkD+XdcMjoufz9dGJx0vkysvO0n1N8/?= =?us-ascii?Q?1HubsgT54FSIMKG0BWr2ytP8Pua5tHFs4br34vq8wX3m3q8cAQ7ZWc87jucG?= =?us-ascii?Q?a9oz+w/gtLzbhwNebuxnOjvOYtCJQFboX1N24jTbIEtUf/NP3oUF2iNI8eE0?= =?us-ascii?Q?5pK5BV0yWx+C665SljfBQuPl5CkacPQG?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(7416014)(36860700013)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Sep 2024 06:14:35.5461 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2b8dfd2b-545a-45ec-5f2b-08dcdacdd501 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099D3.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB7547 Content-Type: text/plain; charset="utf-8" Add support for the Xilinx Versal CPM5 Root Port Controller 1. The key difference between Controller 0 and Controller 1 lies in the platform-specific error interrupt bits, which are located at different register offsets. To handle these differences, updated variant structure to hold the following platform-specific details: - Interrupt status register offset (ir_status) - Interrupt enable register offset (ir_enable) - Miscellaneous interrupt values (ir_misc_value) The driver differentiates between Controller 0 and Controller 1 using the compatible string in the device tree. This ensures that the appropriate register offsets are used for each controller, allowing for correct handling of platform-specific interrupts and initialization. Signed-off-by: Thippeswamy Havalige Reviewed-by: Manivannan Sadhasivam --- changes in v3: -------------- 1. Add kernel Documentation for variant structure. 2. Modify compatible string. changes in v2: -------------- 1. Introduced new constants for Controller 1. 2. Extended the xilinx_cpm_variant structure to support a. ir_status, b. ir_enable, and=20 c. ir_misc_value for different controllers. 3. Updated IRQ handling and initialization to use the variant structure. 4. Added a new device tree match entry for Controller 1. --- drivers/pci/controller/pcie-xilinx-cpm.c | 50 ++++++++++++++++++------ 1 file changed, 39 insertions(+), 11 deletions(-) diff --git a/drivers/pci/controller/pcie-xilinx-cpm.c b/drivers/pci/control= ler/pcie-xilinx-cpm.c index a0f5e1d67b04..81e8bfae53d0 100644 --- a/drivers/pci/controller/pcie-xilinx-cpm.c +++ b/drivers/pci/controller/pcie-xilinx-cpm.c @@ -30,11 +30,14 @@ #define XILINX_CPM_PCIE_REG_IDRN_MASK 0x00000E3C #define XILINX_CPM_PCIE_MISC_IR_STATUS 0x00000340 #define XILINX_CPM_PCIE_MISC_IR_ENABLE 0x00000348 -#define XILINX_CPM_PCIE_MISC_IR_LOCAL BIT(1) +#define XILINX_CPM_PCIE0_MISC_IR_LOCAL BIT(1) +#define XILINX_CPM_PCIE1_MISC_IR_LOCAL BIT(2) =20 -#define XILINX_CPM_PCIE_IR_STATUS 0x000002A0 -#define XILINX_CPM_PCIE_IR_ENABLE 0x000002A8 -#define XILINX_CPM_PCIE_IR_LOCAL BIT(0) +#define XILINX_CPM_PCIE0_IR_STATUS 0x000002A0 +#define XILINX_CPM_PCIE1_IR_STATUS 0x000002B4 +#define XILINX_CPM_PCIE0_IR_ENABLE 0x000002A8 +#define XILINX_CPM_PCIE1_IR_ENABLE 0x000002BC +#define XILINX_CPM_PCIE_IR_LOCAL BIT(0) =20 #define IMR(x) BIT(XILINX_PCIE_INTR_ ##x) =20 @@ -80,14 +83,21 @@ enum xilinx_cpm_version { CPM, CPM5, + CPM5_HOST1, }; =20 /** * struct xilinx_cpm_variant - CPM variant information * @version: CPM version + * @ir_status: Offset for the error interrupt status register + * @ir_enable: Offset for the CPM5 local error interrupt enable register + * @ir_misc_value: A bitmask for the miscellaneous interrupt status */ struct xilinx_cpm_variant { enum xilinx_cpm_version version; + u32 ir_status; + u32 ir_enable; + u32 ir_misc_value; }; =20 /** @@ -269,6 +279,7 @@ static void xilinx_cpm_pcie_event_flow(struct irq_desc = *desc) { struct xilinx_cpm_pcie *port =3D irq_desc_get_handler_data(desc); struct irq_chip *chip =3D irq_desc_get_chip(desc); + const struct xilinx_cpm_variant *variant =3D port->variant; unsigned long val; int i; =20 @@ -279,11 +290,11 @@ static void xilinx_cpm_pcie_event_flow(struct irq_des= c *desc) generic_handle_domain_irq(port->cpm_domain, i); pcie_write(port, val, XILINX_CPM_PCIE_REG_IDR); =20 - if (port->variant->version =3D=3D CPM5) { - val =3D readl_relaxed(port->cpm_base + XILINX_CPM_PCIE_IR_STATUS); + if (variant->ir_status) { + val =3D readl_relaxed(port->cpm_base + variant->ir_status); if (val) writel_relaxed(val, port->cpm_base + - XILINX_CPM_PCIE_IR_STATUS); + variant->ir_status); } =20 /* @@ -465,6 +476,8 @@ static int xilinx_cpm_setup_irq(struct xilinx_cpm_pcie = *port) */ static void xilinx_cpm_pcie_init_port(struct xilinx_cpm_pcie *port) { + const struct xilinx_cpm_variant *variant =3D port->variant; + if (cpm_pcie_link_up(port)) dev_info(port->dev, "PCIe Link is UP\n"); else @@ -483,15 +496,15 @@ static void xilinx_cpm_pcie_init_port(struct xilinx_c= pm_pcie *port) * XILINX_CPM_PCIE_MISC_IR_ENABLE register is mapped to * CPM SLCR block. */ - writel(XILINX_CPM_PCIE_MISC_IR_LOCAL, + writel(variant->ir_misc_value, port->cpm_base + XILINX_CPM_PCIE_MISC_IR_ENABLE); =20 - if (port->variant->version =3D=3D CPM5) { + if (variant->ir_enable) { writel(XILINX_CPM_PCIE_IR_LOCAL, - port->cpm_base + XILINX_CPM_PCIE_IR_ENABLE); + port->cpm_base + variant->ir_enable); } =20 - /* Enable the Bridge enable bit */ + /* Set Bridge enable bit */ pcie_write(port, pcie_read(port, XILINX_CPM_PCIE_REG_RPSC) | XILINX_CPM_PCIE_REG_RPSC_BEN, XILINX_CPM_PCIE_REG_RPSC); @@ -609,10 +622,21 @@ static int xilinx_cpm_pcie_probe(struct platform_devi= ce *pdev) =20 static const struct xilinx_cpm_variant cpm_host =3D { .version =3D CPM, + .ir_misc_value =3D XILINX_CPM_PCIE0_MISC_IR_LOCAL, }; =20 static const struct xilinx_cpm_variant cpm5_host =3D { .version =3D CPM5, + .ir_misc_value =3D XILINX_CPM_PCIE0_MISC_IR_LOCAL, + .ir_status =3D XILINX_CPM_PCIE0_IR_STATUS, + .ir_enable =3D XILINX_CPM_PCIE0_IR_ENABLE, +}; + +static const struct xilinx_cpm_variant cpm5_host1 =3D { + .version =3D CPM5_HOST1, + .ir_misc_value =3D XILINX_CPM_PCIE1_MISC_IR_LOCAL, + .ir_status =3D XILINX_CPM_PCIE1_IR_STATUS, + .ir_enable =3D XILINX_CPM_PCIE1_IR_ENABLE, }; =20 static const struct of_device_id xilinx_cpm_pcie_of_match[] =3D { @@ -624,6 +648,10 @@ static const struct of_device_id xilinx_cpm_pcie_of_ma= tch[] =3D { .compatible =3D "xlnx,versal-cpm5-host", .data =3D &cpm5_host, }, + { + .compatible =3D "xlnx,versal-cpm5-host1", + .data =3D &cpm5_host1, + }, {} }; =20 --=20 2.34.1