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Sat, 21 Sep 2024 01:17:37 -0700 (PDT) Received: from umbar.lan ([192.130.178.90]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-536870968d1sm2466380e87.175.2024.09.21.01.17.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 21 Sep 2024 01:17:36 -0700 (PDT) From: Dmitry Baryshkov Date: Sat, 21 Sep 2024 11:17:29 +0300 Subject: [PATCH 1/4] drm/msm: move MDSS registers to separate header file Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240921-msm-mdss-ubwc-v1-1-411dcf309d05@linaro.org> References: <20240921-msm-mdss-ubwc-v1-0-411dcf309d05@linaro.org> In-Reply-To: <20240921-msm-mdss-ubwc-v1-0-411dcf309d05@linaro.org> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3169; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=xLM1ISnVwa/GRZKkuzfezgSM5E3kbR2k0DPUIeRVKCA=; b=owGbwMvMwMXYbdNlx6SpcZXxtFoSQ9q7RvmrvSzz6qY77lq3Y239d6FM0cAjy46E/LzRb+T8l 7k7xzuyk9GYhYGRi0FWTJHFp6Blasym5LAPO6bWwwxiZQKZwsDFKQATWfKD/X/tKw3dxFsN4Ym3 YpXVTZRYN9jL5NXWnOlYHOdqu9t9jWvgkaZ1dg9d/m195H6t7pqhXHZW3vPbCv1xiybfcZVc++V Dpt+F+mzlxzUmP1ofvWll2bBo4S+FXC9uy0ym9lCl9w8LbgucNHoix1W5a5bYwzKbPX9L3Jju2H VOve4vPsk2Y7K33OLwstK9t2LUFy5huLT0oIqVwgV7nT+v7z49EbNsq2WfFa/VM9tb7TvDfvJ7L 1N3WOb5/1ebqSTvlijxz65FZ2y09hxzSJ88tYmxLs6zoXjeeTGFJYWhLsvepWpK/85wCVr12z3W jc9xzuuo6wzS9luXBKZYamvWSKsfZvv+tPuFQRuf9rY8AA== X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A In preparation of adding more registers, move MDSS-related headers to the separate top-level file. Signed-off-by: Dmitry Baryshkov Reviewed-by: Abhinav Kumar --- drivers/gpu/drm/msm/Makefile | 1 + drivers/gpu/drm/msm/registers/display/mdp5.xml | 16 ---------------- drivers/gpu/drm/msm/registers/display/mdss.xml | 23 +++++++++++++++++++++++ 3 files changed, 24 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile index 13110fcc46a8..db2174e2efa8 100644 --- a/drivers/gpu/drm/msm/Makefile +++ b/drivers/gpu/drm/msm/Makefile @@ -210,6 +210,7 @@ DISPLAY_HEADERS =3D \ generated/mdp4.xml.h \ generated/mdp5.xml.h \ generated/mdp_common.xml.h \ + generated/mdss.xml.h \ generated/sfpb.xml.h =20 $(addprefix $(obj)/,$(adreno-y)): $(addprefix $(obj)/,$(ADRENO_HEADERS)) diff --git a/drivers/gpu/drm/msm/registers/display/mdp5.xml b/drivers/gpu/d= rm/msm/registers/display/mdp5.xml index 92f3263af170..8c9c4af350aa 100644 --- a/drivers/gpu/drm/msm/registers/display/mdp5.xml +++ b/drivers/gpu/drm/msm/registers/display/mdp5.xml @@ -9,22 +9,6 @@ xsi:schemaLocation=3D"https://gitlab.freedesktop.org/freed= reno/ rules-fd.xsd"> =20 - - - - - - - - - - - - - - - - =20 diff --git a/drivers/gpu/drm/msm/registers/display/mdss.xml b/drivers/gpu/d= rm/msm/registers/display/mdss.xml new file mode 100644 index 000000000000..9354cfffb730 --- /dev/null +++ b/drivers/gpu/drm/msm/registers/display/mdss.xml @@ -0,0 +1,23 @@ + + + + + + + + + + + + + + + + + + + + + --=20 2.39.5 From nobody Mon Feb 9 10:49:46 2026 Received: from mail-lf1-f51.google.com (mail-lf1-f51.google.com [209.85.167.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 208851547CC for ; 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a=openpgp-sha256; l=4880; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=G6PowQr5FW3NdBDRADRSrKvw2U+ewXo5XcoYzvoJ6Pw=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBm7oEf05dbGt5Lc6aHVGnCmSnC98kTf0qX6d9UE NnCD/w7AaqJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZu6BHwAKCRCLPIo+Aiko 1dcDCACg5ArOXMPZTRiJhXhrpweO8bTOXVhdYdh/WLR70YN5xSIeKiL6XFSJMwK2Sf/5QdIPwit nyF2N7SRgIbtc5i6+CPjY1UnAd4jC3KbAJYj5xXbEvcse3JL7J69jyo9EjN+3fkdRpGdaebVPtJ gvge8Of9xdqhu4ruDUrXLtOhly39eJNgQuZp4IaSLE+7uSWXfPbUXte0KdBVEwvLKobTzVjBfn0 xA5B6HQSvB6Jazb6SxWSGLE+lYFDlPIQdF79sOxj2e10qYxDDVY3te0rhlXJ96j6aAtZHe4z5x7 Xu2D+JHnnr5aRg2XxLNx2zE4tc/6TsbAe2E3UD2sKbf10bkE X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Move existing register definitions to mdss.xml and use generated defines for registers access instead of hand-coding everything in the source file. Signed-off-by: Dmitry Baryshkov Reviewed-by: Abhinav Kumar --- drivers/gpu/drm/msm/msm_mdss.c | 35 +++++++++++-----------= ---- drivers/gpu/drm/msm/registers/display/mdss.xml | 6 +++++ 2 files changed, 21 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c index faa88fd6eb4d..ca9b7f953ac4 100644 --- a/drivers/gpu/drm/msm/msm_mdss.c +++ b/drivers/gpu/drm/msm/msm_mdss.c @@ -19,13 +19,7 @@ #include "msm_mdss.h" #include "msm_kms.h" =20 -#define HW_REV 0x0 -#define HW_INTR_STATUS 0x0010 - -#define UBWC_DEC_HW_VERSION 0x58 -#define UBWC_STATIC 0x144 -#define UBWC_CTRL_2 0x150 -#define UBWC_PREDICTION_MODE 0x154 +#include =20 #define MIN_IB_BW 400000000UL /* Min ib vote 400MB */ =20 @@ -83,7 +77,7 @@ static void msm_mdss_irq(struct irq_desc *desc) =20 chained_irq_enter(chip, desc); =20 - interrupts =3D readl_relaxed(msm_mdss->mmio + HW_INTR_STATUS); + interrupts =3D readl_relaxed(msm_mdss->mmio + REG_MDSS_HW_INTR_STATUS); =20 while (interrupts) { irq_hw_number_t hwirq =3D fls(interrupts) - 1; @@ -173,7 +167,7 @@ static void msm_mdss_setup_ubwc_dec_20(struct msm_mdss = *msm_mdss) { const struct msm_mdss_data *data =3D msm_mdss->mdss_data; =20 - writel_relaxed(data->ubwc_static, msm_mdss->mmio + UBWC_STATIC); + writel_relaxed(data->ubwc_static, msm_mdss->mmio + REG_MDSS_UBWC_STATIC); } =20 static void msm_mdss_setup_ubwc_dec_30(struct msm_mdss *msm_mdss) @@ -189,7 +183,7 @@ static void msm_mdss_setup_ubwc_dec_30(struct msm_mdss = *msm_mdss) if (data->ubwc_enc_version =3D=3D UBWC_1_0) value |=3D BIT(8); =20 - writel_relaxed(value, msm_mdss->mmio + UBWC_STATIC); + writel_relaxed(value, msm_mdss->mmio + REG_MDSS_UBWC_STATIC); } =20 static void msm_mdss_setup_ubwc_dec_40(struct msm_mdss *msm_mdss) @@ -200,21 +194,22 @@ static void msm_mdss_setup_ubwc_dec_40(struct msm_mds= s *msm_mdss) (data->highest_bank_bit & 0x7) << 4 | (data->macrotile_mode & 0x1) << 12; =20 - writel_relaxed(value, msm_mdss->mmio + UBWC_STATIC); + writel_relaxed(value, msm_mdss->mmio + REG_MDSS_UBWC_STATIC); =20 if (data->ubwc_enc_version =3D=3D UBWC_3_0) { - writel_relaxed(1, msm_mdss->mmio + UBWC_CTRL_2); - writel_relaxed(0, msm_mdss->mmio + UBWC_PREDICTION_MODE); + writel_relaxed(1, msm_mdss->mmio + REG_MDSS_UBWC_CTRL_2); + writel_relaxed(0, msm_mdss->mmio + REG_MDSS_UBWC_PREDICTION_MODE); } else { if (data->ubwc_dec_version =3D=3D UBWC_4_3) - writel_relaxed(3, msm_mdss->mmio + UBWC_CTRL_2); + writel_relaxed(3, msm_mdss->mmio + REG_MDSS_UBWC_CTRL_2); else - writel_relaxed(2, msm_mdss->mmio + UBWC_CTRL_2); - writel_relaxed(1, msm_mdss->mmio + UBWC_PREDICTION_MODE); + writel_relaxed(2, msm_mdss->mmio + REG_MDSS_UBWC_CTRL_2); + writel_relaxed(1, msm_mdss->mmio + REG_MDSS_UBWC_PREDICTION_MODE); } } =20 -#define MDSS_HW_MAJ_MIN GENMASK(31, 16) +#define MDSS_HW_MAJ_MIN \ + (MDSS_HW_VERSION_MAJOR__MASK | MDSS_HW_VERSION_MINOR__MASK) =20 #define MDSS_HW_MSM8996 0x1007 #define MDSS_HW_MSM8937 0x100e @@ -235,7 +230,7 @@ static const struct msm_mdss_data *msm_mdss_generate_md= p5_mdss_data(struct msm_m if (!data) return NULL; =20 - hw_rev =3D readl_relaxed(mdss->mmio + HW_REV); + hw_rev =3D readl_relaxed(mdss->mmio + REG_MDSS_HW_VERSION); hw_rev =3D FIELD_GET(MDSS_HW_MAJ_MIN, hw_rev); =20 if (hw_rev =3D=3D MDSS_HW_MSM8996 || @@ -334,9 +329,9 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss) dev_err(msm_mdss->dev, "Unsupported UBWC decoder version %x\n", msm_mdss->mdss_data->ubwc_dec_version); dev_err(msm_mdss->dev, "HW_REV: 0x%x\n", - readl_relaxed(msm_mdss->mmio + HW_REV)); + readl_relaxed(msm_mdss->mmio + REG_MDSS_HW_VERSION)); dev_err(msm_mdss->dev, "UBWC_DEC_HW_VERSION: 0x%x\n", - readl_relaxed(msm_mdss->mmio + UBWC_DEC_HW_VERSION)); + readl_relaxed(msm_mdss->mmio + REG_MDSS_UBWC_DEC_HW_VERSION)); break; } =20 diff --git a/drivers/gpu/drm/msm/registers/display/mdss.xml b/drivers/gpu/d= rm/msm/registers/display/mdss.xml index 9354cfffb730..ac85caf1575c 100644 --- a/drivers/gpu/drm/msm/registers/display/mdss.xml +++ b/drivers/gpu/drm/msm/registers/display/mdss.xml @@ -18,6 +18,12 @@ xsi:schemaLocation=3D"https://gitlab.freedesktop.org/fre= edreno/ rules-fd.xsd"> + + + + + + =20 --=20 2.39.5 From nobody Mon Feb 9 10:49:46 2026 Received: from mail-lf1-f49.google.com (mail-lf1-f49.google.com [209.85.167.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1D19615C13A for ; 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a=openpgp-sha256; l=5389; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=utH3zMLcvKLREFFdRj1W6cb06ULAA1VlL6GfopIfnMQ=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBm7oEfpeo0nvjCbwL2dXM/STLppUW5swOrto7k9 XdHqOo7RduJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZu6BHwAKCRCLPIo+Aiko 1VCqB/9LxaTlULqdwKDcuNwoJVeE49D/XErOIzKSH73pAJu7Mpe32GRuPRCDmOlTPEkxRsso+i9 l45NWc0w56sxH4PhPj7k7kb0enJOA+mF/4csROdGXG1mey2JkQ91evsX+gAdUUDJATv5tyYtKzM fclXMaHCMl8iadQpu2K9zV8c0sC7UNmbZWe5jKzuSAMeHk0kSGSt8qL2k7tKzMYIU+9slUTgemN CijIzfNW8lFkY7Ozx/N1qhjw5pX/BV2DBKRhlzyRhPJHkBPUmT9mSSbq87sQGaNNXSm6GPsz2ZS bj4qTK+Ar4E7IToM2yyfb/NxaA1DtYwZAlR7ZT1CLTc9cG0U X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Rather than hand-coding UBWC_STATIC value calculation, define corresponding bitfields and use them to setup the register value. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/msm_mdss.c | 36 +++++++++++++++-------= ---- drivers/gpu/drm/msm/msm_mdss.h | 3 ++- drivers/gpu/drm/msm/registers/display/mdss.xml | 11 +++++++- 3 files changed, 33 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c index ca9b7f953ac4..7704e1c9eb2a 100644 --- a/drivers/gpu/drm/msm/msm_mdss.c +++ b/drivers/gpu/drm/msm/msm_mdss.c @@ -173,15 +173,17 @@ static void msm_mdss_setup_ubwc_dec_20(struct msm_mds= s *msm_mdss) static void msm_mdss_setup_ubwc_dec_30(struct msm_mdss *msm_mdss) { const struct msm_mdss_data *data =3D msm_mdss->mdss_data; - u32 value =3D (data->ubwc_swizzle & 0x1) | - (data->highest_bank_bit & 0x3) << 4 | - (data->macrotile_mode & 0x1) << 12; + u32 value =3D MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle & 0x1) | + MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit); + + if (data->macrotile_mode) + value |=3D MDSS_UBWC_STATIC_MACROTILE_MODE; =20 if (data->ubwc_enc_version =3D=3D UBWC_3_0) - value |=3D BIT(10); + value |=3D MDSS_UBWC_STATIC_UNKNOWN_10; =20 if (data->ubwc_enc_version =3D=3D UBWC_1_0) - value |=3D BIT(8); + value |=3D MDSS_UBWC_STATIC_UNKNOWN_8; =20 writel_relaxed(value, msm_mdss->mmio + REG_MDSS_UBWC_STATIC); } @@ -189,10 +191,14 @@ static void msm_mdss_setup_ubwc_dec_30(struct msm_mds= s *msm_mdss) static void msm_mdss_setup_ubwc_dec_40(struct msm_mdss *msm_mdss) { const struct msm_mdss_data *data =3D msm_mdss->mdss_data; - u32 value =3D (data->ubwc_swizzle & 0x7) | - (data->ubwc_static & 0x1) << 3 | - (data->highest_bank_bit & 0x7) << 4 | - (data->macrotile_mode & 0x1) << 12; + u32 value =3D MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle) | + MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit); + + if (data->unknown_3) + value |=3D MDSS_UBWC_STATIC_UNKNOWN_3; + + if (data->macrotile_mode) + value |=3D MDSS_UBWC_STATIC_MACROTILE_MODE; =20 writel_relaxed(value, msm_mdss->mmio + REG_MDSS_UBWC_STATIC); =20 @@ -580,7 +586,7 @@ static const struct msm_mdss_data sc7280_data =3D { .ubwc_enc_version =3D UBWC_3_0, .ubwc_dec_version =3D UBWC_4_0, .ubwc_swizzle =3D 6, - .ubwc_static =3D 1, + .unknown_3 =3D true, .highest_bank_bit =3D 1, .macrotile_mode =3D 1, .reg_bus_bw =3D 74000, @@ -598,7 +604,7 @@ static const struct msm_mdss_data sc8280xp_data =3D { .ubwc_enc_version =3D UBWC_4_0, .ubwc_dec_version =3D UBWC_4_0, .ubwc_swizzle =3D 6, - .ubwc_static =3D 1, + .unknown_3 =3D true, .highest_bank_bit =3D 3, .macrotile_mode =3D 1, .reg_bus_bw =3D 76800, @@ -661,7 +667,7 @@ static const struct msm_mdss_data sm8250_data =3D { .ubwc_enc_version =3D UBWC_4_0, .ubwc_dec_version =3D UBWC_4_0, .ubwc_swizzle =3D 6, - .ubwc_static =3D 1, + .unknown_3 =3D true, /* TODO: highest_bank_bit =3D 2 for LP_DDR4 */ .highest_bank_bit =3D 3, .macrotile_mode =3D 1, @@ -672,7 +678,7 @@ static const struct msm_mdss_data sm8350_data =3D { .ubwc_enc_version =3D UBWC_4_0, .ubwc_dec_version =3D UBWC_4_0, .ubwc_swizzle =3D 6, - .ubwc_static =3D 1, + .unknown_3 =3D true, /* TODO: highest_bank_bit =3D 2 for LP_DDR4 */ .highest_bank_bit =3D 3, .macrotile_mode =3D 1, @@ -683,7 +689,7 @@ static const struct msm_mdss_data sm8550_data =3D { .ubwc_enc_version =3D UBWC_4_0, .ubwc_dec_version =3D UBWC_4_3, .ubwc_swizzle =3D 6, - .ubwc_static =3D 1, + .unknown_3 =3D true, /* TODO: highest_bank_bit =3D 2 for LP_DDR4 */ .highest_bank_bit =3D 3, .macrotile_mode =3D 1, @@ -694,7 +700,7 @@ static const struct msm_mdss_data x1e80100_data =3D { .ubwc_enc_version =3D UBWC_4_0, .ubwc_dec_version =3D UBWC_4_3, .ubwc_swizzle =3D 6, - .ubwc_static =3D 1, + .unknown_3 =3D true, /* TODO: highest_bank_bit =3D 2 for LP_DDR4 */ .highest_bank_bit =3D 3, .macrotile_mode =3D 1, diff --git a/drivers/gpu/drm/msm/msm_mdss.h b/drivers/gpu/drm/msm/msm_mdss.h index 3afef4b1786d..69095c18ab4a 100644 --- a/drivers/gpu/drm/msm/msm_mdss.h +++ b/drivers/gpu/drm/msm/msm_mdss.h @@ -13,7 +13,8 @@ struct msm_mdss_data { u32 ubwc_swizzle; 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Sat, 21 Sep 2024 01:17:43 -0700 (PDT) Received: from umbar.lan ([192.130.178.90]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-536870968d1sm2466380e87.175.2024.09.21.01.17.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 21 Sep 2024 01:17:42 -0700 (PDT) From: Dmitry Baryshkov Date: Sat, 21 Sep 2024 11:17:32 +0300 Subject: [PATCH 4/4] drm/msm/mdss: reuse defined bitfields for UBWC 2.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240921-msm-mdss-ubwc-v1-4-411dcf309d05@linaro.org> References: <20240921-msm-mdss-ubwc-v1-0-411dcf309d05@linaro.org> In-Reply-To: <20240921-msm-mdss-ubwc-v1-0-411dcf309d05@linaro.org> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2564; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=ScCRd7+z7cwAGX0LzQnkBaj1sUTBN7g+ylhI1wBf8No=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBm7oEfFUNz63SZIIIv4PSfaBvDuI15ysOw/396a 6UffauUniqJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZu6BHwAKCRCLPIo+Aiko 1dLUCACLFFbWklq276VM0/8R0H4sDEzmkz4gKnwfDpRPWAfsBCwUuuo+yznN+gqcNrh5FQKRyJq 4a6Lq5j9qgRAt92C9N3elKB+wQXyIy8k06pGS/gL/eWnx/2YpQJ1seTn0GcN9iEOEHyv2petgEK uT1h8YyflDQfylQpRjWCdItA7GaFNpShxp4W2cqcCf5LyFC7c3I1Pcvquel4wv1n15N8mc5xtvt PuSQ22r/G0Mlmt8BKBd0jpa/dGfK6YwDmSPZsYy0whHFOajAVpZXDaQBoGunDeJyGmpA0tRhLGr BQfl+po4ZAG2aTUqjR8nNkWJlMSoXHaIS+8hTXCMv7Qr31zK X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Follow other msm_mdss_setup_ubwc_dec_nn functions and use individual bits instead of just specifying the value to be programmed to the UBWC_STATIC register. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/msm_mdss.c | 17 +++++++++++++---- drivers/gpu/drm/msm/msm_mdss.h | 1 - 2 files changed, 13 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c index 7704e1c9eb2a..0b49187c52de 100644 --- a/drivers/gpu/drm/msm/msm_mdss.c +++ b/drivers/gpu/drm/msm/msm_mdss.c @@ -166,8 +166,16 @@ static int _msm_mdss_irq_domain_add(struct msm_mdss *m= sm_mdss) static void msm_mdss_setup_ubwc_dec_20(struct msm_mdss *msm_mdss) { const struct msm_mdss_data *data =3D msm_mdss->mdss_data; + u32 value =3D MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle) | + MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit); =20 - writel_relaxed(data->ubwc_static, msm_mdss->mmio + REG_MDSS_UBWC_STATIC); + if (data->unknown_3) + value |=3D MDSS_UBWC_STATIC_UNKNOWN_3; + + if (data->ubwc_enc_version =3D=3D UBWC_1_0) + value |=3D MDSS_UBWC_STATIC_UNKNOWN_8; + + writel_relaxed(value, msm_mdss->mmio + REG_MDSS_UBWC_STATIC); } =20 static void msm_mdss_setup_ubwc_dec_30(struct msm_mdss *msm_mdss) @@ -577,7 +585,8 @@ static const struct msm_mdss_data qcm2290_data =3D { static const struct msm_mdss_data sc7180_data =3D { .ubwc_enc_version =3D UBWC_2_0, .ubwc_dec_version =3D UBWC_2_0, - .ubwc_static =3D 0x1e, + .ubwc_swizzle =3D 6, + .unknown_3 =3D true, .highest_bank_bit =3D 0x1, .reg_bus_bw =3D 76800, }; @@ -628,7 +637,7 @@ static const struct msm_mdss_data sm6350_data =3D { .ubwc_enc_version =3D UBWC_2_0, .ubwc_dec_version =3D UBWC_2_0, .ubwc_swizzle =3D 6, - .ubwc_static =3D 0x1e, + .unknown_3 =3D true, .highest_bank_bit =3D 1, .reg_bus_bw =3D 76800, }; @@ -651,7 +660,7 @@ static const struct msm_mdss_data sm6115_data =3D { .ubwc_enc_version =3D UBWC_1_0, .ubwc_dec_version =3D UBWC_2_0, .ubwc_swizzle =3D 7, - .ubwc_static =3D 0x11f, + .unknown_3 =3D true, .highest_bank_bit =3D 0x1, .reg_bus_bw =3D 76800, }; diff --git a/drivers/gpu/drm/msm/msm_mdss.h b/drivers/gpu/drm/msm/msm_mdss.h index 69095c18ab4a..521d4e6b8043 100644 --- a/drivers/gpu/drm/msm/msm_mdss.h +++ b/drivers/gpu/drm/msm/msm_mdss.h @@ -11,7 +11,6 @@ struct msm_mdss_data { /* can be read from register 0x58 */ u32 ubwc_dec_version; u32 ubwc_swizzle; - u32 ubwc_static; u32 highest_bank_bit; bool unknown_3; bool macrotile_mode; --=20 2.39.5