From nobody Fri Nov 29 12:49:18 2024 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5D663183CA7; Fri, 20 Sep 2024 15:59:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726847983; cv=none; b=DzrRyBTLPfRsV2U4ZyOGOur1a3KBCTeJT+372GDNxwt+zTjIBz15ylE9JZGBybT9JbIjIWbYFLhJzqtt3lpF6His3mU2UrRWE8owPRVl/zhVUWH6Qovk47qlBHh9oySJoAWMNbESg6OULsLmpf/1FdYCxaX4PE2LMlXCJIiAQ7w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726847983; c=relaxed/simple; bh=As++/LNcQAm3hNuvrtPvYljouNsNhpeBScZck/Ccpuc=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=rGVpzE8e+I5u/EwKIBbHYN9hqOQ5/XNWI1tzY1z7jh5812p2CWCz+KMe8MEKWZv7ZHdtwJP0aCppLqRKVbbmL05VowUXzbdnkjek5s4vqICaapFatYAE7tCXHJHVT8Sc75LqKq9HU9SmwxwPC+m0HfJ9gPZhVa74eLu7zqmeffI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=aTTNw+Ow; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="aTTNw+Ow" Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 48K8Kepf010967; Fri, 20 Sep 2024 15:59:26 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= Vws35iDyMsqwIxaWK55MmeMrXTFYsyqDwSO6u3RYfec=; b=aTTNw+Owu8fOTwJu wmUmEFYoMDf3Vusv+s/kxcwdnI6m+8dXjzHM/PJKtc2ajDBM7vj6ik/ZBecAqMkY AeYyFXWPD6vRyFHwZKzaD2MMpGo1FKJLMRH21ZCufPpCNQliFsxo7LEUhS24Dv3L r0HulbzV2bphvtPHpeTDzcioP6BMUua96D9XZhHzSipJUTsuKsVk+f+m4f9Jj9Qv FDCF7L+1v3ME7c7FPAUtX6wxR4naLovtBry0YKhVu727bYVLnEhqWZty27Y5fgv1 t6+q4Sin1jHjRooXFxiEBgibfkNkPoRPVYoDetnRlmFJNTUMN+qEis/L4B08j45s QhURnw== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 41n4hfsuj7-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 20 Sep 2024 15:59:25 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 48KFxO61018070 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 20 Sep 2024 15:59:24 GMT Received: from hu-bibekkum-hyd.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 20 Sep 2024 08:59:20 -0700 From: Bibek Kumar Patro To: , , , , , , , , , CC: , , , , Subject: [PATCH v15 4/5] iommu/arm-smmu: introduction of ACTLR for custom prefetcher settings Date: Fri, 20 Sep 2024 21:28:12 +0530 Message-ID: <20240920155813.3434021-5-quic_bibekkum@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240920155813.3434021-1-quic_bibekkum@quicinc.com> References: <20240920155813.3434021-1-quic_bibekkum@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: Ui4LfD2vUObvyMwnETtIc4wJEA0JkrAo X-Proofpoint-ORIG-GUID: Ui4LfD2vUObvyMwnETtIc4wJEA0JkrAo X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 clxscore=1015 phishscore=0 malwarescore=0 mlxlogscore=999 mlxscore=0 impostorscore=0 adultscore=0 suspectscore=0 lowpriorityscore=0 spamscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2408220000 definitions=main-2409200117 Content-Type: text/plain; charset="utf-8" Currently in Qualcomm SoCs the default prefetch is set to 1 which allows the TLB to fetch just the next page table. MMU-500 features ACTLR register which is implementation defined and is used for Qualcomm SoCs to have a custom prefetch setting enabling TLB to prefetch the next set of page tables accordingly allowing for faster translations. ACTLR value is unique for each SMR (Stream matching register) and stored in a pre-populated table. This value is set to the register during context bank initialisation. Signed-off-by: Bibek Kumar Patro --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 26 ++++++++++++++++++++++ drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h | 1 + 2 files changed, 27 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm= /arm-smmu/arm-smmu-qcom.c index 38ac9cab763b..4ac272d05843 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -252,6 +252,20 @@ static bool qcom_adreno_can_do_ttbr1(struct arm_smmu_d= evice *smmu) return true; } +static void qcom_smmu_set_actlr_dev(struct device *dev, struct arm_smmu_de= vice *smmu, int cbndx, + const struct of_device_id *client_match) +{ + const struct of_device_id *match =3D + of_match_device(client_match, dev); + + if (!match) { + dev_notice(dev, "no ACTLR settings present\n"); + return; + } + + arm_smmu_cb_write(smmu, cbndx, ARM_SMMU_CB_ACTLR, (u64)match->data); +} + static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_doma= in, struct io_pgtable_cfg *pgtbl_cfg, struct device *dev) { @@ -316,8 +330,20 @@ static const struct of_device_id qcom_smmu_client_of_m= atch[] __maybe_unused =3D { static int qcom_smmu_init_context(struct arm_smmu_domain *smmu_domain, struct io_pgtable_cfg *pgtbl_cfg, struct device *dev) { + struct arm_smmu_device *smmu =3D smmu_domain->smmu; + struct qcom_smmu *qsmmu =3D to_qcom_smmu(smmu); + const struct of_device_id *client_match; + int cbndx =3D smmu_domain->cfg.cbndx; + smmu_domain->cfg.flush_walk_prefer_tlbiasid =3D true; + client_match =3D qsmmu->data->client_match; + + if (!client_match) + return 0; + + qcom_smmu_set_actlr_dev(dev, smmu, cbndx, client_match); + return 0; } diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h b/drivers/iommu/arm= /arm-smmu/arm-smmu-qcom.h index b55cd3e3ae48..8addd453f5f1 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h @@ -28,6 +28,7 @@ struct qcom_smmu_match_data { const struct qcom_smmu_config *cfg; const struct arm_smmu_impl *impl; const struct arm_smmu_impl *adreno_impl; + const struct of_device_id * const client_match; }; irqreturn_t qcom_smmu_context_fault(int irq, void *dev); -- 2.34.1