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[2001:b400:e35c:9cc2:447a:d760:d4f6:1f4]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7db4998b4f3sm10636251a12.72.2024.09.20.03.18.32 (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 20 Sep 2024 03:18:33 -0700 (PDT) From: warp5tw@gmail.com X-Google-Original-From: kfting@nuvoton.com To: avifishman70@gmail.com, tmaimon77@gmail.com, tali.perry1@gmail.com, venture@google.com, yuenn@google.com, benjaminfair@google.com, andi.shyti@kernel.org, andriy.shevchenko@linux.intel.com, wsa@kernel.org, rand.sec96@gmail.com, wsa+renesas@sang-engineering.com, warp5tw@gmail.com, tali.perry@nuvoton.com, Avi.Fishman@nuvoton.com, tomer.maimon@nuvoton.com, KWLIU@nuvoton.com, JJLIU0@nuvoton.com, kfting@nuvoton.com Cc: openbmc@lists.ozlabs.org, linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 1/6] i2c: npcm: correct the read/write operation procedure Date: Fri, 20 Sep 2024 18:18:15 +0800 Message-Id: <20240920101820.44850-2-kfting@nuvoton.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240920101820.44850-1-kfting@nuvoton.com> References: <20240920101820.44850-1-kfting@nuvoton.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Tyrone Ting From: Tyrone Ting Originally the driver uses the XMIT bit in SMBnST register to decide the upcoming i2c transaction. If XMIT bit is 1, then it will be an i2c write operation. If it's 0, then a read operation will be executed. In slave mode the XMIT bit can simply be used directly to set the state. XMIT bit can be used as an indication to the current state of the state machine during slave operation. (meaning XMIT =3D 1 during writing and XMIT =3D 0 during reading). In master operation XMIT is valid only if there are no bus errors. For example: in a multi master where the same module is switching from master to slave at runtime, and there are collisions, the XMIT bit cannot be trusted. However the maser already "knows" what the bus state is, so this bit is not needed and the driver can just track what it is currently doing. Signed-off-by: Tyrone Ting Reviewed-by: Tali Perry --- drivers/i2c/busses/i2c-npcm7xx.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/drivers/i2c/busses/i2c-npcm7xx.c b/drivers/i2c/busses/i2c-npcm= 7xx.c index bbcb4d6668ce..2b76dbfba438 100644 --- a/drivers/i2c/busses/i2c-npcm7xx.c +++ b/drivers/i2c/busses/i2c-npcm7xx.c @@ -1628,13 +1628,10 @@ static void npcm_i2c_irq_handle_sda(struct npcm_i2c= *bus, u8 i2cst) npcm_i2c_wr_byte(bus, bus->dest_addr | BIT(0)); /* SDA interrupt, after start\restart */ } else { - if (NPCM_I2CST_XMIT & i2cst) { - bus->operation =3D I2C_WRITE_OPER; + if (bus->operation =3D=3D I2C_WRITE_OPER) npcm_i2c_irq_master_handler_write(bus); - } else { - bus->operation =3D I2C_READ_OPER; + else if (bus->operation =3D=3D I2C_READ_OPER) npcm_i2c_irq_master_handler_read(bus); - } } } =20 --=20 2.34.1