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(unknown [58.22.7.114]) by gzsmtp3 (Coremail) with SMTP id sigvCgCHF5n3MO1mlL4ZAA--.3563S2; Fri, 20 Sep 2024 16:23:23 +0800 (CST) From: Andy Yan To: heiko@sntech.de Cc: hjc@rock-chips.com, krzk+dt@kernel.org, robh@kernel.org, conor+dt@kernel.org, s.hauer@pengutronix.de, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, derek.foreman@collabora.com, minhuadotchen@gmail.com, detlev.casanova@collabora.com, Andy Yan Subject: [PATCH v3 15/15] drm/rockchip: vop2: Add support for rk3576 Date: Fri, 20 Sep 2024 16:23:17 +0800 Message-ID: <20240920082318.7012-1-andyshrk@163.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240920081626.6433-1-andyshrk@163.com> References: <20240920081626.6433-1-andyshrk@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: sigvCgCHF5n3MO1mlL4ZAA--.3563S2 X-Coremail-Antispam: 1Uf129KBjvAXoWDCFW3Jry5CFyDZrW8ArykGrg_yoW7Jr17Ao W3CFnIqryxt34Sk395Gr17XryxWF4vkan7ur1IyFy2k3y3X3y5Cryxt3ZIqF4ayw45CFWr A3sYq3WrZFWfZw1xn29KB7ZKAUJUUUU8529EdanIXcx71UUUUU7v73VFW2AGmfu7bjvjm3 AaLaJ3UbIYCTnIWIevJa73UjIFyTuYvjxU44rWUUUUU X-CM-SenderInfo: 5dqg52xkunqiywtou0bp/1tbiqRxgXmVODBHrRAAAsS Content-Type: text/plain; charset="utf-8" From: Andy Yan VOP2 on rk3576: Three video ports: VP0 Max 4096x2160 VP1 Max 2560x1600 VP2 Max 1920x1080 2 4K Cluster windows with AFBC/RFBC, line RGB and YUV 4 Esmart windows with line RGB/YUV support: Esmart0/1: 4K Esmart2/3: 2k, or worked together as a single 4K plane at shared line buffer mode. Compared to the previous VOP, another difference is that each VP has its own independent vsync interrupt number. Signed-off-by: Andy Yan --- Changes in v3: - Share the alpha setup function with rk3568 - recoder the code block by soc Changes in v2: - Add platform specific callback drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 144 +++- drivers/gpu/drm/rockchip/rockchip_drm_vop2.h | 87 +++ drivers/gpu/drm/rockchip/rockchip_vop2_reg.c | 780 ++++++++++++++++++- 3 files changed, 956 insertions(+), 55 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm= /rockchip/rockchip_drm_vop2.c index 84c67f5d267f..e25904e4f97b 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -1187,6 +1187,9 @@ static void vop2_plane_atomic_update(struct drm_plane= *plane, &fb->format->format, afbc_en ? "AFBC" : "", &yrgb_mst); =20 + if (vop2->version >=3D VOP_VERSION_RK3576) + vop2_win_write(win, VOP2_WIN_VP_SEL, vp->id); + if (vop2_cluster_window(win)) vop2_win_write(win, VOP2_WIN_AFBC_HALF_BLOCK_EN, half_block_en); =20 @@ -1251,6 +1254,11 @@ static void vop2_plane_atomic_update(struct drm_plan= e *plane, else vop2_win_write(win, VOP2_WIN_AFBC_BLOCK_SPLIT_EN, 0); =20 + if (vop2->version >=3D VOP_VERSION_RK3576) { + vop2_win_write(win, VOP2_WIN_AFBC_PLD_OFFSET_EN, 1); + vop2_win_write(win, VOP2_WIN_AFBC_PLD_OFFSET, yrgb_mst); + } + transform_offset =3D vop2_afbc_transform_offset(pstate, half_block_en); vop2_win_write(win, VOP2_WIN_AFBC_HDR_PTR, yrgb_mst); vop2_win_write(win, VOP2_WIN_AFBC_PIC_SIZE, act_info); @@ -1919,6 +1927,56 @@ static const struct drm_crtc_funcs vop2_crtc_funcs = =3D { .late_register =3D vop2_crtc_late_register, }; =20 +static irqreturn_t rk3576_vp_isr(int irq, void *data) +{ + struct vop2_video_port *vp =3D data; + struct vop2 *vop2 =3D vp->vop2; + struct drm_crtc *crtc =3D &vp->crtc; + uint32_t irqs; + int ret =3D IRQ_NONE; + + /* + * The irq is shared with the iommu. If the runtime-pm state of the + * vop2-device is disabled the irq has to be targeted at the iommu. + */ + if (!pm_runtime_get_if_in_use(vop2->dev)) + return IRQ_NONE; + + irqs =3D vop2_readl(vop2, RK3568_VP_INT_STATUS(vp->id)); + vop2_writel(vop2, RK3568_VP_INT_CLR(vp->id), irqs << 16 | irqs); + + if (irqs & VP_INT_DSP_HOLD_VALID) { + complete(&vp->dsp_hold_completion); + ret =3D IRQ_HANDLED; + } + + if (irqs & VP_INT_FS_FIELD) { + drm_crtc_handle_vblank(crtc); + spin_lock(&crtc->dev->event_lock); + if (vp->event) { + u32 val =3D vop2_readl(vop2, RK3568_REG_CFG_DONE); + + if (!(val & BIT(vp->id))) { + drm_crtc_send_vblank_event(crtc, vp->event); + vp->event =3D NULL; + drm_crtc_vblank_put(crtc); + } + } + spin_unlock(&crtc->dev->event_lock); + + ret =3D IRQ_HANDLED; + } + + if (irqs & VP_INT_POST_BUF_EMPTY) { + drm_err_ratelimited(vop2->drm, "POST_BUF_EMPTY irq err at vp%d\n", vp->i= d); + ret =3D IRQ_HANDLED; + } + + pm_runtime_put(vop2->dev); + + return ret; +} + static irqreturn_t vop2_isr(int irq, void *data) { struct vop2 *vop2 =3D data; @@ -1934,41 +1992,43 @@ static irqreturn_t vop2_isr(int irq, void *data) if (!pm_runtime_get_if_in_use(vop2->dev)) return IRQ_NONE; =20 - for (i =3D 0; i < vop2_data->nr_vps; i++) { - struct vop2_video_port *vp =3D &vop2->vps[i]; - struct drm_crtc *crtc =3D &vp->crtc; - u32 irqs; + if (vop2->version < VOP_VERSION_RK3576) { + for (i =3D 0; i < vop2_data->nr_vps; i++) { + struct vop2_video_port *vp =3D &vop2->vps[i]; + struct drm_crtc *crtc =3D &vp->crtc; + u32 irqs; =20 - irqs =3D vop2_readl(vop2, RK3568_VP_INT_STATUS(vp->id)); - vop2_writel(vop2, RK3568_VP_INT_CLR(vp->id), irqs << 16 | irqs); + irqs =3D vop2_readl(vop2, RK3568_VP_INT_STATUS(vp->id)); + vop2_writel(vop2, RK3568_VP_INT_CLR(vp->id), irqs << 16 | irqs); =20 - if (irqs & VP_INT_DSP_HOLD_VALID) { - complete(&vp->dsp_hold_completion); - ret =3D IRQ_HANDLED; - } - - if (irqs & VP_INT_FS_FIELD) { - drm_crtc_handle_vblank(crtc); - spin_lock(&crtc->dev->event_lock); - if (vp->event) { - u32 val =3D vop2_readl(vop2, RK3568_REG_CFG_DONE); + if (irqs & VP_INT_DSP_HOLD_VALID) { + complete(&vp->dsp_hold_completion); + ret =3D IRQ_HANDLED; + } =20 - if (!(val & BIT(vp->id))) { - drm_crtc_send_vblank_event(crtc, vp->event); - vp->event =3D NULL; - drm_crtc_vblank_put(crtc); + if (irqs & VP_INT_FS_FIELD) { + drm_crtc_handle_vblank(crtc); + spin_lock(&crtc->dev->event_lock); + if (vp->event) { + u32 val =3D vop2_readl(vop2, RK3568_REG_CFG_DONE); + + if (!(val & BIT(vp->id))) { + drm_crtc_send_vblank_event(crtc, vp->event); + vp->event =3D NULL; + drm_crtc_vblank_put(crtc); + } } - } - spin_unlock(&crtc->dev->event_lock); + spin_unlock(&crtc->dev->event_lock); =20 - ret =3D IRQ_HANDLED; - } + ret =3D IRQ_HANDLED; + } =20 - if (irqs & VP_INT_POST_BUF_EMPTY) { - drm_err_ratelimited(vop2->drm, - "POST_BUF_EMPTY irq err at vp%d\n", - vp->id); - ret =3D IRQ_HANDLED; + if (irqs & VP_INT_POST_BUF_EMPTY) { + drm_err_ratelimited(vop2->drm, + "POST_BUF_EMPTY irq err at vp%d\n", + vp->id); + ret =3D IRQ_HANDLED; + } } } =20 @@ -2455,6 +2515,32 @@ static int vop2_bind(struct device *dev, struct devi= ce *master, void *data) if (ret) return ret; =20 + if (vop2->version >=3D VOP_VERSION_RK3576) { + struct drm_crtc *crtc; + + drm_for_each_crtc(crtc, drm) { + struct vop2_video_port *vp =3D to_vop2_video_port(crtc); + int vp_irq; + const char *irq_name =3D devm_kasprintf(dev, GFP_KERNEL, "vop-vp%d", vp= ->id); + + if (!irq_name) + return -ENOMEM; + + vp_irq =3D platform_get_irq_byname(pdev, irq_name); + if (vp_irq < 0) { + DRM_DEV_ERROR(dev, "cannot find irq for vop2 vp%d\n", vp->id); + return vp_irq; + } + + ret =3D devm_request_irq(dev, vp_irq, rk3576_vp_isr, IRQF_SHARED, irq_n= ame, + vp); + if (ret) { + DRM_DEV_ERROR(dev, "request irq for vop2 vp%d failed\n", vp->id); + return ret; + } + } + } + ret =3D vop2_find_rgb_encoder(vop2); if (ret >=3D 0) { vop2->rgb =3D rockchip_rgb_init(dev, &vop2->vps[ret].crtc, diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h b/drivers/gpu/drm= /rockchip/rockchip_drm_vop2.h index 064167afebf4..e2485c2285ad 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h @@ -44,6 +44,13 @@ enum win_dly_mode { VOP2_DLY_MODE_MAX, }; =20 +enum vop2_dly_module { + VOP2_DLY_WIN, /** Win delay cycle for this VP */ + VOP2_DLY_LAYER_MIX, /** Layer Mix delay cycle for this VP */ + VOP2_DLY_HDR_MIX, /** HDR delay cycle for this VP */ + VOP2_DLY_MAX, +}; + enum vop2_scale_up_mode { VOP2_SCALE_UP_NRST_NBOR, VOP2_SCALE_UP_BIL, @@ -137,16 +144,22 @@ enum vop2_win_regs { VOP2_WIN_AFBC_UV_SWAP, VOP2_WIN_AFBC_AUTO_GATING_EN, VOP2_WIN_AFBC_BLOCK_SPLIT_EN, + VOP2_WIN_AFBC_PLD_OFFSET_EN, VOP2_WIN_AFBC_PIC_VIR_WIDTH, VOP2_WIN_AFBC_TILE_NUM, VOP2_WIN_AFBC_PIC_OFFSET, VOP2_WIN_AFBC_PIC_SIZE, VOP2_WIN_AFBC_DSP_OFFSET, + VOP2_WIN_AFBC_PLD_OFFSET, VOP2_WIN_AFBC_TRANSFORM_OFFSET, VOP2_WIN_AFBC_HDR_PTR, VOP2_WIN_AFBC_HALF_BLOCK_EN, VOP2_WIN_AFBC_ROTATE_270, VOP2_WIN_AFBC_ROTATE_90, + + VOP2_WIN_VP_SEL, + VOP2_WIN_DLY_NUM, + VOP2_WIN_MAX_REG, }; =20 @@ -208,6 +221,10 @@ struct vop2_video_port_data { struct vop_rect max_output; const u8 pre_scan_max_dly[4]; unsigned int offset; + /** + * @pixel_rate: pixel per cycle + */ + u8 pixel_rate; }; =20 struct vop2_video_port { @@ -365,10 +382,13 @@ enum dst_factor_mode { #define RK3568_REG_CFG_DONE 0x000 #define RK3568_VERSION_INFO 0x004 #define RK3568_SYS_AUTO_GATING_CTRL 0x008 +#define RK3576_SYS_MMU_CTRL_IMD 0x020 #define RK3568_SYS_AXI_LUT_CTRL 0x024 #define RK3568_DSP_IF_EN 0x028 +#define RK3576_SYS_PORT_CTRL_IMD 0x028 #define RK3568_DSP_IF_CTRL 0x02c #define RK3568_DSP_IF_POL 0x030 +#define RK3576_SYS_CLUSTER_PD_CTRL_IMD 0x030 #define RK3588_SYS_PD_CTRL 0x034 #define RK3568_WB_CTRL 0x40 #define RK3568_WB_XSCAL_FACTOR 0x44 @@ -388,6 +408,55 @@ enum dst_factor_mode { #define RK3568_VP_INT_CLR(vp) (0xA4 + (vp) * 0x10) #define RK3568_VP_INT_STATUS(vp) (0xA8 + (vp) * 0x10) #define RK3568_VP_INT_RAW_STATUS(vp) (0xAC + (vp) * 0x10) +#define RK3576_WB_CTRL 0x100 +#define RK3576_WB_XSCAL_FACTOR 0x104 +#define RK3576_WB_YRGB_MST 0x108 +#define RK3576_WB_CBR_MST 0x10C +#define RK3576_WB_VIR_STRIDE 0x110 +#define RK3576_WB_TIMEOUT_CTRL 0x114 +#define RK3576_MIPI0_IF_CTRL 0x180 +#define RK3576_HDMI0_IF_CTRL 0x184 +#define RK3576_EDP0_IF_CTRL 0x188 +#define RK3576_DP0_IF_CTRL 0x18C +#define RK3576_RGB_IF_CTRL 0x194 +#define RK3576_DP1_IF_CTRL 0x1A4 +#define RK3576_DP2_IF_CTRL 0x1B0 + +/* Extra OVL register definition */ +#define RK3576_SYS_EXTRA_ALPHA_CTRL 0x500 +#define RK3576_CLUSTER0_MIX_SRC_COLOR_CTRL 0x530 +#define RK3576_CLUSTER0_MIX_DST_COLOR_CTRL 0x534 +#define RK3576_CLUSTER0_MIX_SRC_ALPHA_CTRL 0x538 +#define RK3576_CLUSTER0_MIX_DST_ALPHA_CTRL 0x53c +#define RK3576_CLUSTER1_MIX_SRC_COLOR_CTRL 0x540 +#define RK3576_CLUSTER1_MIX_DST_COLOR_CTRL 0x544 +#define RK3576_CLUSTER1_MIX_SRC_ALPHA_CTRL 0x548 +#define RK3576_CLUSTER1_MIX_DST_ALPHA_CTRL 0x54c + +/* OVL registers for Video Port definition */ +#define RK3576_OVL_CTRL(vp) (0x600 + (vp) * 0x100) +#define RK3576_OVL_LAYER_SEL(vp) (0x604 + (vp) * 0x100) +#define RK3576_OVL_MIX0_SRC_COLOR_CTRL(vp) (0x620 + (vp) * 0x100) +#define RK3576_OVL_MIX0_DST_COLOR_CTRL(vp) (0x624 + (vp) * 0x100) +#define RK3576_OVL_MIX0_SRC_ALPHA_CTRL(vp) (0x628 + (vp) * 0x100) +#define RK3576_OVL_MIX0_DST_ALPHA_CTRL(vp) (0x62C + (vp) * 0x100) +#define RK3576_OVL_MIX1_SRC_COLOR_CTRL(vp) (0x630 + (vp) * 0x100) +#define RK3576_OVL_MIX1_DST_COLOR_CTRL(vp) (0x634 + (vp) * 0x100) +#define RK3576_OVL_MIX1_SRC_ALPHA_CTRL(vp) (0x638 + (vp) * 0x100) +#define RK3576_OVL_MIX1_DST_ALPHA_CTRL(vp) (0x63C + (vp) * 0x100) +#define RK3576_OVL_MIX2_SRC_COLOR_CTRL(vp) (0x640 + (vp) * 0x100) +#define RK3576_OVL_MIX2_DST_COLOR_CTRL(vp) (0x644 + (vp) * 0x100) +#define RK3576_OVL_MIX2_SRC_ALPHA_CTRL(vp) (0x648 + (vp) * 0x100) +#define RK3576_OVL_MIX2_DST_ALPHA_CTRL(vp) (0x64C + (vp) * 0x100) +#define RK3576_EXTRA_OVL_SRC_COLOR_CTRL(vp) (0x650 + (vp) * 0x100) +#define RK3576_EXTRA_OVL_DST_COLOR_CTRL(vp) (0x654 + (vp) * 0x100) +#define RK3576_EXTRA_OVL_SRC_ALPHA_CTRL(vp) (0x658 + (vp) * 0x100) +#define RK3576_EXTRA_OVL_DST_ALPHA_CTRL(vp) (0x65C + (vp) * 0x100) +#define RK3576_OVL_HDR_SRC_COLOR_CTRL(vp) (0x660 + (vp) * 0x100) +#define RK3576_OVL_HDR_DST_COLOR_CTRL(vp) (0x664 + (vp) * 0x100) +#define RK3576_OVL_HDR_SRC_ALPHA_CTRL(vp) (0x668 + (vp) * 0x100) +#define RK3576_OVL_HDR_DST_ALPHA_CTRL(vp) (0x66C + (vp) * 0x100) +#define RK3576_OVL_BG_MIX_CTRL(vp) (0x670 + (vp) * 0x100) =20 /* Video Port registers definition */ #define RK3568_VP0_CTRL_BASE 0x0C00 @@ -469,7 +538,11 @@ enum dst_factor_mode { #define RK3568_CLUSTER_WIN_AFBCD_DSP_OFFSET 0x68 #define RK3568_CLUSTER_WIN_AFBCD_CTRL 0x6C =20 +#define RK3576_CLUSTER_WIN_AFBCD_PLD_PTR_OFFSET 0x78 + #define RK3568_CLUSTER_CTRL 0x100 +#define RK3576_CLUSTER_PORT_SEL_IMD 0x1F4 +#define RK3576_CLUSTER_DLY_NUM 0x1F8 =20 /* (E)smart register definition, offset relative to window base */ #define RK3568_SMART_CTRL0 0x00 @@ -519,6 +592,9 @@ enum dst_factor_mode { #define RK3568_SMART_REGION3_SCL_FACTOR_CBR 0xC8 #define RK3568_SMART_REGION3_SCL_OFFSET 0xCC #define RK3568_SMART_COLOR_KEY_CTRL 0xD0 +#define RK3576_SMART_ALPHA_MAP 0xD8 +#define RK3576_SMART_PORT_SEL_IMD 0xF4 +#define RK3576_SMART_DLY_NUM 0xF8 =20 /* HDR register definition */ #define RK3568_HDR_LUT_CTRL 0x2000 @@ -662,6 +738,17 @@ enum dst_factor_mode { =20 #define POLFLAG_DCLK_INV BIT(3) =20 +#define RK3576_OVL_CTRL__YUV_MODE BIT(0) +#define RK3576_OVL_BG_MIX_CTRL__BG_DLY GENMASK(31, 24) + +#define RK3576_DSP_IF_CFG_DONE_IMD BIT(31) +#define RK3576_DSP_IF_DCLK_SEL_OUT BIT(21) +#define RK3576_DSP_IF_PCLK_DIV BIT(20) +#define RK3576_DSP_IF_PIN_POL GENMASK(5, 4) +#define RK3576_DSP_IF_MUX GENMASK(3, 2) +#define RK3576_DSP_IF_CLK_OUT_EN BIT(1) +#define RK3576_DSP_IF_EN BIT(0) + enum vop2_layer_phy_id { ROCKCHIP_VOP2_CLUSTER0 =3D 0, ROCKCHIP_VOP2_CLUSTER1, diff --git a/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c b/drivers/gpu/drm= /rockchip/rockchip_vop2_reg.c index 95e31ee84f4f..91c2443567d1 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c @@ -70,6 +70,37 @@ static const uint32_t formats_cluster[] =3D { DRM_FORMAT_Y210, /* yuv422_10bit non-Linear mode only */ }; =20 +/* + * The cluster windows on rk3576 support: + * RGB: linear mode and afbc + * YUV: linear mode and rfbc + * rfbc is a rockchip defined non-linear mode, produced by + * Video decoder + */ +static const uint32_t formats_rk3576_cluster[] =3D { + DRM_FORMAT_XRGB2101010, + DRM_FORMAT_XBGR2101010, + DRM_FORMAT_ARGB2101010, + DRM_FORMAT_ABGR2101010, + DRM_FORMAT_XRGB8888, + DRM_FORMAT_ARGB8888, + DRM_FORMAT_XBGR8888, + DRM_FORMAT_ABGR8888, + DRM_FORMAT_RGB888, + DRM_FORMAT_BGR888, + DRM_FORMAT_RGB565, + DRM_FORMAT_BGR565, + DRM_FORMAT_NV12, /* yuv420_8bit linear mode, 2 plane */ + DRM_FORMAT_NV21, /* yvu420_8bit linear mode, 2 plane */ + DRM_FORMAT_NV16, /* yuv422_8bit linear mode, 2 plane */ + DRM_FORMAT_NV61, /* yvu422_8bit linear mode, 2 plane */ + DRM_FORMAT_NV24, /* yuv444_8bit linear mode, 2 plane */ + DRM_FORMAT_NV42, /* yvu444_8bit linear mode, 2 plane */ + DRM_FORMAT_NV15, /* yuv420_10bit linear mode, 2 plane, no padding */ + DRM_FORMAT_NV20, /* yuv422_10bit linear mode, 2 plane, no padding */ + DRM_FORMAT_NV30, /* yuv444_10bit linear mode, 2 plane, no padding */ +}; + static const uint32_t formats_esmart[] =3D { DRM_FORMAT_XRGB8888, DRM_FORMAT_ARGB8888, @@ -116,6 +147,41 @@ static const uint32_t formats_rk356x_esmart[] =3D { DRM_FORMAT_VYUY, /* yuv422_8bit[VYUY] linear mode */ }; =20 +/* + * Add XRGB2101010/ARGB2101010ARGB1555/XRGB1555 + */ +static const uint32_t formats_rk3576_esmart[] =3D { + DRM_FORMAT_XRGB2101010, + DRM_FORMAT_XBGR2101010, + DRM_FORMAT_ARGB2101010, + DRM_FORMAT_ABGR2101010, + DRM_FORMAT_XRGB8888, + DRM_FORMAT_ARGB8888, + DRM_FORMAT_XBGR8888, + DRM_FORMAT_ABGR8888, + DRM_FORMAT_RGB888, + DRM_FORMAT_BGR888, + DRM_FORMAT_RGB565, + DRM_FORMAT_BGR565, + DRM_FORMAT_ARGB1555, + DRM_FORMAT_ABGR1555, + DRM_FORMAT_XRGB1555, + DRM_FORMAT_XBGR1555, + DRM_FORMAT_NV12, /* yuv420_8bit linear mode, 2 plane */ + DRM_FORMAT_NV21, /* yvu420_8bit linear mode, 2 plane */ + DRM_FORMAT_NV16, /* yuv422_8bit linear mode, 2 plane */ + DRM_FORMAT_NV61, /* yvu422_8bit linear mode, 2 plane */ + DRM_FORMAT_NV20, /* yuv422_10bit linear mode, 2 plane, no padding */ + DRM_FORMAT_NV24, /* yuv444_8bit linear mode, 2 plane */ + DRM_FORMAT_NV42, /* yvu444_8bit linear mode, 2 plane */ + DRM_FORMAT_NV30, /* yuv444_10bit linear mode, 2 plane, no padding */ + DRM_FORMAT_NV15, /* yuv420_10bit linear mode, 2 plane, no padding */ + DRM_FORMAT_YVYU, /* yuv422_8bit[YVYU] linear mode */ + DRM_FORMAT_VYUY, /* yuv422_8bit[VYUY] linear mode */ + DRM_FORMAT_YUYV, /* yuv422_8bit[YUYV] linear mode */ + DRM_FORMAT_UYVY, /* yuv422_8bit[UYVY] linear mode */ +}; + static const uint32_t formats_smart[] =3D { DRM_FORMAT_XRGB8888, DRM_FORMAT_ARGB8888, @@ -169,6 +235,48 @@ static const uint64_t format_modifiers_afbc[] =3D { DRM_FORMAT_MOD_INVALID, }; =20 +/* used from rk3576, afbc 32*8 half mode */ +static const uint64_t format_modifiers_rk3576_afbc[] =3D { + DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 | + AFBC_FORMAT_MOD_SPLIT), + + DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 | + AFBC_FORMAT_MOD_SPARSE | + AFBC_FORMAT_MOD_SPLIT), + + DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 | + AFBC_FORMAT_MOD_YTR | + AFBC_FORMAT_MOD_SPLIT), + + DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 | + AFBC_FORMAT_MOD_CBR | + AFBC_FORMAT_MOD_SPLIT), + + DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 | + AFBC_FORMAT_MOD_CBR | + AFBC_FORMAT_MOD_SPARSE | + AFBC_FORMAT_MOD_SPLIT), + + DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 | + AFBC_FORMAT_MOD_YTR | + AFBC_FORMAT_MOD_CBR | + AFBC_FORMAT_MOD_SPLIT), + + DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 | + AFBC_FORMAT_MOD_YTR | + AFBC_FORMAT_MOD_CBR | + AFBC_FORMAT_MOD_SPARSE | + AFBC_FORMAT_MOD_SPLIT), + + /* SPLIT mandates SPARSE, RGB modes mandates YTR */ + DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 | + AFBC_FORMAT_MOD_YTR | + AFBC_FORMAT_MOD_SPARSE | + AFBC_FORMAT_MOD_SPLIT), + DRM_FORMAT_MOD_LINEAR, + DRM_FORMAT_MOD_INVALID, +}; + static const struct reg_field rk3568_vop_cluster_regs[VOP2_WIN_MAX_REG] = =3D { [VOP2_WIN_ENABLE] =3D REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 0, 0), [VOP2_WIN_FORMAT] =3D REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 1, 5), @@ -293,6 +401,136 @@ static const struct reg_field rk3568_vop_smart_regs[V= OP2_WIN_MAX_REG] =3D { [VOP2_WIN_AFBC_ROTATE_90] =3D { .reg =3D 0xffffffff }, }; =20 +static const struct reg_field rk3576_vop_cluster_regs[VOP2_WIN_MAX_REG] = =3D { + [VOP2_WIN_ENABLE] =3D REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 0, 0), + [VOP2_WIN_FORMAT] =3D REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 1, 5), + [VOP2_WIN_RB_SWAP] =3D REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 14, 14), + [VOP2_WIN_UV_SWAP] =3D REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 17, 17), + [VOP2_WIN_DITHER_UP] =3D REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 18, 18), + [VOP2_WIN_ACT_INFO] =3D REG_FIELD(RK3568_CLUSTER_WIN_ACT_INFO, 0, 31), + [VOP2_WIN_DSP_INFO] =3D REG_FIELD(RK3568_CLUSTER_WIN_DSP_INFO, 0, 31), + [VOP2_WIN_DSP_ST] =3D REG_FIELD(RK3568_CLUSTER_WIN_DSP_ST, 0, 31), + [VOP2_WIN_YRGB_MST] =3D REG_FIELD(RK3568_CLUSTER_WIN_YRGB_MST, 0, 31), + [VOP2_WIN_UV_MST] =3D REG_FIELD(RK3568_CLUSTER_WIN_CBR_MST, 0, 31), + [VOP2_WIN_YUV_CLIP] =3D REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 19, 19), + [VOP2_WIN_YRGB_VIR] =3D REG_FIELD(RK3568_CLUSTER_WIN_VIR, 0, 15), + [VOP2_WIN_UV_VIR] =3D REG_FIELD(RK3568_CLUSTER_WIN_VIR, 16, 31), + [VOP2_WIN_Y2R_EN] =3D REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 8, 8), + [VOP2_WIN_R2Y_EN] =3D REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 9, 9), + [VOP2_WIN_CSC_MODE] =3D REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 10, 11), + [VOP2_WIN_VP_SEL] =3D REG_FIELD(RK3576_CLUSTER_PORT_SEL_IMD, 0, 1), + [VOP2_WIN_DLY_NUM] =3D REG_FIELD(RK3576_CLUSTER_DLY_NUM, 0, 7), + + /* Scale */ + [VOP2_WIN_SCALE_YRGB_X] =3D REG_FIELD(RK3568_CLUSTER_WIN_SCL_FACTOR_YRGB,= 0, 15), + [VOP2_WIN_SCALE_YRGB_Y] =3D REG_FIELD(RK3568_CLUSTER_WIN_SCL_FACTOR_YRGB,= 16, 31), + [VOP2_WIN_BIC_COE_SEL] =3D REG_FIELD(RK3568_CLUSTER_WIN_CTRL1, 2, 3), + [VOP2_WIN_YRGB_VER_SCL_MODE] =3D REG_FIELD(RK3568_CLUSTER_WIN_CTRL1, 14, = 15), + [VOP2_WIN_YRGB_HOR_SCL_MODE] =3D REG_FIELD(RK3568_CLUSTER_WIN_CTRL1, 22, = 23), + [VOP2_WIN_VSD_YRGB_GT2] =3D REG_FIELD(RK3568_CLUSTER_WIN_CTRL1, 28, 28), + [VOP2_WIN_VSD_YRGB_GT4] =3D REG_FIELD(RK3568_CLUSTER_WIN_CTRL1, 29, 29), + + /* cluster regs */ + [VOP2_WIN_AFBC_ENABLE] =3D REG_FIELD(RK3568_CLUSTER_CTRL, 1, 1), + [VOP2_WIN_CLUSTER_ENABLE] =3D REG_FIELD(RK3568_CLUSTER_CTRL, 0, 0), + [VOP2_WIN_CLUSTER_LB_MODE] =3D REG_FIELD(RK3568_CLUSTER_CTRL, 4, 7), + + /* afbc regs */ + [VOP2_WIN_AFBC_FORMAT] =3D REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_CTRL, 2, 6), + [VOP2_WIN_AFBC_RB_SWAP] =3D REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_CTRL, 9, 9= ), + [VOP2_WIN_AFBC_UV_SWAP] =3D REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_CTRL, 10, = 10), + [VOP2_WIN_AFBC_AUTO_GATING_EN] =3D REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_OUT= PUT_CTRL, 4, 4), + [VOP2_WIN_AFBC_HALF_BLOCK_EN] =3D REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_CTRL= , 7, 7), + [VOP2_WIN_AFBC_BLOCK_SPLIT_EN] =3D REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_CTR= L, 8, 8), + [VOP2_WIN_AFBC_PLD_OFFSET_EN] =3D REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_CTRL= , 16, 16), + [VOP2_WIN_AFBC_HDR_PTR] =3D REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_HDR_PTR, 0= , 31), + [VOP2_WIN_AFBC_PIC_SIZE] =3D REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_PIC_SIZE,= 0, 31), + [VOP2_WIN_AFBC_PIC_VIR_WIDTH] =3D REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_VIR_= WIDTH, 0, 15), + [VOP2_WIN_AFBC_TILE_NUM] =3D REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_VIR_WIDTH= , 16, 31), + [VOP2_WIN_AFBC_PIC_OFFSET] =3D REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_PIC_OFF= SET, 0, 31), + [VOP2_WIN_AFBC_DSP_OFFSET] =3D REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_DSP_OFF= SET, 0, 31), + [VOP2_WIN_AFBC_PLD_OFFSET] =3D REG_FIELD(RK3576_CLUSTER_WIN_AFBCD_PLD_PTR= _OFFSET, 0, 31), + [VOP2_WIN_AFBC_TRANSFORM_OFFSET] =3D REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_T= RANSFORM_OFFSET, 0, 31), + [VOP2_WIN_AFBC_ROTATE_90] =3D REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_ROTATE_M= ODE, 0, 0), + [VOP2_WIN_AFBC_ROTATE_270] =3D REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_ROTATE_= MODE, 1, 1), + [VOP2_WIN_XMIRROR] =3D REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_ROTATE_MODE, 2,= 2), + [VOP2_WIN_YMIRROR] =3D REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_ROTATE_MODE, 3,= 3), + [VOP2_WIN_COLOR_KEY] =3D { .reg =3D 0xffffffff }, + [VOP2_WIN_COLOR_KEY_EN] =3D { .reg =3D 0xffffffff }, + [VOP2_WIN_SCALE_CBCR_X] =3D { .reg =3D 0xffffffff }, + [VOP2_WIN_SCALE_CBCR_Y] =3D { .reg =3D 0xffffffff }, + [VOP2_WIN_YRGB_HSCL_FILTER_MODE] =3D { .reg =3D 0xffffffff }, + [VOP2_WIN_YRGB_VSCL_FILTER_MODE] =3D { .reg =3D 0xffffffff }, + [VOP2_WIN_CBCR_VER_SCL_MODE] =3D { .reg =3D 0xffffffff }, + [VOP2_WIN_CBCR_HSCL_FILTER_MODE] =3D { .reg =3D 0xffffffff }, + [VOP2_WIN_CBCR_HOR_SCL_MODE] =3D { .reg =3D 0xffffffff }, + [VOP2_WIN_CBCR_VSCL_FILTER_MODE] =3D { .reg =3D 0xffffffff }, + [VOP2_WIN_VSD_CBCR_GT2] =3D { .reg =3D 0xffffffff }, + [VOP2_WIN_VSD_CBCR_GT4] =3D { .reg =3D 0xffffffff }, +}; + +static const struct reg_field rk3576_vop_smart_regs[VOP2_WIN_MAX_REG] =3D { + [VOP2_WIN_ENABLE] =3D REG_FIELD(RK3568_SMART_REGION0_CTRL, 0, 0), + [VOP2_WIN_FORMAT] =3D REG_FIELD(RK3568_SMART_REGION0_CTRL, 1, 5), + [VOP2_WIN_DITHER_UP] =3D REG_FIELD(RK3568_SMART_REGION0_CTRL, 12, 12), + [VOP2_WIN_RB_SWAP] =3D REG_FIELD(RK3568_SMART_REGION0_CTRL, 14, 14), + [VOP2_WIN_UV_SWAP] =3D REG_FIELD(RK3568_SMART_REGION0_CTRL, 16, 16), + [VOP2_WIN_ACT_INFO] =3D REG_FIELD(RK3568_SMART_REGION0_ACT_INFO, 0, 31), + [VOP2_WIN_DSP_INFO] =3D REG_FIELD(RK3568_SMART_REGION0_DSP_INFO, 0, 31), + [VOP2_WIN_DSP_ST] =3D REG_FIELD(RK3568_SMART_REGION0_DSP_ST, 0, 28), + [VOP2_WIN_YRGB_MST] =3D REG_FIELD(RK3568_SMART_REGION0_YRGB_MST, 0, 31), + [VOP2_WIN_UV_MST] =3D REG_FIELD(RK3568_SMART_REGION0_CBR_MST, 0, 31), + [VOP2_WIN_YUV_CLIP] =3D REG_FIELD(RK3568_SMART_REGION0_CTRL, 17, 17), + [VOP2_WIN_YRGB_VIR] =3D REG_FIELD(RK3568_SMART_REGION0_VIR, 0, 15), + [VOP2_WIN_UV_VIR] =3D REG_FIELD(RK3568_SMART_REGION0_VIR, 16, 31), + [VOP2_WIN_Y2R_EN] =3D REG_FIELD(RK3568_SMART_CTRL0, 0, 0), + [VOP2_WIN_R2Y_EN] =3D REG_FIELD(RK3568_SMART_CTRL0, 1, 1), + [VOP2_WIN_CSC_MODE] =3D REG_FIELD(RK3568_SMART_CTRL0, 2, 3), + [VOP2_WIN_YMIRROR] =3D REG_FIELD(RK3568_SMART_CTRL1, 31, 31), + [VOP2_WIN_COLOR_KEY] =3D REG_FIELD(RK3568_SMART_COLOR_KEY_CTRL, 0, 29), + [VOP2_WIN_COLOR_KEY_EN] =3D REG_FIELD(RK3568_SMART_COLOR_KEY_CTRL, 31, 31= ), + [VOP2_WIN_VP_SEL] =3D REG_FIELD(RK3576_SMART_PORT_SEL_IMD, 0, 1), + [VOP2_WIN_DLY_NUM] =3D REG_FIELD(RK3576_SMART_DLY_NUM, 0, 7), + + /* Scale */ + [VOP2_WIN_SCALE_YRGB_X] =3D REG_FIELD(RK3568_SMART_REGION0_SCL_FACTOR_YRG= B, 0, 15), + [VOP2_WIN_SCALE_YRGB_Y] =3D REG_FIELD(RK3568_SMART_REGION0_SCL_FACTOR_YRG= B, 16, 31), + [VOP2_WIN_SCALE_CBCR_X] =3D REG_FIELD(RK3568_SMART_REGION0_SCL_FACTOR_CBR= , 0, 15), + [VOP2_WIN_SCALE_CBCR_Y] =3D REG_FIELD(RK3568_SMART_REGION0_SCL_FACTOR_CBR= , 16, 31), + [VOP2_WIN_YRGB_HOR_SCL_MODE] =3D REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL,= 0, 1), + [VOP2_WIN_YRGB_HSCL_FILTER_MODE] =3D REG_FIELD(RK3568_SMART_REGION0_SCL_C= TRL, 2, 3), + [VOP2_WIN_YRGB_VER_SCL_MODE] =3D REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL,= 4, 5), + [VOP2_WIN_YRGB_VSCL_FILTER_MODE] =3D REG_FIELD(RK3568_SMART_REGION0_SCL_C= TRL, 6, 7), + [VOP2_WIN_CBCR_HOR_SCL_MODE] =3D REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL,= 8, 9), + [VOP2_WIN_CBCR_HSCL_FILTER_MODE] =3D REG_FIELD(RK3568_SMART_REGION0_SCL_C= TRL, 10, 11), + [VOP2_WIN_CBCR_VER_SCL_MODE] =3D REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL,= 12, 13), + [VOP2_WIN_CBCR_VSCL_FILTER_MODE] =3D REG_FIELD(RK3568_SMART_REGION0_SCL_C= TRL, 14, 15), + [VOP2_WIN_BIC_COE_SEL] =3D REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 16, 1= 7), + [VOP2_WIN_VSD_YRGB_GT2] =3D REG_FIELD(RK3568_SMART_REGION0_CTRL, 8, 8), + [VOP2_WIN_VSD_YRGB_GT4] =3D REG_FIELD(RK3568_SMART_REGION0_CTRL, 9, 9), + [VOP2_WIN_VSD_CBCR_GT2] =3D REG_FIELD(RK3568_SMART_REGION0_CTRL, 10, 10), + [VOP2_WIN_VSD_CBCR_GT4] =3D REG_FIELD(RK3568_SMART_REGION0_CTRL, 11, 11), + [VOP2_WIN_XMIRROR] =3D { .reg =3D 0xffffffff }, + [VOP2_WIN_CLUSTER_ENABLE] =3D { .reg =3D 0xffffffff }, + [VOP2_WIN_AFBC_ENABLE] =3D { .reg =3D 0xffffffff }, + [VOP2_WIN_CLUSTER_LB_MODE] =3D { .reg =3D 0xffffffff }, + [VOP2_WIN_AFBC_FORMAT] =3D { .reg =3D 0xffffffff }, + [VOP2_WIN_AFBC_RB_SWAP] =3D { .reg =3D 0xffffffff }, + [VOP2_WIN_AFBC_UV_SWAP] =3D { .reg =3D 0xffffffff }, + [VOP2_WIN_AFBC_AUTO_GATING_EN] =3D { .reg =3D 0xffffffff }, + [VOP2_WIN_AFBC_BLOCK_SPLIT_EN] =3D { .reg =3D 0xffffffff }, + [VOP2_WIN_AFBC_PIC_VIR_WIDTH] =3D { .reg =3D 0xffffffff }, + [VOP2_WIN_AFBC_TILE_NUM] =3D { .reg =3D 0xffffffff }, + [VOP2_WIN_AFBC_PIC_OFFSET] =3D { .reg =3D 0xffffffff }, + [VOP2_WIN_AFBC_PIC_SIZE] =3D { .reg =3D 0xffffffff }, + [VOP2_WIN_AFBC_DSP_OFFSET] =3D { .reg =3D 0xffffffff }, + [VOP2_WIN_AFBC_TRANSFORM_OFFSET] =3D { .reg =3D 0xffffffff }, + [VOP2_WIN_AFBC_HDR_PTR] =3D { .reg =3D 0xffffffff }, + [VOP2_WIN_AFBC_HALF_BLOCK_EN] =3D { .reg =3D 0xffffffff }, + [VOP2_WIN_AFBC_ROTATE_270] =3D { .reg =3D 0xffffffff }, + [VOP2_WIN_AFBC_ROTATE_90] =3D { .reg =3D 0xffffffff }, +}; + static const struct vop2_video_port_data rk3568_vop_video_ports[] =3D { { .id =3D 0, @@ -509,6 +747,272 @@ static const struct vop2_regs_dump rk3568_regs_dump[]= =3D { }, }; =20 +static const struct vop2_video_port_data rk3576_vop_video_ports[] =3D { + { + .id =3D 0, + .feature =3D VOP2_VP_FEATURE_OUTPUT_10BIT, + .gamma_lut_len =3D 1024, + .cubic_lut_len =3D 9 * 9 * 9, /* 9x9x9 */ + .max_output =3D { 4096, 2304 }, + /* win layer_mix hdr */ + .pre_scan_max_dly =3D { 10, 8, 2, 0 }, + .offset =3D 0xc00, + .pixel_rate =3D 2, + }, { + .id =3D 1, + .feature =3D VOP2_VP_FEATURE_OUTPUT_10BIT, + .gamma_lut_len =3D 1024, + .cubic_lut_len =3D 729, /* 9x9x9 */ + .max_output =3D { 2560, 1600 }, + /* win layer_mix hdr */ + .pre_scan_max_dly =3D { 10, 6, 0, 0 }, + .offset =3D 0xd00, + .pixel_rate =3D 1, + }, { + .id =3D 2, + .gamma_lut_len =3D 1024, + .max_output =3D { 1920, 1080 }, + /* win layer_mix hdr */ + .pre_scan_max_dly =3D { 10, 6, 0, 0 }, + .offset =3D 0xe00, + .pixel_rate =3D 1, + }, +}; + +/* + * rk3576 vop with 2 cluster, 4 esmart win. + * Every cluster can work as 4K win or split into two win. + * All win in cluster support AFBCD. + * + * Every esmart win support 4 Multi-region. + * + * VP0 can use Cluster0/1 and Esmart0/2 + * VP1 can use Cluster0/1 and Esmart1/3 + * VP2 can use Esmart0/1/2/3 + * + * Scale filter mode: + * + * * Cluster: + * * Support prescale down: + * * H/V: gt2/avg2 or gt4/avg4 + * * After prescale down: + * * nearest-neighbor/bilinear/multi-phase filter for scale up + * * nearest-neighbor/bilinear/multi-phase filter for scale down + * + * * Esmart: + * * Support prescale down: + * * H: gt2/avg2 or gt4/avg4 + * * V: gt2 or gt4 + * * After prescale down: + * * nearest-neighbor/bilinear/bicubic for scale up + * * nearest-neighbor/bilinear for scale down + * + * AXI config:: + * + * * Cluster0 win0: 0xa, 0xb [AXI0] + * * Cluster0 win1: 0xc, 0xd [AXI0] + * * Cluster1 win0: 0x6, 0x7 [AXI0] + * * Cluster1 win1: 0x8, 0x9 [AXI0] + * * Esmart0: 0x10, 0x11 [AXI0] + * * Esmart1: 0x12, 0x13 [AXI0] + * * Esmart2: 0xa, 0xb [AXI1] + * * Esmart3: 0xc, 0xd [AXI1] + * * Lut dma rid: 0x1, 0x2, 0x3 [AXI0] + * * DCI dma rid: 0x4 [AXI0] + * * Metadata rid: 0x5 [AXI0] + * + * * Limit: + * * (1) 0x0 and 0xf can't be used; + * * (2) cluster and lut/dci/metadata rid must smaller than 0xf, + * * if Cluster rid is bigger than 0xf, VOP will dead at the + * * system bandwidth very terrible scene. + */ +static const struct vop2_win_data rk3576_vop_win_data[] =3D { + { + .name =3D "Cluster0-win0", + .phys_id =3D ROCKCHIP_VOP2_CLUSTER0, + .base =3D 0x1000, + .possible_vp_mask =3D BIT(0) | BIT(1), + .formats =3D formats_rk3576_cluster, + .nformats =3D ARRAY_SIZE(formats_rk3576_cluster), + .format_modifiers =3D format_modifiers_rk3576_afbc, + .layer_sel_id =3D { 0, 0, 0xf, 0xf }, + .supported_rotations =3D DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y, + .max_upscale_factor =3D 4, + .max_downscale_factor =3D 4, + .type =3D DRM_PLANE_TYPE_PRIMARY, + .feature =3D WIN_FEATURE_AFBDC | WIN_FEATURE_CLUSTER, + }, { + .name =3D "Cluster1-win0", + .phys_id =3D ROCKCHIP_VOP2_CLUSTER1, + .base =3D 0x1200, + .possible_vp_mask =3D BIT(0) | BIT(1), + .formats =3D formats_rk3576_cluster, + .nformats =3D ARRAY_SIZE(formats_rk3576_cluster), + .format_modifiers =3D format_modifiers_rk3576_afbc, + .layer_sel_id =3D { 1, 1, 0xf, 0xf }, + .supported_rotations =3D DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y, + .type =3D DRM_PLANE_TYPE_PRIMARY, + .max_upscale_factor =3D 4, + .max_downscale_factor =3D 4, + .feature =3D WIN_FEATURE_AFBDC | WIN_FEATURE_CLUSTER, + }, { + .name =3D "Esmart0-win0", + .phys_id =3D ROCKCHIP_VOP2_ESMART0, + .base =3D 0x1800, + .possible_vp_mask =3D BIT(0) | BIT(2), + .formats =3D formats_rk3576_esmart, + .nformats =3D ARRAY_SIZE(formats_rk3576_esmart), + .format_modifiers =3D format_modifiers, + .layer_sel_id =3D { 2, 0xf, 0, 0xf }, + .supported_rotations =3D DRM_MODE_REFLECT_Y, + .type =3D DRM_PLANE_TYPE_OVERLAY, + .max_upscale_factor =3D 8, + .max_downscale_factor =3D 8, + }, { + .name =3D "Esmart1-win0", + .phys_id =3D ROCKCHIP_VOP2_ESMART1, + .base =3D 0x1a00, + .possible_vp_mask =3D BIT(1) | BIT(2), + .formats =3D formats_rk3576_esmart, + .nformats =3D ARRAY_SIZE(formats_rk3576_esmart), + .format_modifiers =3D format_modifiers, + .layer_sel_id =3D { 0xf, 2, 1, 0xf }, + .supported_rotations =3D DRM_MODE_REFLECT_Y, + .type =3D DRM_PLANE_TYPE_OVERLAY, + .max_upscale_factor =3D 8, + .max_downscale_factor =3D 8, + }, { + .name =3D "Esmart2-win0", + .phys_id =3D ROCKCHIP_VOP2_ESMART2, + .base =3D 0x1c00, + .possible_vp_mask =3D BIT(0) | BIT(2), + .formats =3D formats_rk3576_esmart, + .nformats =3D ARRAY_SIZE(formats_rk3576_esmart), + .format_modifiers =3D format_modifiers, + .layer_sel_id =3D { 3, 0xf, 2, 0xf }, + .supported_rotations =3D DRM_MODE_REFLECT_Y, + .type =3D DRM_PLANE_TYPE_OVERLAY, + .max_upscale_factor =3D 8, + .max_downscale_factor =3D 8, + }, { + .name =3D "Esmart3-win0", + .phys_id =3D ROCKCHIP_VOP2_ESMART3, + .base =3D 0x1e00, + .possible_vp_mask =3D BIT(1) | BIT(2), + .formats =3D formats_rk3576_esmart, + .nformats =3D ARRAY_SIZE(formats_rk3576_esmart), + .format_modifiers =3D format_modifiers, + .layer_sel_id =3D { 0xf, 3, 3, 0xf }, + .supported_rotations =3D DRM_MODE_REFLECT_Y, + .type =3D DRM_PLANE_TYPE_OVERLAY, + .max_upscale_factor =3D 8, + .max_downscale_factor =3D 8, + }, +}; + +static const struct vop2_regs_dump rk3576_regs_dump[] =3D { + { + .name =3D "SYS", + .base =3D RK3568_REG_CFG_DONE, + .size =3D 0x200, + .en_reg =3D 0, + .en_val =3D 0, + .en_mask =3D 0 + }, { + .name =3D "OVL_SYS", + .base =3D RK3576_SYS_EXTRA_ALPHA_CTRL, + .size =3D 0x50, + .en_reg =3D 0, + .en_val =3D 0, + .en_mask =3D 0, + }, { + .name =3D "OVL_VP0", + .base =3D RK3576_OVL_CTRL(0), + .size =3D 0x80, + .en_reg =3D 0, + .en_val =3D 0, + .en_mask =3D 0, + }, { + .name =3D "OVL_VP1", + .base =3D RK3576_OVL_CTRL(1), + .size =3D 0x80, + .en_reg =3D 0, + .en_val =3D 0, + .en_mask =3D 0, + }, { + .name =3D "OVL_VP2", + .base =3D RK3576_OVL_CTRL(2), + .size =3D 0x80, + .en_reg =3D 0, + .en_val =3D 0, + .en_mask =3D 0, + }, { + .name =3D "VP0", + .base =3D RK3568_VP0_CTRL_BASE, + .size =3D 0x100, + .en_reg =3D RK3568_VP_DSP_CTRL, + .en_val =3D 0, + .en_mask =3D RK3568_VP_DSP_CTRL__STANDBY, + }, { + .name =3D "VP1", + .base =3D RK3568_VP1_CTRL_BASE, + .size =3D 0x100, + .en_reg =3D RK3568_VP_DSP_CTRL, + .en_val =3D 0, + .en_mask =3D RK3568_VP_DSP_CTRL__STANDBY, + }, { + .name =3D "VP2", + .base =3D RK3568_VP2_CTRL_BASE, + .size =3D 0x100, + .en_reg =3D RK3568_VP_DSP_CTRL, + .en_val =3D 0, + .en_mask =3D RK3568_VP_DSP_CTRL__STANDBY, + }, { + .name =3D "Cluster0", + .base =3D RK3568_CLUSTER0_CTRL_BASE, + .size =3D 0x200, + .en_reg =3D RK3568_CLUSTER_WIN_CTRL0, + .en_val =3D RK3568_CLUSTER_WIN_CTRL0__WIN0_EN, + .en_mask =3D RK3568_CLUSTER_WIN_CTRL0__WIN0_EN, + }, { + .name =3D "Cluster1", + .base =3D RK3568_CLUSTER1_CTRL_BASE, + .size =3D 0x200, + .en_reg =3D RK3568_CLUSTER_WIN_CTRL0, + .en_val =3D RK3568_CLUSTER_WIN_CTRL0__WIN0_EN, + .en_mask =3D RK3568_CLUSTER_WIN_CTRL0__WIN0_EN, + }, { + .name =3D "Esmart0", + .base =3D RK3568_ESMART0_CTRL_BASE, + .size =3D 0xf0, + .en_reg =3D RK3568_SMART_REGION0_CTRL, + .en_val =3D RK3568_SMART_REGION0_CTRL__WIN0_EN, + .en_mask =3D RK3568_SMART_REGION0_CTRL__WIN0_EN, + }, { + .name =3D "Esmart1", + .base =3D RK3568_ESMART1_CTRL_BASE, + .size =3D 0xf0, + .en_reg =3D RK3568_SMART_REGION0_CTRL, + .en_val =3D RK3568_SMART_REGION0_CTRL__WIN0_EN, + .en_mask =3D RK3568_SMART_REGION0_CTRL__WIN0_EN, + }, { + .name =3D "Esmart2", + .base =3D RK3588_ESMART2_CTRL_BASE, + .size =3D 0xf0, + .en_reg =3D RK3568_SMART_REGION0_CTRL, + .en_val =3D RK3568_SMART_REGION0_CTRL__WIN0_EN, + .en_mask =3D RK3568_SMART_REGION0_CTRL__WIN0_EN, + }, { + .name =3D "Esmart3", + .base =3D RK3588_ESMART3_CTRL_BASE, + .size =3D 0xf0, + .en_reg =3D RK3568_SMART_REGION0_CTRL, + .en_val =3D RK3568_SMART_REGION0_CTRL__WIN0_EN, + .en_mask =3D RK3568_SMART_REGION0_CTRL__WIN0_EN, + }, +}; + static const struct vop2_video_port_data rk3588_vop_video_ports[] =3D { { .id =3D 0, @@ -876,6 +1380,84 @@ static unsigned long rk3568_set_intf_mux(struct vop2_= video_port *vp, int id, u32 return crtc->state->adjusted_mode.crtc_clock * 1000LL; } =20 +static unsigned long rk3576_set_intf_mux(struct vop2_video_port *vp, int i= d, u32 polflags) +{ + struct vop2 *vop2 =3D vp->vop2; + struct drm_crtc *crtc =3D &vp->crtc; + struct drm_display_mode *adjusted_mode =3D &crtc->state->adjusted_mode; + struct rockchip_crtc_state *vcstate =3D to_rockchip_crtc_state(crtc->stat= e); + u8 port_pix_rate =3D vp->data->pixel_rate; + int dclk_core_div, dclk_out_div, if_pixclk_div, if_dclk_sel; + u32 ctrl, vp_clk_div, reg, dclk_div; + unsigned long dclk_in_rate, dclk_core_rate; + + if (vcstate->output_mode =3D=3D ROCKCHIP_OUT_MODE_YUV420 || adjusted_mode= ->crtc_clock > 600000) + dclk_div =3D 2; + else + dclk_div =3D 1; + + if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) + dclk_core_rate =3D adjusted_mode->crtc_clock / 2; + else + dclk_core_rate =3D adjusted_mode->crtc_clock / port_pix_rate; + + dclk_in_rate =3D adjusted_mode->crtc_clock / dclk_div; + + dclk_core_div =3D dclk_in_rate > dclk_core_rate ? 1 : 0; + + if (vop2_output_if_is_edp(id)) + if_pixclk_div =3D port_pix_rate =3D=3D 2 ? RK3576_DSP_IF_PCLK_DIV : 0; + else + if_pixclk_div =3D port_pix_rate =3D=3D 1 ? RK3576_DSP_IF_PCLK_DIV : 0; + + if (vcstate->output_mode =3D=3D ROCKCHIP_OUT_MODE_YUV420) { + if_dclk_sel =3D RK3576_DSP_IF_DCLK_SEL_OUT; + dclk_out_div =3D 1; + } else { + if_dclk_sel =3D 0; + dclk_out_div =3D 0; + } + + switch (id) { + case ROCKCHIP_VOP2_EP_HDMI0: + reg =3D RK3576_HDMI0_IF_CTRL; + break; + case ROCKCHIP_VOP2_EP_EDP0: + reg =3D RK3576_EDP0_IF_CTRL; + break; + case ROCKCHIP_VOP2_EP_MIPI0: + reg =3D RK3576_MIPI0_IF_CTRL; + break; + case ROCKCHIP_VOP2_EP_DP0: + reg =3D RK3576_DP0_IF_CTRL; + break; + case ROCKCHIP_VOP2_EP_DP1: + reg =3D RK3576_DP1_IF_CTRL; + break; + default: + drm_err(vop2->drm, "Invalid interface id %d on vp%d\n", id, vp->id); + return 0; + } + + ctrl =3D vop2_readl(vop2, reg); + ctrl &=3D ~RK3576_DSP_IF_DCLK_SEL_OUT; + ctrl &=3D ~RK3576_DSP_IF_PCLK_DIV; + ctrl &=3D ~RK3576_DSP_IF_MUX; + ctrl |=3D RK3576_DSP_IF_CFG_DONE_IMD; + ctrl |=3D if_dclk_sel | if_pixclk_div; + ctrl |=3D RK3576_DSP_IF_CLK_OUT_EN | RK3576_DSP_IF_EN; + ctrl |=3D FIELD_PREP(RK3576_DSP_IF_MUX, vp->id); + ctrl |=3D FIELD_PREP(RK3576_DSP_IF_PIN_POL, polflags); + vop2_writel(vop2, reg, ctrl); + + vp_clk_div =3D FIELD_PREP(RK3588_VP_CLK_CTRL__DCLK_CORE_DIV, dclk_core_di= v); + vp_clk_div |=3D FIELD_PREP(RK3588_VP_CLK_CTRL__DCLK_OUT_DIV, dclk_out_div= ); + + vop2_vp_write(vp, RK3588_VP_CLK_CTRL, vp_clk_div); + + return dclk_in_rate * 1000LL; +} + /* * calc the dclk on rk3588 * the available div of dclk is 1, 2, 4 @@ -1214,6 +1796,7 @@ static void vop2_setup_cluster_alpha(struct vop2 *vop= 2, struct vop2_win *main_wi struct drm_plane_state *bottom_win_pstate; bool src_pixel_alpha_en =3D false; u16 src_glb_alpha_val, dst_glb_alpha_val; + u32 src_color_ctrl_reg, dst_color_ctrl_reg, src_alpha_ctrl_reg, dst_alpha= _ctrl_reg; u32 offset =3D 0; bool premulti_en =3D false; bool swap =3D false; @@ -1251,14 +1834,22 @@ static void vop2_setup_cluster_alpha(struct vop2 *v= op2, struct vop2_win *main_wi break; } =20 - vop2_writel(vop2, RK3568_CLUSTER0_MIX_SRC_COLOR_CTRL + offset, - alpha.src_color_ctrl.val); - vop2_writel(vop2, RK3568_CLUSTER0_MIX_DST_COLOR_CTRL + offset, - alpha.dst_color_ctrl.val); - vop2_writel(vop2, RK3568_CLUSTER0_MIX_SRC_ALPHA_CTRL + offset, - alpha.src_alpha_ctrl.val); - vop2_writel(vop2, RK3568_CLUSTER0_MIX_DST_ALPHA_CTRL + offset, - alpha.dst_alpha_ctrl.val); + if (vop2->version <=3D VOP_VERSION_RK3588) { + src_color_ctrl_reg =3D RK3568_CLUSTER0_MIX_SRC_COLOR_CTRL; + dst_color_ctrl_reg =3D RK3568_CLUSTER0_MIX_DST_COLOR_CTRL; + src_alpha_ctrl_reg =3D RK3568_CLUSTER0_MIX_SRC_ALPHA_CTRL; + dst_alpha_ctrl_reg =3D RK3568_CLUSTER0_MIX_DST_ALPHA_CTRL; + } else { + src_color_ctrl_reg =3D RK3576_CLUSTER0_MIX_SRC_COLOR_CTRL; + dst_color_ctrl_reg =3D RK3576_CLUSTER0_MIX_DST_COLOR_CTRL; + src_alpha_ctrl_reg =3D RK3576_CLUSTER0_MIX_SRC_ALPHA_CTRL; + dst_alpha_ctrl_reg =3D RK3576_CLUSTER0_MIX_DST_ALPHA_CTRL; + } + + vop2_writel(vop2, src_color_ctrl_reg + offset, alpha.src_color_ctrl.val); + vop2_writel(vop2, dst_color_ctrl_reg + offset, alpha.dst_color_ctrl.val); + vop2_writel(vop2, src_alpha_ctrl_reg + offset, alpha.src_alpha_ctrl.val); + vop2_writel(vop2, dst_alpha_ctrl_reg + offset, alpha.dst_alpha_ctrl.val); } =20 static void vop2_setup_alpha(struct vop2_video_port *vp) @@ -1271,11 +1862,16 @@ static void vop2_setup_alpha(struct vop2_video_port= *vp) int pixel_alpha_en; int premulti_en, gpremulti_en =3D 0; int mixer_id; + u32 src_color_ctrl_reg, dst_color_ctrl_reg, src_alpha_ctrl_reg, dst_alpha= _ctrl_reg; u32 offset; bool bottom_layer_alpha_en =3D false; u32 dst_global_alpha =3D DRM_BLEND_ALPHA_OPAQUE; =20 - mixer_id =3D vop2_find_start_mixer_id_for_vp(vop2, vp->id); + if (vop2->version <=3D VOP_VERSION_RK3588) + mixer_id =3D vop2_find_start_mixer_id_for_vp(vop2, vp->id); + else + mixer_id =3D 0; + alpha_config.dst_pixel_alpha_en =3D true; /* alpha value need transfer to= next mix */ =20 drm_atomic_crtc_for_each_plane(plane, &vp->crtc) { @@ -1294,6 +1890,18 @@ static void vop2_setup_alpha(struct vop2_video_port = *vp) } } =20 + if (vop2->version <=3D VOP_VERSION_RK3588) { + src_color_ctrl_reg =3D RK3568_MIX0_SRC_COLOR_CTRL; + dst_color_ctrl_reg =3D RK3568_MIX0_DST_COLOR_CTRL; + src_alpha_ctrl_reg =3D RK3568_MIX0_SRC_ALPHA_CTRL; + dst_alpha_ctrl_reg =3D RK3568_MIX0_DST_ALPHA_CTRL; + } else { + src_color_ctrl_reg =3D RK3576_OVL_MIX0_SRC_COLOR_CTRL(vp->id); + dst_color_ctrl_reg =3D RK3576_OVL_MIX0_DST_COLOR_CTRL(vp->id); + src_alpha_ctrl_reg =3D RK3576_OVL_MIX0_SRC_ALPHA_CTRL(vp->id); + dst_alpha_ctrl_reg =3D RK3576_OVL_MIX0_DST_ALPHA_CTRL(vp->id); + } + drm_atomic_crtc_for_each_plane(plane, &vp->crtc) { struct vop2_win *win =3D to_vop2_win(plane); int zpos =3D plane->state->normalized_zpos; @@ -1340,17 +1948,26 @@ static void vop2_setup_alpha(struct vop2_video_port= *vp) vop2_parse_alpha(&alpha_config, &alpha); =20 offset =3D (mixer_id + zpos - 1) * 0x10; - vop2_writel(vop2, RK3568_MIX0_SRC_COLOR_CTRL + offset, - alpha.src_color_ctrl.val); - vop2_writel(vop2, RK3568_MIX0_DST_COLOR_CTRL + offset, - alpha.dst_color_ctrl.val); - vop2_writel(vop2, RK3568_MIX0_SRC_ALPHA_CTRL + offset, - alpha.src_alpha_ctrl.val); - vop2_writel(vop2, RK3568_MIX0_DST_ALPHA_CTRL + offset, - alpha.dst_alpha_ctrl.val); + + vop2_writel(vop2, src_color_ctrl_reg + offset, alpha.src_color_ctrl.val); + vop2_writel(vop2, dst_color_ctrl_reg + offset, alpha.dst_color_ctrl.val); + vop2_writel(vop2, src_alpha_ctrl_reg + offset, alpha.src_alpha_ctrl.val); + vop2_writel(vop2, dst_alpha_ctrl_reg + offset, alpha.dst_alpha_ctrl.val); } =20 if (vp->id =3D=3D 0) { + if (vop2->version <=3D VOP_VERSION_RK3588) { + src_color_ctrl_reg =3D RK3568_HDR0_SRC_COLOR_CTRL; + dst_color_ctrl_reg =3D RK3568_HDR0_DST_COLOR_CTRL; + src_alpha_ctrl_reg =3D RK3568_HDR0_SRC_ALPHA_CTRL; + dst_alpha_ctrl_reg =3D RK3568_HDR0_DST_ALPHA_CTRL; + } else { + src_color_ctrl_reg =3D RK3576_OVL_HDR_SRC_COLOR_CTRL(vp->id); + dst_color_ctrl_reg =3D RK3576_OVL_HDR_DST_COLOR_CTRL(vp->id); + src_alpha_ctrl_reg =3D RK3576_OVL_HDR_SRC_ALPHA_CTRL(vp->id); + dst_alpha_ctrl_reg =3D RK3576_OVL_HDR_DST_ALPHA_CTRL(vp->id); + } + if (bottom_layer_alpha_en) { /* Transfer pixel alpha to hdr mix */ alpha_config.src_premulti_en =3D gpremulti_en; @@ -1358,18 +1975,15 @@ static void vop2_setup_alpha(struct vop2_video_port= *vp) alpha_config.src_pixel_alpha_en =3D true; alpha_config.src_glb_alpha_value =3D DRM_BLEND_ALPHA_OPAQUE; alpha_config.dst_glb_alpha_value =3D DRM_BLEND_ALPHA_OPAQUE; + vop2_parse_alpha(&alpha_config, &alpha); =20 - vop2_writel(vop2, RK3568_HDR0_SRC_COLOR_CTRL, - alpha.src_color_ctrl.val); - vop2_writel(vop2, RK3568_HDR0_DST_COLOR_CTRL, - alpha.dst_color_ctrl.val); - vop2_writel(vop2, RK3568_HDR0_SRC_ALPHA_CTRL, - alpha.src_alpha_ctrl.val); - vop2_writel(vop2, RK3568_HDR0_DST_ALPHA_CTRL, - alpha.dst_alpha_ctrl.val); + vop2_writel(vop2, src_color_ctrl_reg, alpha.src_color_ctrl.val); + vop2_writel(vop2, dst_color_ctrl_reg, alpha.dst_color_ctrl.val); + vop2_writel(vop2, src_alpha_ctrl_reg, alpha.src_alpha_ctrl.val); + vop2_writel(vop2, dst_alpha_ctrl_reg, alpha.dst_alpha_ctrl.val); } else { - vop2_writel(vop2, RK3568_HDR0_SRC_COLOR_CTRL, 0); + vop2_writel(vop2, src_color_ctrl_reg, 0); } } } @@ -1577,6 +2191,72 @@ static void rk3568_vop2_setup_overlay(struct vop2_vi= deo_port *vp) rk3568_vop2_setup_dly_for_windows(vp); } =20 +static void rk3576_vop2_setup_layer_mixer(struct vop2_video_port *vp) +{ + struct rockchip_crtc_state *vcstate =3D to_rockchip_crtc_state(vp->crtc.s= tate); + struct vop2 *vop2 =3D vp->vop2; + struct drm_plane *plane; + u32 layer_sel =3D 0xffff; /* 0xf means this layer is disabled */ + u32 ovl_ctrl; + + ovl_ctrl =3D vop2_readl(vop2, RK3576_OVL_CTRL(vp->id)); + if (vcstate->yuv_overlay) + ovl_ctrl |=3D RK3576_OVL_CTRL__YUV_MODE; + else + ovl_ctrl &=3D ~RK3576_OVL_CTRL__YUV_MODE; + + vop2_writel(vop2, RK3576_OVL_CTRL(vp->id), ovl_ctrl); + + drm_atomic_crtc_for_each_plane(plane, &vp->crtc) { + struct vop2_win *win =3D to_vop2_win(plane); + + layer_sel &=3D ~RK3568_OVL_LAYER_SEL__LAYER(plane->state->normalized_zpo= s, + 0xf); + layer_sel |=3D RK3568_OVL_LAYER_SEL__LAYER(plane->state->normalized_zpos, + win->data->layer_sel_id[vp->id]); + } + + vop2_writel(vop2, RK3576_OVL_LAYER_SEL(vp->id), layer_sel); +} + +static void rk3576_vop2_setup_dly_for_windows(struct vop2_video_port *vp) +{ + struct drm_plane *plane; + struct vop2_win *win; + + drm_atomic_crtc_for_each_plane(plane, &vp->crtc) { + win =3D to_vop2_win(plane); + vop2_win_write(win, VOP2_WIN_DLY_NUM, 0); + } +} + +static void rk3576_vop2_setup_overlay(struct vop2_video_port *vp) +{ + struct vop2 *vop2 =3D vp->vop2; + struct drm_crtc *crtc =3D &vp->crtc; + struct drm_plane *plane; + + vp->win_mask =3D 0; + + drm_atomic_crtc_for_each_plane(plane, crtc) { + struct vop2_win *win =3D to_vop2_win(plane); + + win->delay =3D win->data->dly[VOP2_DLY_MODE_DEFAULT]; + + vp->win_mask |=3D BIT(win->data->phys_id); + + if (vop2_cluster_window(win)) + vop2_setup_cluster_alpha(vop2, win); + } + + if (!vp->win_mask) + return; + + rk3576_vop2_setup_layer_mixer(vp); + vop2_setup_alpha(vp); + rk3576_vop2_setup_dly_for_windows(vp); +} + static void rk3568_vop2_setup_bg_dly(struct vop2_video_port *vp) { struct drm_crtc *crtc =3D &vp->crtc; @@ -1594,12 +2274,38 @@ static void rk3568_vop2_setup_bg_dly(struct vop2_vi= deo_port *vp) vop2_vp_write(vp, RK3568_VP_PRE_SCAN_HTIMING, pre_scan_dly); } =20 +static void rk3576_vop2_setup_bg_dly(struct vop2_video_port *vp) +{ + struct drm_crtc *crtc =3D &vp->crtc; + struct drm_display_mode *mode =3D &crtc->state->adjusted_mode; + u16 hdisplay =3D mode->crtc_hdisplay; + u16 hsync_len =3D mode->crtc_hsync_end - mode->crtc_hsync_start; + u32 bg_dly; + u32 pre_scan_dly; + + bg_dly =3D vp->data->pre_scan_max_dly[VOP2_DLY_WIN] + + vp->data->pre_scan_max_dly[VOP2_DLY_LAYER_MIX] + + vp->data->pre_scan_max_dly[VOP2_DLY_HDR_MIX]; + + vop2_writel(vp->vop2, RK3576_OVL_BG_MIX_CTRL(vp->id), + FIELD_PREP(RK3576_OVL_BG_MIX_CTRL__BG_DLY, bg_dly)); + + pre_scan_dly =3D ((bg_dly + (hdisplay >> 1) - 1) << 16) | hsync_len; + vop2_vp_write(vp, RK3568_VP_PRE_SCAN_HTIMING, pre_scan_dly); +} + static const struct vop2_ops rk3568_vop_ops =3D { .setup_intf_mux =3D rk3568_set_intf_mux, .setup_bg_dly =3D rk3568_vop2_setup_bg_dly, .setup_overlay =3D rk3568_vop2_setup_overlay, }; =20 +static const struct vop2_ops rk3576_vop_ops =3D { + .setup_intf_mux =3D rk3576_set_intf_mux, + .setup_bg_dly =3D rk3576_vop2_setup_bg_dly, + .setup_overlay =3D rk3576_vop2_setup_overlay, +}; + static const struct vop2_ops rk3588_vop_ops =3D { .setup_intf_mux =3D rk3588_set_intf_mux, .setup_bg_dly =3D rk3568_vop2_setup_bg_dly, @@ -1644,6 +2350,25 @@ static const struct vop2_data rk3568_vop =3D { .soc_id =3D 3568, }; =20 +static const struct vop2_data rk3576_vop =3D { + .version =3D VOP_VERSION_RK3576, + .feature =3D VOP2_FEATURE_HAS_SYS_PMU, + .nr_vps =3D 3, + .max_input =3D { 4096, 4320 }, + .max_output =3D { 4096, 4320 }, + .vp =3D rk3576_vop_video_ports, + .win =3D rk3576_vop_win_data, + .win_size =3D ARRAY_SIZE(rk3576_vop_win_data), + .cluster_reg =3D rk3576_vop_cluster_regs, + .nr_cluster_regs =3D ARRAY_SIZE(rk3576_vop_cluster_regs), + .smart_reg =3D rk3576_vop_smart_regs, + .nr_smart_regs =3D ARRAY_SIZE(rk3576_vop_smart_regs), + .regs_dump =3D rk3576_regs_dump, + .regs_dump_size =3D ARRAY_SIZE(rk3576_regs_dump), + .ops =3D &rk3576_vop_ops, + .soc_id =3D 3576, +}; + static const struct vop2_data rk3588_vop =3D { .version =3D VOP_VERSION_RK3588, .feature =3D VOP2_FEATURE_HAS_SYS_GRF | VOP2_FEATURE_HAS_VO1_GRF | @@ -1671,6 +2396,9 @@ static const struct of_device_id vop2_dt_match[] =3D { }, { .compatible =3D "rockchip,rk3568-vop", .data =3D &rk3568_vop, + }, { + .compatible =3D "rockchip,rk3576-vop", + .data =3D &rk3576_vop, }, { .compatible =3D "rockchip,rk3588-vop", .data =3D &rk3588_vop --=20 2.34.1