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([2405:201:d007:50c2:4888:86b4:6f32:9ae]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20794735728sm83021645ad.271.2024.09.19.11.29.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Sep 2024 11:29:59 -0700 (PDT) From: Vamsi Krishna Brahmajosyula To: gustavo.sousa@intel.com, jani.nikula@linux.intel.com, rodrigo.vivi@intel.com, joonas.lahtinen@linux.intel.com, tursulin@ursulin.net, airlied@gmail.com, daniel@ffwll.ch Cc: skhan@linuxfoundation.org, intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH] drm/i915/cx0: Set power state to ready only on owned PHY lanes Date: Thu, 19 Sep 2024 23:59:52 +0530 Message-ID: <20240919182952.51326-1-vamsikrishna.brahmajosyula@gmail.com> X-Mailer: git-send-email 2.46.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In DP alt mode, when pin assignment is D, only one PHY lane is owned by the display. intel_cx0pll_enable currently performs a power state ready on both the lanes in all cases. Address the todo to perfom power state ready on owned lanes. Tested on Meteor Lake-P [Intel Arc Graphics] with DP alt mode. v2 -> v3: - Fix changelog per Jani Nikula's feedback v1 -> v2: Address Gustavo Sousa's feedback - Use owned lanes mask to set Phy power state to Ready, instead of maxpclk_lane with DP alt mode check. - Owned lanes are obtained from intel_cx0_get_owned_lane_mask(). Signed-off-by: Vamsi Krishna Brahmajosyula --- Patch version removed so that patchwork would recognize the entry drivers/gpu/drm/i915/display/intel_cx0_phy.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm= /i915/display/intel_cx0_phy.c index 4a6c3040ca15..cbed53d3b250 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c @@ -2934,6 +2934,7 @@ static void intel_cx0pll_enable(struct intel_encoder = *encoder, enum phy phy =3D intel_encoder_to_phy(encoder); struct intel_digital_port *dig_port =3D enc_to_dig_port(encoder); bool lane_reversal =3D dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL; + u8 owned_lane_mask =3D intel_cx0_get_owned_lane_mask(encoder); u8 maxpclk_lane =3D lane_reversal ? INTEL_CX0_LANE1 : INTEL_CX0_LANE0; intel_wakeref_t wakeref =3D intel_cx0_phy_transaction_begin(encoder); @@ -2948,10 +2949,9 @@ static void intel_cx0pll_enable(struct intel_encoder= *encoder, intel_cx0_phy_lane_reset(encoder, lane_reversal); =20 /* - * 3. Change Phy power state to Ready. - * TODO: For DP alt mode use only one lane. + * 3. Change Phy power state to Ready on owned lanes. */ - intel_cx0_powerdown_change_sequence(encoder, INTEL_CX0_BOTH_LANES, + intel_cx0_powerdown_change_sequence(encoder, owned_lane_mask, CX0_P2_STATE_READY); =20 /* base-commit: ad060dbbcfcfcba624ef1a75e1d71365a98b86d8 --=20 2.46.0