From nobody Fri Nov 29 14:31:40 2024 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AE7A21A01D8; Thu, 19 Sep 2024 09:44:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726739052; cv=none; b=h2SmRKqVNKLMPbPWAfGObZEgSEl4mu8HcM/CJ4vV7MpVSqQ3t3hj6Eud33xudsPIqHKLQXaT+qu4nJTnpc5pambZx0Bqc2A3UpKUI4JOwsTDWSXph/WU2bp9hmHeSD5o+yohjIEI0L3/iEWFMIjF1IZtdKauVD+e1myhMU9v6qw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726739052; c=relaxed/simple; bh=gAlJ7gDxm06bfoNA93gike3Nx8ni1gIqR8faTAfBL60=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=eOJeIoWV+MbYgnIz+JLGu/AWPKCgNTdItFFs+98ljETjGlqGooXmtzZ5rIXsmch23QjoGt7foSL9pWXME+DM+DU505wBnvWqkCvy6nRaMudWbpL2frn4zSsG8VXTE4Pl/7jzGmf9AfyHDJH203XFDoFLMEz8WB/vsgiVXF2b0+w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Thu, 19 Sep 2024 17:43:39 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Thu, 19 Sep 2024 17:43:39 +0800 From: Billy Tsai To: , , , , , , , , , , , , , , Subject: [PATCH v4 6/6] gpio: aspeed: Add the flush write to ensure the write complete. Date: Thu, 19 Sep 2024 17:43:39 +0800 Message-ID: <20240919094339.2407641-7-billy_tsai@aspeedtech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240919094339.2407641-1-billy_tsai@aspeedtech.com> References: <20240919094339.2407641-1-billy_tsai@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Performing a dummy read ensures that the register write operation is fully completed, mitigating any potential bus delays that could otherwise impact the frequency of bitbang usage. E.g., if the JTAG application uses GPIO to control the JTAG pins (TCK, TMS, TDI, TDO, and TRST), and the application sets the TCK clock to 1 MHz, the GPIO=E2=80=99s high/low transitions will r= ely on a delay function to ensure the clock frequency does not exceed 1 MHz. However, this can lead to rapid toggling of the GPIO because the write operation is POSTed and does not wait for a bus acknowledgment. Signed-off-by: Billy Tsai Reviewed-by: Linus Walleij --- drivers/gpio/gpio-aspeed.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpio/gpio-aspeed.c b/drivers/gpio/gpio-aspeed.c index c811e84db0b9..daa12e21d946 100644 --- a/drivers/gpio/gpio-aspeed.c +++ b/drivers/gpio/gpio-aspeed.c @@ -400,6 +400,8 @@ static void __aspeed_gpio_set(struct gpio_chip *gc, uns= igned int offset, struct aspeed_gpio *gpio =3D gpiochip_get_data(gc); =20 gpio->config->llops->reg_bit_set(gpio, offset, reg_val, val); + // flush write + gpio->config->llops->reg_bits_get(gpio, offset, reg_val); } =20 static void aspeed_gpio_set(struct gpio_chip *gc, unsigned int offset, --=20 2.25.1