From nobody Fri Nov 29 13:42:32 2024 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 68BAB199240; Thu, 19 Sep 2024 09:18:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726737520; cv=none; b=P4gZl9insRQwqQ/VcJOu5NQo75jDOVDyj5et99D9HDwLZrBTws/+rphuJ3YmTgAWcvQvONTXVeH+NUb4t3n5BG8Y6C0ngBwdQPt9Bx/fkLxB/jYWHEk1dUItQ/19AmVUjzwTdRiLKDHmGFo5boKWRRKmbLUv2NXSeN/20mcnhQQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726737520; c=relaxed/simple; bh=Vx9E0NW09bVtjBV5lKfEh6WBcSKCDD7TcmzItk//06E=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=WJfPeRYh3OM29EOBZqZRx5+uRlrVXoxxa4v2/wsfdlG4RoCCtbQFIgqQ3qIG2H9DELnR1AMSSb2XtupISFiN5eHfa8M2saGHeqmW9XqzeO4xXgX99OAAXT1ZpWKaLMEKcly119a0IhuqLu3fSLiBNG7UVsSJy6VKTFkuckUjtZY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=SKOUz0r9; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="SKOUz0r9" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1726737516; bh=Vx9E0NW09bVtjBV5lKfEh6WBcSKCDD7TcmzItk//06E=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=SKOUz0r9RYvKKUufZKS1qPQyag/Ytz82TxUpll710o+RkjFxibx0os50ztCNhxc/B JlyW7HhfTFaJgP1JLSRhHGexhWuSy8jTOP0S2YdMIeSRlfjfyKqDIXpaxx0Ma0qskC 46IKaUNUcOG93o45ZFaoEeUU52kAzLEsE/y587YgiQTymr2B1bNdpG2e6/yMKF8ven 1C05cdY1O+/m5cnBMHrs8n57ojNOLmYBiHT9VofpGhYMV24c1PC/J4BTwuvBLhJl+U jb+ILnSJ+NMCd8sTh2PURFv3c1fxF97s/hl05dgT2GvOMne8HTysvY8AVXwsv2mQTN XevkQSNoH1gNA== Received: from jupiter.universe (dyndsl-091-248-208-160.ewe-ip-backbone.de [91.248.208.160]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) (Authenticated sender: sre) by bali.collaboradmins.com (Postfix) with ESMTPSA id 8E6B217E10AE; Thu, 19 Sep 2024 11:18:36 +0200 (CEST) Received: by jupiter.universe (Postfix, from userid 1000) id 582B5480075; Thu, 19 Sep 2024 11:18:36 +0200 (CEST) From: Sebastian Reichel To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Ulf Hansson Cc: Elaine Zhang , =?UTF-8?q?Adri=C3=A1n=20Mart=C3=ADnez=20Larumbe?= , Boris Brezillon , Chen-Yu Tsai , devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Sebastian Reichel , kernel@collabora.com Subject: [PATCH v2 1/6] pmdomain: rockchip: cleanup mutex handling in rockchip_pd_power Date: Thu, 19 Sep 2024 11:12:42 +0200 Message-ID: <20240919091834.83572-2-sebastian.reichel@collabora.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240919091834.83572-1-sebastian.reichel@collabora.com> References: <20240919091834.83572-1-sebastian.reichel@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use the cleanup infrastructure to handle the mutex, which slightly improve code readability for this function. Reviewed-by: Heiko Stuebner Tested-by: Adrian Larumbe # On Rock 5B Signed-off-by: Sebastian Reichel --- drivers/pmdomain/rockchip/pm-domains.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/pmdomain/rockchip/pm-domains.c b/drivers/pmdomain/rock= chip/pm-domains.c index 9b76b62869d0..4f7021f47261 100644 --- a/drivers/pmdomain/rockchip/pm-domains.c +++ b/drivers/pmdomain/rockchip/pm-domains.c @@ -529,13 +529,12 @@ static int rockchip_pd_power(struct rockchip_pm_domai= n *pd, bool power_on) struct rockchip_pmu *pmu =3D pd->pmu; int ret; =20 - mutex_lock(&pmu->mutex); + guard(mutex)(&pmu->mutex); =20 if (rockchip_pmu_domain_is_on(pd) !=3D power_on) { ret =3D clk_bulk_enable(pd->num_clks, pd->clks); if (ret < 0) { dev_err(pmu->dev, "failed to enable clocks\n"); - mutex_unlock(&pmu->mutex); return ret; } =20 @@ -558,7 +557,6 @@ static int rockchip_pd_power(struct rockchip_pm_domain = *pd, bool power_on) clk_bulk_disable(pd->num_clks, pd->clks); } =20 - mutex_unlock(&pmu->mutex); return 0; } =20 --=20 2.45.2 From nobody Fri Nov 29 13:42:32 2024 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 68B5419923A; Thu, 19 Sep 2024 09:18:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726737520; cv=none; b=AfYfJXNdMaoef9QkWXsqjkHhmasyaLbOXARp4sJHebpRmRvtOm8b0tVVOavTgTn3CPgDIaGgX1K2W/94qG5pJb49yIzKQmskLDoIibUV1ykclNQ6LPTldQ/Eiod10c5ueqnK4jn0sZS1zncEX/UdTA7HPIxjo5cn1CGuL4262oM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726737520; c=relaxed/simple; bh=QrWsVp0O3acriip4USpkmSpsqOVLVMd3IZ179rzxzbI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=YBojahNarlnW2+8v+oMc0V0qyXtDU7W5Fy4/QEgmTkic4HW0tn9iUCpZzuz3McNExJo93mKffdBfwu0zje0rYW9MAOab6kpEnIALqurI4mOdRc+A33XuAFCJ6Djivc+tzia2C2ejwmoZQ8m1hRSI4jkcVS7TlRyBBFkhuTq+S8U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=nX2d0KxK; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="nX2d0KxK" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1726737516; bh=QrWsVp0O3acriip4USpkmSpsqOVLVMd3IZ179rzxzbI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=nX2d0KxKVHyJVZbo2V53bBjuzcXznsevjWqf7ehrlfLkvc/G+6qW4IJ7MRivWW67Z K5HUaxwtPXnQd6wGRxtUG/YmuBaAIM4fqEGnH6jijOCDj/ZrUGuhKB0g032Z6vJp6Z J9O4DGLl9+zeBKbrjN/spdWRu6ytbn3VKPqsdlZ1G9cN2xZc+Su97m1PZYVMFO8r4w l4PzdZd1XQKRPeKJ+7nVR3EXgMZD7Rg6UJYEp463+ydVRt0njzgaGL7oDd1lf5Pj+h HdDgmEhMpnO5RvDdtuAeo65581oX/hz86nhHRXC0RVoJxM5oi7OFIdap9PuY7UZ8W0 nYEL9MCjFgRvQ== Received: from jupiter.universe (dyndsl-091-248-208-160.ewe-ip-backbone.de [91.248.208.160]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) (Authenticated sender: sre) by bali.collaboradmins.com (Postfix) with ESMTPSA id 8C84917E10AB; Thu, 19 Sep 2024 11:18:36 +0200 (CEST) Received: by jupiter.universe (Postfix, from userid 1000) id 5A37A480084; Thu, 19 Sep 2024 11:18:36 +0200 (CEST) From: Sebastian Reichel To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Ulf Hansson Cc: Elaine Zhang , =?UTF-8?q?Adri=C3=A1n=20Mart=C3=ADnez=20Larumbe?= , Boris Brezillon , Chen-Yu Tsai , devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Sebastian Reichel , kernel@collabora.com Subject: [PATCH v2 2/6] pmdomain: rockchip: forward rockchip_do_pmu_set_power_domain errors Date: Thu, 19 Sep 2024 11:12:43 +0200 Message-ID: <20240919091834.83572-3-sebastian.reichel@collabora.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240919091834.83572-1-sebastian.reichel@collabora.com> References: <20240919091834.83572-1-sebastian.reichel@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Currently rockchip_do_pmu_set_power_domain prints a warning if there have been errors turning on the power domain, but it does not return any errors and rockchip_pd_power() tries to continue setting up the QOS registers. This usually results in accessing unpowered registers, which triggers an SError and a full system hang. This improves the error handling by forwarding the error to avoid kernel panics. Reviewed-by: Heiko Stuebner Tested-by: Adrian Larumbe # On Rock 5B Signed-off-by: Sebastian Reichel --- drivers/pmdomain/rockchip/pm-domains.c | 34 +++++++++++++++++--------- 1 file changed, 22 insertions(+), 12 deletions(-) diff --git a/drivers/pmdomain/rockchip/pm-domains.c b/drivers/pmdomain/rock= chip/pm-domains.c index 4f7021f47261..5e5291dedd28 100644 --- a/drivers/pmdomain/rockchip/pm-domains.c +++ b/drivers/pmdomain/rockchip/pm-domains.c @@ -488,16 +488,17 @@ static int rockchip_pmu_domain_mem_reset(struct rockc= hip_pm_domain *pd) return ret; } =20 -static void rockchip_do_pmu_set_power_domain(struct rockchip_pm_domain *pd, - bool on) +static int rockchip_do_pmu_set_power_domain(struct rockchip_pm_domain *pd, + bool on) { struct rockchip_pmu *pmu =3D pd->pmu; struct generic_pm_domain *genpd =3D &pd->genpd; u32 pd_pwr_offset =3D pd->info->pwr_offset; bool is_on, is_mem_on =3D false; + int ret; =20 if (pd->info->pwr_mask =3D=3D 0) - return; + return 0; =20 if (on && pd->info->mem_status_mask) is_mem_on =3D rockchip_pmu_domain_is_mem_on(pd); @@ -512,16 +513,21 @@ static void rockchip_do_pmu_set_power_domain(struct r= ockchip_pm_domain *pd, =20 wmb(); =20 - if (is_mem_on && rockchip_pmu_domain_mem_reset(pd)) - return; + if (is_mem_on) { + ret =3D rockchip_pmu_domain_mem_reset(pd); + if (ret) + return ret; + } =20 - if (readx_poll_timeout_atomic(rockchip_pmu_domain_is_on, pd, is_on, - is_on =3D=3D on, 0, 10000)) { - dev_err(pmu->dev, - "failed to set domain '%s', val=3D%d\n", - genpd->name, is_on); - return; + ret =3D readx_poll_timeout_atomic(rockchip_pmu_domain_is_on, pd, is_on, + is_on =3D=3D on, 0, 10000); + if (ret) { + dev_err(pmu->dev, "failed to set domain '%s' %s, val=3D%d\n", + genpd->name, on ? "on" : "off", is_on); + return ret; } + + return 0; } =20 static int rockchip_pd_power(struct rockchip_pm_domain *pd, bool power_on) @@ -545,7 +551,11 @@ static int rockchip_pd_power(struct rockchip_pm_domain= *pd, bool power_on) rockchip_pmu_set_idle_request(pd, true); } =20 - rockchip_do_pmu_set_power_domain(pd, power_on); + ret =3D rockchip_do_pmu_set_power_domain(pd, power_on); + if (ret < 0) { + clk_bulk_disable(pd->num_clks, pd->clks); + return ret; + } =20 if (power_on) { /* if powering up, leave idle mode */ --=20 2.45.2 From nobody Fri Nov 29 13:42:32 2024 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 514DF12E48; Thu, 19 Sep 2024 09:18:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726737520; cv=none; b=XXHr0g9QYh2P1P3GkOQXOkegRpMQBjFL7giwWhHxv/+X+0wdvAtJOZKSyt92fy3OLf2enFbYljb/Cha0fmd/egql0pyWnmlzGtMhRqR0FXVxuYOM60wI++Ywju5TkhVBnQ/fPMssu08RCxbJX/fER5zYyGq2mhdFzKtHO+L4lgg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726737520; c=relaxed/simple; bh=Zxm1uLqr1zUwk6C1A4ApcASI47Ep0+VpPk2kApygxO0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=AbiQ8YwnIVQuuXkIasZ8rD4/oPCd6xr+mXih/OarE/sgXlckGPM/eayPBAUyy/xymR6dRfn1m8902Vuy2TaG9lpTkUjDgV7kvP35HlzIdsMca8fcLtzjvAfEGl5OSwFiDF94TXJMeC7M91OUcZVxixl+HWCxBzcm2Yd1LVm1rIY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=p8IxNupL; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="p8IxNupL" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1726737516; bh=Zxm1uLqr1zUwk6C1A4ApcASI47Ep0+VpPk2kApygxO0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=p8IxNupLEi1CO37HBlbjusvnuFIXtFUWOIq1ZrBo8FjbwNC7puM9FfInIJkgLKdc6 zFt/0ho4FEjSfoa4Ja6R6syk1kgexB3Z/KzPh8jNChqKcLrNw2wBxOAP1Pw1c1y4I2 7YRI4G66Q1bfNahuxFF91JdiKGBJ7lQ4wA3NpAgebeszWU1pX6MF6ocUB+fAnLYVAj V1Vsd7EL9OiOaP2s83dtJBfN3rt1itloAj1FBKBkhAjAyAAdij1Vq52KCAH0DshQ77 jqRyRSQwfmbAge5AfR80K9MA07t5cLDEDLd1xgJFa+bkInNg4runv4f2PBjci2Oqhf AqKUuVqYYUaow== Received: from jupiter.universe (dyndsl-091-248-208-160.ewe-ip-backbone.de [91.248.208.160]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) (Authenticated sender: sre) by bali.collaboradmins.com (Postfix) with ESMTPSA id 808BF17E1082; Thu, 19 Sep 2024 11:18:36 +0200 (CEST) Received: by jupiter.universe (Postfix, from userid 1000) id 5C1B5480085; Thu, 19 Sep 2024 11:18:36 +0200 (CEST) From: Sebastian Reichel To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Ulf Hansson Cc: Elaine Zhang , =?UTF-8?q?Adri=C3=A1n=20Mart=C3=ADnez=20Larumbe?= , Boris Brezillon , Chen-Yu Tsai , devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Sebastian Reichel , kernel@collabora.com Subject: [PATCH v2 3/6] pmdomain: rockchip: reduce indentation in rockchip_pd_power Date: Thu, 19 Sep 2024 11:12:44 +0200 Message-ID: <20240919091834.83572-4-sebastian.reichel@collabora.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240919091834.83572-1-sebastian.reichel@collabora.com> References: <20240919091834.83572-1-sebastian.reichel@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Rework the logic, so that the function exits early when the power domain state is already correct to reduce code indentation. No functional change intended. Reviewed-by: Heiko Stuebner Tested-by: Adrian Larumbe # On Rock 5B Signed-off-by: Sebastian Reichel --- drivers/pmdomain/rockchip/pm-domains.c | 45 +++++++++++++------------- 1 file changed, 23 insertions(+), 22 deletions(-) diff --git a/drivers/pmdomain/rockchip/pm-domains.c b/drivers/pmdomain/rock= chip/pm-domains.c index 5e5291dedd28..663d390faaeb 100644 --- a/drivers/pmdomain/rockchip/pm-domains.c +++ b/drivers/pmdomain/rockchip/pm-domains.c @@ -537,36 +537,37 @@ static int rockchip_pd_power(struct rockchip_pm_domai= n *pd, bool power_on) =20 guard(mutex)(&pmu->mutex); =20 - if (rockchip_pmu_domain_is_on(pd) !=3D power_on) { - ret =3D clk_bulk_enable(pd->num_clks, pd->clks); - if (ret < 0) { - dev_err(pmu->dev, "failed to enable clocks\n"); - return ret; - } + if (rockchip_pmu_domain_is_on(pd) =3D=3D power_on) + return 0; =20 - if (!power_on) { - rockchip_pmu_save_qos(pd); + ret =3D clk_bulk_enable(pd->num_clks, pd->clks); + if (ret < 0) { + dev_err(pmu->dev, "failed to enable clocks\n"); + return ret; + } =20 - /* if powering down, idle request to NIU first */ - rockchip_pmu_set_idle_request(pd, true); - } + if (!power_on) { + rockchip_pmu_save_qos(pd); =20 - ret =3D rockchip_do_pmu_set_power_domain(pd, power_on); - if (ret < 0) { - clk_bulk_disable(pd->num_clks, pd->clks); - return ret; - } + /* if powering down, idle request to NIU first */ + rockchip_pmu_set_idle_request(pd, true); + } =20 - if (power_on) { - /* if powering up, leave idle mode */ - rockchip_pmu_set_idle_request(pd, false); + ret =3D rockchip_do_pmu_set_power_domain(pd, power_on); + if (ret < 0) { + clk_bulk_disable(pd->num_clks, pd->clks); + return ret; + } =20 - rockchip_pmu_restore_qos(pd); - } + if (power_on) { + /* if powering up, leave idle mode */ + rockchip_pmu_set_idle_request(pd, false); =20 - clk_bulk_disable(pd->num_clks, pd->clks); + rockchip_pmu_restore_qos(pd); } =20 + clk_bulk_disable(pd->num_clks, pd->clks); + return 0; } =20 --=20 2.45.2 From nobody Fri Nov 29 13:42:32 2024 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5153C19922E; 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Thu, 19 Sep 2024 11:18:36 +0200 (CEST) Received: by jupiter.universe (Postfix, from userid 1000) id 5DE28480086; Thu, 19 Sep 2024 11:18:36 +0200 (CEST) From: Sebastian Reichel To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Ulf Hansson Cc: Elaine Zhang , =?UTF-8?q?Adri=C3=A1n=20Mart=C3=ADnez=20Larumbe?= , Boris Brezillon , Chen-Yu Tsai , devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Sebastian Reichel , kernel@collabora.com Subject: [PATCH v2 4/6] dt-bindings: power: rockchip: add regulator support Date: Thu, 19 Sep 2024 11:12:45 +0200 Message-ID: <20240919091834.83572-5-sebastian.reichel@collabora.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240919091834.83572-1-sebastian.reichel@collabora.com> References: <20240919091834.83572-1-sebastian.reichel@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add optional support for a voltage supply required to enable a power domain. The binding follows the way it is handled by the Mediatek binding to keep things consistent. This will initially be used by the RK3588 GPU power domain, which fails to be enabled when the GPU regulator is not enabled. Reviewed-by: Heiko Stuebner Acked-by: Rob Herring (Arm) Signed-off-by: Sebastian Reichel --- .../devicetree/bindings/power/rockchip,power-controller.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/power/rockchip,power-control= ler.yaml b/Documentation/devicetree/bindings/power/rockchip,power-controlle= r.yaml index 0d5e999a58f1..0b4c5b174812 100644 --- a/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml +++ b/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml @@ -131,6 +131,9 @@ $defs: A number of phandles to clocks that need to be enabled while power domain switches state. =20 + domain-supply: + description: domain regulator supply. + pm_qos: $ref: /schemas/types.yaml#/definitions/phandle-array items: --=20 2.45.2 From nobody Fri Nov 29 13:42:32 2024 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C0E3419ABC6; Thu, 19 Sep 2024 09:18:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726737523; cv=none; b=BPz4qhAKhCJ6egOgI+OBbh5xBdw7Ew1+7b4I10f02fdbkDhVXHGY8WDcyi/urig1YVRpVwkSeED+ZQk5uPIbUpPZV1cc7c3UwsItRfhF2QSeZ+jv74EKkidtB+fC6CYPFlU1OqAv5Sxl0b1KTdCMvVrmCjbVyPJObVWrbdo3xZM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726737523; c=relaxed/simple; bh=5X2JcD6nxPTdz5lMfErMebNbQNrki2yIYXCau8/4xYY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=uUO7Up5rYsbh5FIpyrndImBDNwb3k8pYQnpWodbWtm6wKP+jiFvEXuqw/JsIQ9m1hbBTlkMa+3zxFgSUsFLwvobyF7BGCT/UR96ieUuQscB+FxOQI59zlbnTAYQcJyUElFeDuv1JKGQBqYgTWMcPlGFna6HE9oAHHfyGE0Pi9Ig= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=XQ0Mwkmk; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="XQ0Mwkmk" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1726737516; bh=5X2JcD6nxPTdz5lMfErMebNbQNrki2yIYXCau8/4xYY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=XQ0Mwkmk5GWH0Rq6ltYmTNoJC6Hwcm7PQjj+VB0c5RIm6hSfZxnIfCzQuSBij7HvB 7JS6h047lXbzKvXkwks9j9vfBF97HoBcKHHaMXb9YVxii30KTcZ6iqDEm3CVAISMaU LNz4SViNLTbTjasgJNbVTYqYHVvFPze3l3G9/Qj51FJ/8nKfgfwRSTZbS2c4A864Tz JYek4jlRgaI5yug+H18LC3RClfrx3toHzDBFV11WGEsLuidblth1NWkgWYRi0fhrlq 1RxgdfjZITTfFvzxaBAvIAYmy6HryNmSSMoQ22IwjPMISxfbC9ZKeWEDNTVoeHm6n6 gkR0/Jm+lWSqg== Received: from jupiter.universe (dyndsl-091-248-208-160.ewe-ip-backbone.de [91.248.208.160]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) (Authenticated sender: sre) by bali.collaboradmins.com (Postfix) with ESMTPSA id B8DD417E10AF; Thu, 19 Sep 2024 11:18:36 +0200 (CEST) Received: by jupiter.universe (Postfix, from userid 1000) id 5FA46480088; Thu, 19 Sep 2024 11:18:36 +0200 (CEST) From: Sebastian Reichel To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Ulf Hansson Cc: Elaine Zhang , =?UTF-8?q?Adri=C3=A1n=20Mart=C3=ADnez=20Larumbe?= , Boris Brezillon , Chen-Yu Tsai , devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Sebastian Reichel , kernel@collabora.com Subject: [PATCH v2 5/6] pmdomain: rockchip: add regulator support Date: Thu, 19 Sep 2024 11:12:46 +0200 Message-ID: <20240919091834.83572-6-sebastian.reichel@collabora.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240919091834.83572-1-sebastian.reichel@collabora.com> References: <20240919091834.83572-1-sebastian.reichel@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Some power domains require extra voltages to be applied. For example trying to enable the GPU domain on RK3588 fails when the SoC does not have VDD GPU enabled. The solution to temporarily change the device's device tree node has been taken over from the Mediatek power domain driver. The regulator is not acquired at probe time, since that creates circular dependencies. The power domain driver must be probed early, since SoC peripherals need it. Regulators on the other hand depend on SoC peripherals like SPI, I2C or GPIO. Reviewed-by: Heiko Stuebner Tested-by: Adrian Larumbe # On Rock 5B Signed-off-by: Sebastian Reichel --- drivers/pmdomain/rockchip/pm-domains.c | 56 +++++++++++++++++++++++++- 1 file changed, 54 insertions(+), 2 deletions(-) diff --git a/drivers/pmdomain/rockchip/pm-domains.c b/drivers/pmdomain/rock= chip/pm-domains.c index 663d390faaeb..4bc17b588419 100644 --- a/drivers/pmdomain/rockchip/pm-domains.c +++ b/drivers/pmdomain/rockchip/pm-domains.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -89,6 +90,8 @@ struct rockchip_pm_domain { u32 *qos_save_regs[MAX_QOS_REGS_NUM]; int num_clks; struct clk_bulk_data *clks; + struct device_node *node; + struct regulator *supply; }; =20 struct rockchip_pmu { @@ -571,18 +574,66 @@ static int rockchip_pd_power(struct rockchip_pm_domai= n *pd, bool power_on) return 0; } =20 +static int rockchip_pd_regulator_disable(struct rockchip_pm_domain *pd) +{ + return pd->supply ? regulator_disable(pd->supply) : 0; +} + +static int rockchip_pd_regulator_enable(struct rockchip_pm_domain *pd) +{ + struct rockchip_pmu *pmu =3D pd->pmu; + struct device_node *main_node; + + if (!pd->supply) { + /* + * Find regulator in current power domain node. + * devm_regulator_get() finds regulator in a node and its child + * node, so set of_node to current power domain node then change + * back to original node after regulator is found for current + * power domain node. + */ + main_node =3D pmu->dev->of_node; + pmu->dev->of_node =3D pd->node; + pd->supply =3D devm_regulator_get(pmu->dev, "domain"); + pmu->dev->of_node =3D main_node; + if (IS_ERR(pd->supply)) { + pd->supply =3D NULL; + return 0; + } + } + + return regulator_enable(pd->supply); +} + static int rockchip_pd_power_on(struct generic_pm_domain *domain) { struct rockchip_pm_domain *pd =3D to_rockchip_pd(domain); + int ret; + + ret =3D rockchip_pd_regulator_enable(pd); + if (ret) { + dev_err(pd->pmu->dev, "Failed to enable supply: %d\n", ret); + return ret; + } =20 - return rockchip_pd_power(pd, true); + ret =3D rockchip_pd_power(pd, true); + if (ret) + rockchip_pd_regulator_disable(pd); + + return ret; } =20 static int rockchip_pd_power_off(struct generic_pm_domain *domain) { struct rockchip_pm_domain *pd =3D to_rockchip_pd(domain); + int ret; =20 - return rockchip_pd_power(pd, false); + ret =3D rockchip_pd_power(pd, false); + if (ret) + return ret; + + rockchip_pd_regulator_disable(pd); + return ret; } =20 static int rockchip_pd_attach_dev(struct generic_pm_domain *genpd, @@ -663,6 +714,7 @@ static int rockchip_pm_add_one_domain(struct rockchip_p= mu *pmu, =20 pd->info =3D pd_info; pd->pmu =3D pmu; + pd->node =3D node; =20 pd->num_clks =3D of_clk_get_parent_count(node); if (pd->num_clks > 0) { --=20 2.45.2 From nobody Fri Nov 29 13:42:32 2024 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8167819A2A3; Thu, 19 Sep 2024 09:18:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Thu, 19 Sep 2024 11:18:36 +0200 (CEST) Received: by jupiter.universe (Postfix, from userid 1000) id 6153048008A; Thu, 19 Sep 2024 11:18:36 +0200 (CEST) From: Sebastian Reichel To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Ulf Hansson Cc: Elaine Zhang , =?UTF-8?q?Adri=C3=A1n=20Mart=C3=ADnez=20Larumbe?= , Boris Brezillon , Chen-Yu Tsai , devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Sebastian Reichel , kernel@collabora.com Subject: [PATCH v2 6/6] arm64: dts: rockchip: Add GPU power domain regulator dependency for RK3588 Date: Thu, 19 Sep 2024 11:12:47 +0200 Message-ID: <20240919091834.83572-7-sebastian.reichel@collabora.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240919091834.83572-1-sebastian.reichel@collabora.com> References: <20240919091834.83572-1-sebastian.reichel@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Enabling the GPU power domain requires that the GPU regulator is enabled. The regulator is enabled at boot time, but automatically gets disabled when there are no users. If the GPU driver is not probed at boot time or rebound while the system is running the system will try to enable the power domain before the regulator is enabled resulting in a failure hanging the whole system. Avoid this by adding an explicit dependency. Reported-by: Adri=C3=A1n Mart=C3=ADnez Larumbe Tested-by: Adrian Larumbe # On Rock 5B Signed-off-by: Sebastian Reichel --- arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts | 4 ++++ arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 2 +- arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5.dtsi | 4 ++++ arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588.dtsi | 4 ++++ arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts | 4 ++++ arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts | 4 ++++ arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts | 4 ++++ arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 4 ++++ arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi | 4 ++++ arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts | 4 ++++ arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts | 4 ++++ arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts | 4 ++++ 12 files changed, 45 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts b/arch/ar= m64/boot/dts/rockchip/rk3588-armsom-sige7.dts index c667704ba985..00a1cd96781d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts @@ -286,6 +286,10 @@ &pcie3x4 { status =3D "okay"; }; =20 +&pd_gpu { + domain-supply =3D <&vdd_gpu_s0>; +}; + &pinctrl { hym8563 { hym8563_int: hym8563-int { diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boo= t/dts/rockchip/rk3588-base.dtsi index 905f37876c23..d82ac5a481b4 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi @@ -861,7 +861,7 @@ power-domain@RK3588_PD_NPU2 { }; }; /* These power domains are grouped by VD_GPU */ - power-domain@RK3588_PD_GPU { + pd_gpu: power-domain@RK3588_PD_GPU { reg =3D ; clocks =3D <&cru CLK_GPU>, <&cru CLK_GPU_COREGROUP>, diff --git a/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5.dtsi b/arch/arm= 64/boot/dts/rockchip/rk3588-coolpi-cm5.dtsi index fde8b228f2c7..cf9d75159ba6 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5.dtsi @@ -277,6 +277,10 @@ &pcie2x1l2 { status =3D "okay"; }; =20 +&pd_gpu { + domain-supply =3D <&vdd_gpu_s0>; +}; + &pinctrl { hym8563 { hym8563_int: hym8563-int { diff --git a/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588.dtsi b= /arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588.dtsi index e3a9598b99fc..1af0a30866f6 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588.dtsi @@ -256,6 +256,10 @@ &pcie2x1l2 { status =3D "okay"; }; =20 +&pd_gpu { + domain-supply =3D <&vdd_gpu_s0>; +}; + &pinctrl { gpio-leds { led_sys_pin: led-sys-pin { diff --git a/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts b/arch/arm64/bo= ot/dts/rockchip/rk3588-jaguar.dts index 31d2f8994f85..3cefaf830229 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts @@ -403,6 +403,10 @@ &pcie3x4 { status =3D "okay"; }; =20 +&pd_gpu { + domain-supply =3D <&vdd_gpu_s0>; +}; + &pinctrl { emmc { emmc_reset: emmc-reset { diff --git a/arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts b/arch/arm64/= boot/dts/rockchip/rk3588-ok3588-c.dts index c2a08bdf09e8..a9c1fed929fd 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts @@ -312,6 +312,10 @@ &pcie3x4 { status =3D "okay"; }; =20 +&pd_gpu { + domain-supply =3D <&vdd_gpu_s0>; +}; + &pinctrl { pcie2 { pcie2_0_rst: pcie2-0-rst { diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts b/arch/arm6= 4/boot/dts/rockchip/rk3588-rock-5-itx.dts index d0b922b8d67e..0eadf4fb4ba4 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts @@ -530,6 +530,10 @@ &pcie3x4 { status =3D "okay"; }; =20 +&pd_gpu { + domain-supply =3D <&vdd_gpu_s0>; +}; + &pinctrl { hym8563 { rtc_int: rtc-int { diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/b= oot/dts/rockchip/rk3588-rock-5b.dts index 8f7a59918db7..717504383d46 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts @@ -465,6 +465,10 @@ &pcie3x4 { status =3D "okay"; }; =20 +&pd_gpu { + domain-supply =3D <&vdd_gpu_s0>; +}; + &pinctrl { hdmirx { hdmirx_hpd: hdmirx-5v-detection { diff --git a/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi b/arch/arm64/bo= ot/dts/rockchip/rk3588-tiger.dtsi index 615094bb8ba3..1b5c4a7fd5c6 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi @@ -317,6 +317,10 @@ &pcie3x4 { reset-gpios =3D <&gpio3 RK_PB6 GPIO_ACTIVE_HIGH>; }; =20 +&pd_gpu { + domain-supply =3D <&vdd_gpu_s0>; +}; + &pinctrl { emmc { emmc_reset: emmc-reset { diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts b/arch/arm6= 4/boot/dts/rockchip/rk3588s-coolpi-4b.dts index 074c316a9a69..d938db0e2239 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts @@ -329,6 +329,10 @@ &pcie2x1l2 { status =3D "okay"; }; =20 +&pd_gpu { + domain-supply =3D <&vdd_gpu_s0>; +}; + &pinctrl { hym8563 { hym8563_int: hym8563-int { diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts b/arch/a= rm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts index dbddfc3bb464..d29d404417ee 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts @@ -233,6 +233,10 @@ hym8563: rtc@51 { }; }; =20 +&pd_gpu { + domain-supply =3D <&vdd_gpu_s0>; +}; + &pinctrl { vdd_sd { vdd_sd_en: vdd-sd-en { diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts b/arch/arm= 64/boot/dts/rockchip/rk3588s-orangepi-5.dts index feea6b20a6bf..ef3a721d1fc7 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts @@ -297,6 +297,10 @@ &pcie2x1l2 { status =3D "okay"; }; =20 +&pd_gpu { + domain-supply =3D <&vdd_gpu_s0>; +}; + &pinctrl { gpio-func { leds_gpio: leds-gpio { --=20 2.45.2