From nobody Fri Nov 29 15:33:04 2024 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 952124206D; Thu, 19 Sep 2024 08:31:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.248 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726734688; cv=none; b=Tn5aY8MBqwkK5CxInvYMVTp/rJcB910PakMbrwkbms7dz6dfiGQi8TYl4BeadKUMuEgThmYS7rmYcvKcILINBbI9jnFdUBCe3DM2Yb3/9RQaGPBoRFJKd3RP9KK6VakA3hCIVA5nS4bjKbtUELWLwiD2jMz2vj8Y/9sOkdpgr5Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726734688; c=relaxed/simple; bh=3fIs40RGLxrlBC62+0Irt8S7XAR3jTEsIaLomCTRzjM=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=EjZnrK10J+T5ho766E6klTphz66WaC0plhVV82eODP4kOAA/Qkkedlz2/TxW8hMpVH0BM5dQIs7hxkVC2tcyEoIn2Rr6u750htK2ZexvjWJrRcc7YlU38sMQX7DjyR7m2UYoMqnQ/xQrAlmPjh9zGRNumYTnZvAYdDp7qNf9rYs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=wV7EVFXP; arc=none smtp.client-ip=198.47.23.248 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="wV7EVFXP" Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 48J8VAx2038138; Thu, 19 Sep 2024 03:31:10 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1726734670; bh=jNfXfPExIzUjGNzDpXtLRBjmKO3m6/OLlLeRKB1p0wc=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=wV7EVFXPPnQegsooEN7ViuQj9merg3VEcmrP+gv044LZl5TtkmoXzG4MJ9FOhaC4t eVAfqGlD53I/1XMu0/ojC7v/QiFHNS81kEvrmt+FZoM0Wby4Mkwm5VwcYHIUFpEXJI EZNUM+gho7yoUI0bwqgfqZP5Fw08n6xK1SbXY4JY= Received: from DFLE104.ent.ti.com (dfle104.ent.ti.com [10.64.6.25]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTP id 48J8VAp7077504; Thu, 19 Sep 2024 03:31:10 -0500 Received: from DFLE115.ent.ti.com (10.64.6.36) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 19 Sep 2024 03:31:10 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 19 Sep 2024 03:31:10 -0500 Received: from lcpd911.dhcp.ti.com (lcpd911.dhcp.ti.com [172.24.227.226]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 48J8UrgW042798; Thu, 19 Sep 2024 03:31:07 -0500 From: Dhruva Gole To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Viresh Kumar , "Rafael J . Wysocki" CC: , , , , Dhruva Gole , Rob Herring , Krzysztof Kozlowski , Bryan Brattlof Subject: [PATCH V4 1/6] arm64: dts: ti: k3-am62a: add opp frequencies Date: Thu, 19 Sep 2024 13:58:05 +0530 Message-ID: <20240919082809.174589-2-d-gole@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240919082809.174589-1-d-gole@ti.com> References: <20240919082809.174589-1-d-gole@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" From: Bryan Brattlof One power management technique available to the Cortex-A53s is their ability to dynamically scale their frequency across the device's Operating Performance Points (OPP) The OPPs available for the Cortex-A53s on the AM62Ax can vary based on the silicon variant used. The SoC variant is encoded into the WKUP_MMR0_WKUP0_CTRL_MMR0_JTAG_USER_ID register which is used to limit to only OPP entries the variant supports. A table of all these variants can be found in it's data sheet[0] for the AM62Ax family. Add the OPP table into the SoC's fdti file along with the syscon node to describe the WKUP_MMR0_WKUP0_CTRL_MMR0_JTAG_USER_ID register to detect the SoC variant. [0] https://www.ti.com/lit/ds/symlink/am62a3.pdf Signed-off-by: Bryan Brattlof --- Link to comment on previous rev: https://lore.kernel.org/all/20240828131601.6sxvnwpcsb36tz4m@eloquent/ Nishanth, this series has been tested to work on all platforms [1]. I hope that with the revision picking from socinfo and the efuse_offsets being picked from DT (as they should) there are no longer any major outstanding concerns on this series? [1] https://gist.github.com/DhruvaG2000/63f5e28636d52787488f776e5bf39498 --- arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi | 5 ++ arch/arm64/boot/dts/ti/k3-am62a7.dtsi | 51 +++++++++++++++++++++ 2 files changed, 56 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi b/arch/arm64/boot/= dts/ti/k3-am62a-wakeup.dtsi index f5ac101a04df..0b1dd5390cd3 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi @@ -17,6 +17,11 @@ chipid: chipid@14 { reg =3D <0x14 0x4>; }; =20 + opp_efuse_table: syscon@18 { + compatible =3D "ti,am62-opp-efuse-table", "syscon"; + reg =3D <0x18 0x4>; + }; + cpsw_mac_syscon: ethernet-mac-syscon@200 { compatible =3D "ti,am62p-cpsw-mac-efuse", "syscon"; reg =3D <0x200 0x8>; diff --git a/arch/arm64/boot/dts/ti/k3-am62a7.dtsi b/arch/arm64/boot/dts/ti= /k3-am62a7.dtsi index f86a23404e6d..6c99221beb6b 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a7.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a7.dtsi @@ -48,6 +48,8 @@ cpu0: cpu@0 { d-cache-line-size =3D <64>; d-cache-sets =3D <128>; next-level-cache =3D <&L2_0>; + operating-points-v2 =3D <&a53_opp_table>; + clocks =3D <&k3_clks 135 0>; }; =20 cpu1: cpu@1 { @@ -62,6 +64,8 @@ cpu1: cpu@1 { d-cache-line-size =3D <64>; d-cache-sets =3D <128>; next-level-cache =3D <&L2_0>; + operating-points-v2 =3D <&a53_opp_table>; + clocks =3D <&k3_clks 136 0>; }; =20 cpu2: cpu@2 { @@ -76,6 +80,8 @@ cpu2: cpu@2 { d-cache-line-size =3D <64>; d-cache-sets =3D <128>; next-level-cache =3D <&L2_0>; + operating-points-v2 =3D <&a53_opp_table>; + clocks =3D <&k3_clks 137 0>; }; =20 cpu3: cpu@3 { @@ -90,6 +96,51 @@ cpu3: cpu@3 { d-cache-line-size =3D <64>; d-cache-sets =3D <128>; next-level-cache =3D <&L2_0>; + operating-points-v2 =3D <&a53_opp_table>; + clocks =3D <&k3_clks 138 0>; + }; + }; + + a53_opp_table: opp-table { + compatible =3D "operating-points-v2-ti-cpu"; + opp-shared; + syscon =3D <&opp_efuse_table>; + + opp-200000000 { + opp-hz =3D /bits/ 64 <200000000>; + opp-supported-hw =3D <0x01 0x0007>; + clock-latency-ns =3D <6000000>; + }; + + opp-400000000 { + opp-hz =3D /bits/ 64 <400000000>; + opp-supported-hw =3D <0x01 0x0007>; + clock-latency-ns =3D <6000000>; + }; + + opp-600000000 { + opp-hz =3D /bits/ 64 <600000000>; + opp-supported-hw =3D <0x01 0x0007>; + clock-latency-ns =3D <6000000>; + }; + + opp-800000000 { + opp-hz =3D /bits/ 64 <800000000>; + opp-supported-hw =3D <0x01 0x0007>; + clock-latency-ns =3D <6000000>; + }; + + opp-1000000000 { + opp-hz =3D /bits/ 64 <1000000000>; + opp-supported-hw =3D <0x01 0x0006>; + clock-latency-ns =3D <6000000>; + }; + + opp-1250000000 { + opp-hz =3D /bits/ 64 <1250000000>; + opp-supported-hw =3D <0x01 0x0004>; + clock-latency-ns =3D <6000000>; + opp-suspend; }; }; =20 --=20 2.34.1