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[80.117.99.70]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42e75468413sm16889465e9.45.2024.09.19.02.21.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Sep 2024 02:21:42 -0700 (PDT) From: Angelo Dureghello X-Google-Original-From: Angelo Dureghello Date: Thu, 19 Sep 2024 11:20:02 +0200 Subject: [PATCH v3 06/10] iio: backend: adi-axi-dac: extend features Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240919-wip-bl-ad3552r-axi-v0-iio-testing-v3-6-a17b9b3d05d9@baylibre.com> References: <20240919-wip-bl-ad3552r-axi-v0-iio-testing-v3-0-a17b9b3d05d9@baylibre.com> In-Reply-To: <20240919-wip-bl-ad3552r-axi-v0-iio-testing-v3-0-a17b9b3d05d9@baylibre.com> To: Lars-Peter Clausen , Michael Hennerich , Nuno Sa , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Olivier Moysan Cc: linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, dlechner@baylibre.com, Angelo Dureghello X-Mailer: b4 0.14.1 From: Angelo Dureghello Extend AXI-DAC backend with new features required to interface to the ad3552r DAC. Mainly, a new compatible string is added to support the ad3552r-axi DAC IP, very similar to the generic DAC IP but with some customizations to work with the ad3552r. Then, a serie of generic functions has been added to match with ad3552r needs. Function names has been kept generic as much as possible, to allow re-utilization from other frontend drivers. Signed-off-by: Angelo Dureghello --- drivers/iio/dac/adi-axi-dac.c | 274 ++++++++++++++++++++++++++++++++++++++= ++-- 1 file changed, 265 insertions(+), 9 deletions(-) diff --git a/drivers/iio/dac/adi-axi-dac.c b/drivers/iio/dac/adi-axi-dac.c index b8b4171b8043..3ca3a14c575b 100644 --- a/drivers/iio/dac/adi-axi-dac.c +++ b/drivers/iio/dac/adi-axi-dac.c @@ -44,11 +44,34 @@ #define AXI_DAC_RSTN_MMCM_RSTN BIT(1) #define AXI_DAC_RSTN_RSTN BIT(0) #define AXI_DAC_REG_CNTRL_1 0x0044 +#define AXI_DAC_EXT_SYNC_ARM BIT(1) +#define AXI_DAC_EXT_SYNC_DISARM BIT(2) #define AXI_DAC_SYNC BIT(0) #define AXI_DAC_REG_CNTRL_2 0x0048 +#define AXI_DAC_SDR_DDR_N BIT(16) +#define AXI_DAC_SYMB_8B BIT(14) #define ADI_DAC_R1_MODE BIT(5) +#define AXI_DAC_UNSIGNED_DATA BIT(4) +#define AXI_DAC_REG_STATUS_1 0x54 +#define AXI_DAC_REG_STATUS_2 0x58 #define AXI_DAC_DRP_STATUS 0x0074 #define AXI_DAC_DRP_LOCKED BIT(17) +#define AXI_DAC_CNTRL_DATA_RD 0x0080 +#define AXI_DAC_DATA_RD_8 GENMASK(7, 0) +#define AXI_DAC_DATA_RD_16 GENMASK(15, 0) +#define AXI_DAC_CNTRL_DATA_WR 0x0084 +#define AXI_DAC_DATA_WR_8 GENMASK(23, 16) +#define AXI_DAC_DATA_WR_16 GENMASK(23, 8) +#define AXI_DAC_UI_STATUS 0x0088 +#define AXI_DAC_BUSY BIT(4) +#define AXI_DAC_REG_CUSTOM_CTRL 0x008C +#define AXI_DAC_ADDRESS GENMASK(31, 24) +#define AXI_DAC_SYNCED_TRANSFER BIT(2) +#define AXI_DAC_STREAM BIT(1) +#define AXI_DAC_TRANSFER_DATA BIT(0) + +#define AXI_DAC_STREAM_ENABLE (AXI_DAC_TRANSFER_DATA | AXI_DAC_STREAM) + /* DAC Channel controls */ #define AXI_DAC_REG_CHAN_CNTRL_1(c) (0x0400 + (c) * 0x40) #define AXI_DAC_REG_CHAN_CNTRL_3(c) (0x0408 + (c) * 0x40) @@ -62,11 +85,25 @@ #define AXI_DAC_REG_CHAN_CNTRL_7(c) (0x0418 + (c) * 0x40) #define AXI_DAC_DATA_SEL GENMASK(3, 0) =20 +#define AXI_DAC_RD_ADDR(x) (BIT(7) | (x)) + /* 360 degrees in rad */ #define AXI_DAC_2_PI_MEGA 6283190 + enum { AXI_DAC_DATA_INTERNAL_TONE, AXI_DAC_DATA_DMA =3D 2, + AXI_DAC_DATA_INTERNAL_RAMP_16BIT =3D 11, +}; + +enum { + AXI_DAC_BUS_TYPE_NONE, + AXI_DAC_BUS_TYPE_DDR_QSPI, +}; + +struct axi_dac_info { + unsigned int version; + int bus_type; }; =20 struct axi_dac_state { @@ -77,6 +114,7 @@ struct axi_dac_state { * data/variables. */ struct mutex lock; + const struct axi_dac_info *info; u64 dac_clk; u32 reg_config; bool int_tone; @@ -461,6 +499,11 @@ static int axi_dac_data_source_set(struct iio_backend = *back, unsigned int chan, return regmap_update_bits(st->regmap, AXI_DAC_REG_CHAN_CNTRL_7(chan), AXI_DAC_DATA_SEL, AXI_DAC_DATA_DMA); + case IIO_BACKEND_INTERNAL_RAMP_16BIT: + return regmap_update_bits(st->regmap, + AXI_DAC_REG_CHAN_CNTRL_7(chan), + AXI_DAC_DATA_SEL, + AXI_DAC_DATA_INTERNAL_RAMP_16BIT); default: return -EINVAL; } @@ -518,9 +561,206 @@ static int axi_dac_reg_access(struct iio_backend *bac= k, unsigned int reg, return regmap_write(st->regmap, reg, writeval); } =20 +static int axi_dac_ext_sync_enable(struct iio_backend *back) +{ + struct axi_dac_state *st =3D iio_backend_get_priv(back); + + return regmap_set_bits(st->regmap, AXI_DAC_REG_CNTRL_1, + AXI_DAC_EXT_SYNC_ARM); +} + +static int axi_dac_ext_sync_disable(struct iio_backend *back) +{ + struct axi_dac_state *st =3D iio_backend_get_priv(back); + + return regmap_clear_bits(st->regmap, AXI_DAC_REG_CNTRL_1, + AXI_DAC_EXT_SYNC_DISARM); +} + +static int axi_dac_ddr_enable(struct iio_backend *back) +{ + struct axi_dac_state *st =3D iio_backend_get_priv(back); + + return regmap_clear_bits(st->regmap, AXI_DAC_REG_CNTRL_2, + AXI_DAC_SDR_DDR_N); +} + +static int axi_dac_ddr_disable(struct iio_backend *back) +{ + struct axi_dac_state *st =3D iio_backend_get_priv(back); + + return regmap_set_bits(st->regmap, AXI_DAC_REG_CNTRL_2, + AXI_DAC_SDR_DDR_N); +} + +static int axi_dac_buffer_enable(struct iio_backend *back) +{ + struct axi_dac_state *st =3D iio_backend_get_priv(back); + + return regmap_set_bits(st->regmap, AXI_DAC_REG_CUSTOM_CTRL, + AXI_DAC_STREAM_ENABLE); +} + +static int axi_dac_buffer_disable(struct iio_backend *back) +{ + struct axi_dac_state *st =3D iio_backend_get_priv(back); + + return regmap_clear_bits(st->regmap, AXI_DAC_REG_CUSTOM_CTRL, + AXI_DAC_STREAM_ENABLE); +} + +static int axi_dac_data_transfer_addr(struct iio_backend *back, u32 addres= s) +{ + struct axi_dac_state *st =3D iio_backend_get_priv(back); + + /* + * Sample register address, when the DAC is configured, or stream + * start address when the FSM is in stream state. + */ + return regmap_update_bits(st->regmap, AXI_DAC_REG_CUSTOM_CTRL, + AXI_DAC_ADDRESS, + FIELD_PREP(AXI_DAC_ADDRESS, address)); +} + +static int axi_dac_data_format_set(struct iio_backend *back, unsigned int = ch, + const struct iio_backend_data_fmt *data) +{ + struct axi_dac_state *st =3D iio_backend_get_priv(back); + + if (data->type =3D=3D IIO_BACKEND_DATA_UNSIGNED) + return regmap_clear_bits(st->regmap, AXI_DAC_REG_CNTRL_2, + AXI_DAC_UNSIGNED_DATA); + + return -EINVAL; +} + +static int axi_dac_read_raw(struct iio_backend *back, + struct iio_chan_spec const *chan, + int *val, int *val2, long mask) +{ + struct axi_dac_state *st =3D iio_backend_get_priv(back); + int err; + + switch (mask) { + case IIO_CHAN_INFO_FREQUENCY: { + int clk_in, reg; + + /* + * As from AXI IP documentation, + * returning the SCLK depending on the stream mode. + */ + clk_in =3D clk_get_rate(clk_get(st->dev, 0)); + + err =3D regmap_read(st->regmap, AXI_DAC_REG_CUSTOM_CTRL, ®); + if (err) + return err; + + if (reg & AXI_DAC_STREAM) + *val =3D clk_in / 2; + else + *val =3D clk_in / 8; + + return IIO_VAL_INT; + } + default: + return -EINVAL; + } +} + +static int axi_dac_bus_reg_write(struct iio_backend *back, u32 reg, + unsigned int val, size_t data_size) +{ + struct axi_dac_state *st =3D iio_backend_get_priv(back); + + switch (st->info->bus_type) { + case AXI_DAC_BUS_TYPE_DDR_QSPI: { + int ret; + u32 ival; + + if (data_size =3D=3D 2) + ival =3D FIELD_PREP(AXI_DAC_DATA_WR_16, val); + else + ival =3D FIELD_PREP(AXI_DAC_DATA_WR_8, val); + + ret =3D regmap_write(st->regmap, AXI_DAC_CNTRL_DATA_WR, ival); + if (ret) + return ret; + + /* + * Both REG_CNTRL_2 and AXI_DAC_CNTRL_DATA_WR need to know + * the data size. So keeping data size control here only, + * since data size is mandatory for the current transfer. + * DDR state handled separately by specific backend calls, + * generally all raw register writes are SDR. + */ + if (data_size =3D=3D 1) + ret =3D regmap_set_bits(st->regmap, AXI_DAC_REG_CNTRL_2, + AXI_DAC_SYMB_8B); + else + ret =3D regmap_clear_bits(st->regmap, AXI_DAC_REG_CNTRL_2, + AXI_DAC_SYMB_8B); + if (ret) + return ret; + + ret =3D regmap_update_bits(st->regmap, AXI_DAC_REG_CUSTOM_CTRL, + AXI_DAC_ADDRESS, + FIELD_PREP(AXI_DAC_ADDRESS, reg)); + if (ret) + return ret; + + ret =3D regmap_update_bits(st->regmap, AXI_DAC_REG_CUSTOM_CTRL, + AXI_DAC_TRANSFER_DATA, + AXI_DAC_TRANSFER_DATA); + if (ret) + return ret; + + ret =3D regmap_read_poll_timeout(st->regmap, + AXI_DAC_REG_CUSTOM_CTRL, ival, + ival & AXI_DAC_TRANSFER_DATA, + 10, 100 * KILO); + if (ret) + return ret; + + return regmap_clear_bits(st->regmap, AXI_DAC_REG_CUSTOM_CTRL, + AXI_DAC_TRANSFER_DATA); + } + default: + return -EOPNOTSUPP; + } +} + +static int axi_dac_bus_reg_read(struct iio_backend *back, u32 reg, + unsigned int *val, size_t data_size) +{ + struct axi_dac_state *st =3D iio_backend_get_priv(back); + + switch (st->info->bus_type) { + case AXI_DAC_BUS_TYPE_DDR_QSPI: { + int ret; + u32 bval; + + ret =3D axi_dac_bus_reg_write(back, AXI_DAC_RD_ADDR(reg), 0, + data_size); + if (ret) + return ret; + + ret =3D regmap_read_poll_timeout(st->regmap, AXI_DAC_UI_STATUS, + bval, bval !=3D AXI_DAC_BUSY, + 10, 100); + if (ret) + return ret; + + return regmap_read(st->regmap, AXI_DAC_CNTRL_DATA_RD, val); + } + default: + return -EOPNOTSUPP; + } +} + static const struct iio_backend_ops axi_dac_generic_ops =3D { .enable =3D axi_dac_enable, .disable =3D axi_dac_disable, + .read_raw =3D axi_dac_read_raw, .request_buffer =3D axi_dac_request_buffer, .free_buffer =3D axi_dac_free_buffer, .extend_chan_spec =3D axi_dac_extend_chan, @@ -528,6 +768,14 @@ static const struct iio_backend_ops axi_dac_generic_op= s =3D { .ext_info_get =3D axi_dac_ext_info_get, .data_source_set =3D axi_dac_data_source_set, .set_sample_rate =3D axi_dac_set_sample_rate, + .ext_sync_enable =3D axi_dac_ext_sync_enable, + .ext_sync_disable =3D axi_dac_ext_sync_disable, + .ddr_enable =3D axi_dac_ddr_enable, + .ddr_disable =3D axi_dac_ddr_disable, + .buffer_enable =3D axi_dac_buffer_enable, + .buffer_disable =3D axi_dac_buffer_disable, + .data_format_set =3D axi_dac_data_format_set, + .data_transfer_addr =3D axi_dac_data_transfer_addr, .debugfs_reg_access =3D iio_backend_debugfs_ptr(axi_dac_reg_access), }; =20 @@ -545,7 +793,6 @@ static const struct regmap_config axi_dac_regmap_config= =3D { =20 static int axi_dac_probe(struct platform_device *pdev) { - const unsigned int *expected_ver; struct axi_dac_state *st; void __iomem *base; unsigned int ver; @@ -556,8 +803,8 @@ static int axi_dac_probe(struct platform_device *pdev) if (!st) return -ENOMEM; =20 - expected_ver =3D device_get_match_data(&pdev->dev); - if (!expected_ver) + st->info =3D device_get_match_data(&pdev->dev); + if (!st->info) return -ENODEV; =20 clk =3D devm_clk_get_enabled(&pdev->dev, NULL); @@ -588,12 +835,13 @@ static int axi_dac_probe(struct platform_device *pdev) if (ret) return ret; =20 - if (ADI_AXI_PCORE_VER_MAJOR(ver) !=3D ADI_AXI_PCORE_VER_MAJOR(*expected_v= er)) { + if (ADI_AXI_PCORE_VER_MAJOR(ver) !=3D + ADI_AXI_PCORE_VER_MAJOR(st->info->version)) { dev_err(&pdev->dev, "Major version mismatch. Expected %d.%.2d.%c, Reported %d.%.2d.%c\n", - ADI_AXI_PCORE_VER_MAJOR(*expected_ver), - ADI_AXI_PCORE_VER_MINOR(*expected_ver), - ADI_AXI_PCORE_VER_PATCH(*expected_ver), + ADI_AXI_PCORE_VER_MAJOR(st->info->version), + ADI_AXI_PCORE_VER_MINOR(st->info->version), + ADI_AXI_PCORE_VER_PATCH(st->info->version), ADI_AXI_PCORE_VER_MAJOR(ver), ADI_AXI_PCORE_VER_MINOR(ver), ADI_AXI_PCORE_VER_PATCH(ver)); @@ -631,10 +879,18 @@ static int axi_dac_probe(struct platform_device *pdev) return 0; } =20 -static unsigned int axi_dac_9_1_b_info =3D ADI_AXI_PCORE_VER(9, 1, 'b'); +static const struct axi_dac_info dac_generic =3D { + .version =3D ADI_AXI_PCORE_VER(9, 1, 'b'), +}; + +static const struct axi_dac_info dac_ad3552r =3D { + .version =3D ADI_AXI_PCORE_VER(9, 1, 'b'), + .bus_type =3D AXI_DAC_BUS_TYPE_DDR_QSPI, +}; =20 static const struct of_device_id axi_dac_of_match[] =3D { - { .compatible =3D "adi,axi-dac-9.1.b", .data =3D &axi_dac_9_1_b_info }, + { .compatible =3D "adi,axi-dac-9.1.b", .data =3D &dac_generic }, + { .compatible =3D "adi,axi-ad3552r", .data =3D &dac_ad3552r }, {} }; MODULE_DEVICE_TABLE(of, axi_dac_of_match); --=20 2.45.0.rc1