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[80.117.99.70]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42e75468413sm16889465e9.45.2024.09.19.02.21.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Sep 2024 02:21:36 -0700 (PDT) From: Angelo Dureghello X-Google-Original-From: Angelo Dureghello Date: Thu, 19 Sep 2024 11:19:58 +0200 Subject: [PATCH v3 02/10] dt-bindings: iio: dac: axi-dac: add ad3552r axi variant Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240919-wip-bl-ad3552r-axi-v0-iio-testing-v3-2-a17b9b3d05d9@baylibre.com> References: <20240919-wip-bl-ad3552r-axi-v0-iio-testing-v3-0-a17b9b3d05d9@baylibre.com> In-Reply-To: <20240919-wip-bl-ad3552r-axi-v0-iio-testing-v3-0-a17b9b3d05d9@baylibre.com> To: Lars-Peter Clausen , Michael Hennerich , Nuno Sa , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Olivier Moysan Cc: linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, dlechner@baylibre.com, Angelo Dureghello X-Mailer: b4 0.14.1 From: Angelo Dureghello Add a new compatible and related bindigns for the fpga-based "ad3552r" AXI IP core, a variant of the generic AXI DAC IP. The AXI "ad3552r" IP is a very similar HDL (fpga) variant of the generic AXI "DAC" IP, intended to control ad3552r and similar chips, mainly to reach high speed transfer rates using an additional QSPI DDR interface. The ad3552r device is defined as a child of the AXI DAC, that in this case is acting as an SPI controller. Signed-off-by: Angelo Dureghello --- .../devicetree/bindings/iio/dac/adi,axi-dac.yaml | 40 ++++++++++++++++++= ++-- 1 file changed, 37 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/iio/dac/adi,axi-dac.yaml b/D= ocumentation/devicetree/bindings/iio/dac/adi,axi-dac.yaml index a55e9bfc66d7..6cf0c2cb84e7 100644 --- a/Documentation/devicetree/bindings/iio/dac/adi,axi-dac.yaml +++ b/Documentation/devicetree/bindings/iio/dac/adi,axi-dac.yaml @@ -19,11 +19,13 @@ description: | memory via DMA into the DAC. =20 https://wiki.analog.com/resources/fpga/docs/axi_dac_ip + https://analogdevicesinc.github.io/hdl/library/axi_ad3552r/index.html =20 properties: compatible: enum: - adi,axi-dac-9.1.b + - adi,axi-ad3552r =20 reg: maxItems: 1 @@ -41,22 +43,54 @@ properties: '#io-backend-cells': const: 0 =20 + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + required: - compatible - dmas - reg - clocks =20 +patternProperties: + "^.*@([0-9])$": + type: object + additionalProperties: true + properties: + io-backends: + description: | + AXI backend reference + required: + - io-backends + additionalProperties: false =20 examples: - | dac@44a00000 { - compatible =3D "adi,axi-dac-9.1.b"; - reg =3D <0x44a00000 0x10000>; - dmas =3D <&tx_dma 0>; + compatible =3D "adi,axi-dac-9.1.b"; + reg =3D <0x44a00000 0x10000>; + dmas =3D <&tx_dma 0>; + dma-names =3D "tx"; + #io-backend-cells =3D <0>; + clocks =3D <&axi_clk>; + }; + + - | + axi_dac: spi@44a70000 { + compatible =3D "adi,axi-ad3552r"; + reg =3D <0x44a70000 0x1000>; + dmas =3D <&dac_tx_dma 0>; dma-names =3D "tx"; #io-backend-cells =3D <0>; clocks =3D <&axi_clk>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + /* DAC devices */ }; ... --=20 2.45.0.rc1