From nobody Fri Nov 29 16:31:39 2024 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0F559194C76; Thu, 19 Sep 2024 07:32:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726731158; cv=none; b=PmDNLVJ8po/B60DIO+3YEgoATEl/9enVDybVLICjkuTDonPs0bEOFhDcjshoBr0c/tvJ71uBpUDnNoa5HCaVLC62U477YA6A3GVKG58gHRq3kUm8SguvBDO/cMryXDFM2HyqF5akLt8mk7DWXMtLb0trHC0EGGTMm6DwiZtsNQs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726731158; c=relaxed/simple; bh=LKqn8Hmg1YOn5awyiAQQP/+3Cl5AuAIc5g1pOeRj1Po=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=FbAY93XFWEdhV00meeFD/try6+1c/eN5d6s5PL8riUNdQ32ul9F3WYtGn4u7ALZQQKrBQ1PVW84QT+Sm7tPN9HgAWrUtWF2hKT/1yKo3B6NfevKJTQ+8qwpPxgwnpJ4JIOJF8LQaeZ6nMFbGAyl91EzyHrP3bSMbVbMzezPFwFk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=gMiDrjuN; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="gMiDrjuN" Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 48INkZLo024086; Thu, 19 Sep 2024 07:32:34 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= TZV6OCcT9GI5GJWDhwoTLVKsbNxQr42iBUprvMI9q0w=; b=gMiDrjuNpOqe9HnT QtEcidxG0YPBLcgMd0/LV6+kBw9niWfDEeRaB4dnBRClxjHtEol4u34/oKJjpRSz G1z5jNuT8frB505u9gpSnTKKQ4uTiFlNxz2DohV+2vl4SBAY4RgAkJCZ93tCPlEA TF+oAdFFfOXgcBaFy0Rkg+1gZQOaakcuZhKe/u3l3a9LL8NIeVd7uLe3YxAM44rY cO5oB9hl4xauKEuPYJmofPPodkq8wrgiSVgNXFeE8sQgkm+ylr15QaON9ZQ4A4qL pOgj8bGCDqspvljNF8Aj7wz2OA3Zya87TqCQTi/I/NMkCY61rXA9ZPIIoNhOGcB5 cPmfCA== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 41n4gecckt-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 19 Sep 2024 07:32:33 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 48J7WWPj012033 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 19 Sep 2024 07:32:33 GMT Received: from hu-tdas-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 19 Sep 2024 00:32:28 -0700 From: Taniya Das Date: Thu, 19 Sep 2024 13:02:16 +0530 Subject: [PATCH 2/4] clk: qcom: rpmhcc: Add support for QCS615 Clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20240919-qcs615-clock-driver-v1-2-51c0cc92e3a2@quicinc.com> References: <20240919-qcs615-clock-driver-v1-0-51c0cc92e3a2@quicinc.com> In-Reply-To: <20240919-qcs615-clock-driver-v1-0-51c0cc92e3a2@quicinc.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ajit Pandey , Imran Shaik , Jagadeesh Kona CC: , , , , Taniya Das X-Mailer: b4 0.14-dev-f7c49 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: sMv2dKQD2GiF9dvtVQyYxj285AYhScWm X-Proofpoint-ORIG-GUID: sMv2dKQD2GiF9dvtVQyYxj285AYhScWm X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 mlxlogscore=943 impostorscore=0 bulkscore=0 clxscore=1015 lowpriorityscore=0 adultscore=0 phishscore=0 suspectscore=0 priorityscore=1501 mlxscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2408220000 definitions=main-2409190046 Add the RPMHCC clocks required for QCS615 SoC. Signed-off-by: Taniya Das --- drivers/clk/qcom/clk-rpmh.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c index 4acde937114a..96600aba9bf2 100644 --- a/drivers/clk/qcom/clk-rpmh.c +++ b/drivers/clk/qcom/clk-rpmh.c @@ -795,6 +795,24 @@ static const struct clk_rpmh_desc clk_rpmh_x1e80100 = =3D { .num_clks =3D ARRAY_SIZE(x1e80100_rpmh_clocks), }; =20 +static struct clk_hw *qcs615_rpmh_clocks[] =3D { + [RPMH_CXO_CLK] =3D &clk_rpmh_bi_tcxo_div2.hw, + [RPMH_CXO_CLK_A] =3D &clk_rpmh_bi_tcxo_div2_ao.hw, + [RPMH_LN_BB_CLK2] =3D &clk_rpmh_ln_bb_clk2_a2.hw, + [RPMH_LN_BB_CLK2_A] =3D &clk_rpmh_ln_bb_clk2_a2_ao.hw, + [RPMH_LN_BB_CLK3] =3D &clk_rpmh_ln_bb_clk3_a2.hw, + [RPMH_LN_BB_CLK3_A] =3D &clk_rpmh_ln_bb_clk3_a2_ao.hw, + [RPMH_RF_CLK1] =3D &clk_rpmh_rf_clk1_a.hw, + [RPMH_RF_CLK1_A] =3D &clk_rpmh_rf_clk1_a_ao.hw, + [RPMH_RF_CLK2] =3D &clk_rpmh_rf_clk2_a.hw, + [RPMH_RF_CLK2_A] =3D &clk_rpmh_rf_clk2_a_ao.hw, +}; + +static const struct clk_rpmh_desc clk_rpmh_qcs615 =3D { + .clks =3D qcs615_rpmh_clocks, + .num_clks =3D ARRAY_SIZE(qcs615_rpmh_clocks), +}; + static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec, void *data) { @@ -879,6 +897,7 @@ static int clk_rpmh_probe(struct platform_device *pdev) =20 static const struct of_device_id clk_rpmh_match_table[] =3D { { .compatible =3D "qcom,qdu1000-rpmh-clk", .data =3D &clk_rpmh_qdu1000}, + { .compatible =3D "qcom,qcs615-rpmh-clk", .data =3D &clk_rpmh_qcs615}, { .compatible =3D "qcom,sa8775p-rpmh-clk", .data =3D &clk_rpmh_sa8775p}, { .compatible =3D "qcom,sc7180-rpmh-clk", .data =3D &clk_rpmh_sc7180}, { .compatible =3D "qcom,sc8180x-rpmh-clk", .data =3D &clk_rpmh_sc8180x}, --=20 2.45.2