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Wed, 18 Sep 2024 14:59:54 -0700 From: Besar Wicaksono To: , , , , CC: , , , , , , , , "Besar Wicaksono" Subject: [PATCH 1/3] perf: arm_cspmu: nvidia: remove unsupported SCF events Date: Wed, 18 Sep 2024 21:58:44 +0000 Message-ID: <20240918215846.1424282-2-bwicaksono@nvidia.com> X-Mailer: git-send-email 2.46.1 In-Reply-To: <20240918215846.1424282-1-bwicaksono@nvidia.com> References: <20240918215846.1424282-1-bwicaksono@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF000044A2:EE_|CY8PR12MB7491:EE_ X-MS-Office365-Filtering-Correlation-Id: 2b24cc76-4e7d-4b35-a1be-08dcd82d4178 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?9D4y8FoQMzU1zcDWJxFm513J5e4P2txySD9R6QFSCoHi9G1XFS+g49tKgLBd?= =?us-ascii?Q?/IJ0gqS/TMMcWVx6bx4fpSuRg+6CDapmmSVpKqug6vXfX2PGdv/TovcXciHN?= =?us-ascii?Q?VguVhq7ZbBu/3g5EA4hAqAvrs0m6P+IMJCTeqcxSM3zWrGw3E6oqWxEJWYgu?= =?us-ascii?Q?jAVXLJ3LK+m9rIdlQtXlRGGavaR5Jq1f6G508rowwxq9OCBI7UP1CrjlO7WW?= =?us-ascii?Q?VFI17lYjrzFNLbyhMBEMpJx2nKG9cUGt8S82ia7h6F5l+LxWzy5Wl361ueR6?= =?us-ascii?Q?3ta90D4Km7zBWDuepA8SrBz+QblqRa5EhI/VVH07VHrhredtfHm+2mp4PSVB?= =?us-ascii?Q?JWrP3SbHEEABaJ9xvuoZHtTx8zdOpoDSinOqwppSxmYiNcDV4LruXgW+I9db?= =?us-ascii?Q?CvyzESlKRktiWo0EPnQMNf5lUiFehVYPAJzChnCMWV2qCMCV0BXHn6IXoyjL?= =?us-ascii?Q?PMYuxtfsUNENftJ9G91ihUrWaOw7wiWAgQCTIqGfJ6CqJ4fgb5k4g8gQHETo?= =?us-ascii?Q?+KUF9lgjS8IoE89KCjiGpNCr3g4r1QTAFSmHd5vjcnOMkExfWxXHgcPcuCL9?= =?us-ascii?Q?CdJYDRK7GDfL5ryQ7L11xGwIk+8KjQrZdvKQoRGIUogDGH/tqNCB+2wdutlb?= =?us-ascii?Q?GjxfmZkvFyCMdnmrR+yN09dlaedAD0x99r2hNM4ZpOy2QnmMRvH3NEHRESrd?= =?us-ascii?Q?+el1uyrRHI6OHXrq0B36LfuctF8EgqQmTo59w73X+q+zHjBRMtJJ/BVbcJaL?= =?us-ascii?Q?vhPCZLDbLicPRVfWm2UEhEdNxxwPBZtdbgMmpLZUXdZ5PNIg1rshW0pHwELH?= =?us-ascii?Q?jT2BTodobvXFWVFZ7oqRrDVmWqvRN2ylTpZ9HWtuwFOQCBi2fk6XM5WKtcPw?= =?us-ascii?Q?WSdiS9QMV9YDKrLjeNGC8+P3lBC0/lBFqagcqhREGqcgZITGafIQXCxRJnzk?= =?us-ascii?Q?Bf88VHF3u+mBgdqMTHQr6U3vNC7ncYgePC1Ey+JdDqkUei1PXM7aFwUHtl2u?= =?us-ascii?Q?enrEX93yauJfzyETewgmenVtOEFR7E/I4VfN2jFHgvgU0KAbTd/TLUWjgltw?= =?us-ascii?Q?wLzX7MPcUDpyxFTDi+M4xoUe60HkwJyXY1f4Jgkdb25kdjGmUmLska/YD+UO?= =?us-ascii?Q?INGL9mOv5UCyMhhzCWI/1tCaA+K3ET8V8wou6G7gpDAsHLGNgBmjgVWEhp0c?= =?us-ascii?Q?o6Tc/fUExF7ijMq51uxvPX1zwia0/XBXh0ci0SVvi7MhJ182Y7Q1g7VfJ/2m?= =?us-ascii?Q?twZ2w4cyBK4m1SmS0lPImD3B8H5gvu8RIxjTv8lmasqIV+ADwicaRg33ha5O?= =?us-ascii?Q?DroNaLXO8mwOicgFYOSz4Ho+RCxtxk5G91RdpgWlKLe59fExBFvZvp6RBtlF?= =?us-ascii?Q?XWiIxT3QN3cyNFGbLiSOy8aWCkWB?= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(1800799024)(36860700013)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Sep 2024 22:00:06.1445 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2b24cc76-4e7d-4b35-a1be-08dcd82d4178 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000044A2.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7491 Content-Type: text/plain; charset="utf-8" Remove unsupported events under SCF PMU. Signed-off-by: Besar Wicaksono --- drivers/perf/arm_cspmu/nvidia_cspmu.c | 64 --------------------------- 1 file changed, 64 deletions(-) diff --git a/drivers/perf/arm_cspmu/nvidia_cspmu.c b/drivers/perf/arm_cspmu= /nvidia_cspmu.c index d0ef611240aa..ea2d44adfa7c 100644 --- a/drivers/perf/arm_cspmu/nvidia_cspmu.c +++ b/drivers/perf/arm_cspmu/nvidia_cspmu.c @@ -54,65 +54,24 @@ static struct attribute *scf_pmu_event_attrs[] =3D { ARM_CSPMU_EVENT_ATTR(scf_cache_wb, 0xF3), =20 NV_CSPMU_EVENT_ATTR_4(socket, rd_data, 0x101), - NV_CSPMU_EVENT_ATTR_4(socket, dl_rsp, 0x105), NV_CSPMU_EVENT_ATTR_4(socket, wb_data, 0x109), - NV_CSPMU_EVENT_ATTR_4(socket, ev_rsp, 0x10d), - NV_CSPMU_EVENT_ATTR_4(socket, prb_data, 0x111), =20 NV_CSPMU_EVENT_ATTR_4(socket, rd_outstanding, 0x115), - NV_CSPMU_EVENT_ATTR_4(socket, dl_outstanding, 0x119), - NV_CSPMU_EVENT_ATTR_4(socket, wb_outstanding, 0x11d), - NV_CSPMU_EVENT_ATTR_4(socket, wr_outstanding, 0x121), - NV_CSPMU_EVENT_ATTR_4(socket, ev_outstanding, 0x125), - NV_CSPMU_EVENT_ATTR_4(socket, prb_outstanding, 0x129), =20 NV_CSPMU_EVENT_ATTR_4(socket, rd_access, 0x12d), - NV_CSPMU_EVENT_ATTR_4(socket, dl_access, 0x131), NV_CSPMU_EVENT_ATTR_4(socket, wb_access, 0x135), NV_CSPMU_EVENT_ATTR_4(socket, wr_access, 0x139), - NV_CSPMU_EVENT_ATTR_4(socket, ev_access, 0x13d), - NV_CSPMU_EVENT_ATTR_4(socket, prb_access, 0x141), - - NV_CSPMU_EVENT_ATTR_4(ocu, gmem_rd_data, 0x145), - NV_CSPMU_EVENT_ATTR_4(ocu, gmem_rd_access, 0x149), - NV_CSPMU_EVENT_ATTR_4(ocu, gmem_wb_access, 0x14d), - NV_CSPMU_EVENT_ATTR_4(ocu, gmem_rd_outstanding, 0x151), - NV_CSPMU_EVENT_ATTR_4(ocu, gmem_wr_outstanding, 0x155), - - NV_CSPMU_EVENT_ATTR_4(ocu, rem_rd_data, 0x159), - NV_CSPMU_EVENT_ATTR_4(ocu, rem_rd_access, 0x15d), - NV_CSPMU_EVENT_ATTR_4(ocu, rem_wb_access, 0x161), - NV_CSPMU_EVENT_ATTR_4(ocu, rem_rd_outstanding, 0x165), - NV_CSPMU_EVENT_ATTR_4(ocu, rem_wr_outstanding, 0x169), =20 ARM_CSPMU_EVENT_ATTR(gmem_rd_data, 0x16d), ARM_CSPMU_EVENT_ATTR(gmem_rd_access, 0x16e), ARM_CSPMU_EVENT_ATTR(gmem_rd_outstanding, 0x16f), - ARM_CSPMU_EVENT_ATTR(gmem_dl_rsp, 0x170), - ARM_CSPMU_EVENT_ATTR(gmem_dl_access, 0x171), - ARM_CSPMU_EVENT_ATTR(gmem_dl_outstanding, 0x172), ARM_CSPMU_EVENT_ATTR(gmem_wb_data, 0x173), ARM_CSPMU_EVENT_ATTR(gmem_wb_access, 0x174), - ARM_CSPMU_EVENT_ATTR(gmem_wb_outstanding, 0x175), - ARM_CSPMU_EVENT_ATTR(gmem_ev_rsp, 0x176), - ARM_CSPMU_EVENT_ATTR(gmem_ev_access, 0x177), - ARM_CSPMU_EVENT_ATTR(gmem_ev_outstanding, 0x178), ARM_CSPMU_EVENT_ATTR(gmem_wr_data, 0x179), - ARM_CSPMU_EVENT_ATTR(gmem_wr_outstanding, 0x17a), ARM_CSPMU_EVENT_ATTR(gmem_wr_access, 0x17b), =20 NV_CSPMU_EVENT_ATTR_4(socket, wr_data, 0x17c), =20 - NV_CSPMU_EVENT_ATTR_4(ocu, gmem_wr_data, 0x180), - NV_CSPMU_EVENT_ATTR_4(ocu, gmem_wb_data, 0x184), - NV_CSPMU_EVENT_ATTR_4(ocu, gmem_wr_access, 0x188), - NV_CSPMU_EVENT_ATTR_4(ocu, gmem_wb_outstanding, 0x18c), - - NV_CSPMU_EVENT_ATTR_4(ocu, rem_wr_data, 0x190), - NV_CSPMU_EVENT_ATTR_4(ocu, rem_wb_data, 0x194), - NV_CSPMU_EVENT_ATTR_4(ocu, rem_wr_access, 0x198), - NV_CSPMU_EVENT_ATTR_4(ocu, rem_wb_outstanding, 0x19c), - ARM_CSPMU_EVENT_ATTR(gmem_wr_total_bytes, 0x1a0), ARM_CSPMU_EVENT_ATTR(remote_socket_wr_total_bytes, 0x1a1), ARM_CSPMU_EVENT_ATTR(remote_socket_rd_data, 0x1a2), @@ -122,35 +81,12 @@ static struct attribute *scf_pmu_event_attrs[] =3D { ARM_CSPMU_EVENT_ATTR(cmem_rd_data, 0x1a5), ARM_CSPMU_EVENT_ATTR(cmem_rd_access, 0x1a6), ARM_CSPMU_EVENT_ATTR(cmem_rd_outstanding, 0x1a7), - ARM_CSPMU_EVENT_ATTR(cmem_dl_rsp, 0x1a8), - ARM_CSPMU_EVENT_ATTR(cmem_dl_access, 0x1a9), - ARM_CSPMU_EVENT_ATTR(cmem_dl_outstanding, 0x1aa), ARM_CSPMU_EVENT_ATTR(cmem_wb_data, 0x1ab), ARM_CSPMU_EVENT_ATTR(cmem_wb_access, 0x1ac), - ARM_CSPMU_EVENT_ATTR(cmem_wb_outstanding, 0x1ad), - ARM_CSPMU_EVENT_ATTR(cmem_ev_rsp, 0x1ae), - ARM_CSPMU_EVENT_ATTR(cmem_ev_access, 0x1af), - ARM_CSPMU_EVENT_ATTR(cmem_ev_outstanding, 0x1b0), ARM_CSPMU_EVENT_ATTR(cmem_wr_data, 0x1b1), - ARM_CSPMU_EVENT_ATTR(cmem_wr_outstanding, 0x1b2), - - NV_CSPMU_EVENT_ATTR_4(ocu, cmem_rd_data, 0x1b3), - NV_CSPMU_EVENT_ATTR_4(ocu, cmem_rd_access, 0x1b7), - NV_CSPMU_EVENT_ATTR_4(ocu, cmem_wb_access, 0x1bb), - NV_CSPMU_EVENT_ATTR_4(ocu, cmem_rd_outstanding, 0x1bf), - NV_CSPMU_EVENT_ATTR_4(ocu, cmem_wr_outstanding, 0x1c3), - - ARM_CSPMU_EVENT_ATTR(ocu_prb_access, 0x1c7), - ARM_CSPMU_EVENT_ATTR(ocu_prb_data, 0x1c8), - ARM_CSPMU_EVENT_ATTR(ocu_prb_outstanding, 0x1c9), =20 ARM_CSPMU_EVENT_ATTR(cmem_wr_access, 0x1ca), =20 - NV_CSPMU_EVENT_ATTR_4(ocu, cmem_wr_access, 0x1cb), - NV_CSPMU_EVENT_ATTR_4(ocu, cmem_wb_data, 0x1cf), - NV_CSPMU_EVENT_ATTR_4(ocu, cmem_wr_data, 0x1d3), - NV_CSPMU_EVENT_ATTR_4(ocu, cmem_wb_outstanding, 0x1d7), - ARM_CSPMU_EVENT_ATTR(cmem_wr_total_bytes, 0x1db), =20 ARM_CSPMU_EVENT_ATTR(cycles, ARM_CSPMU_EVT_CYCLES_DEFAULT), --=20 2.34.1 From nobody Fri Nov 29 14:33:35 2024 Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2067.outbound.protection.outlook.com [40.107.223.67]) (using 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X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CYXPR12MB9425 Content-Type: text/plain; charset="utf-8" Rename loc* and rem* events in CNVLINK PMU to cmem* and gmem* events. Signed-off-by: Besar Wicaksono --- drivers/perf/arm_cspmu/nvidia_cspmu.c | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/drivers/perf/arm_cspmu/nvidia_cspmu.c b/drivers/perf/arm_cspmu= /nvidia_cspmu.c index ea2d44adfa7c..d1cd9975e71a 100644 --- a/drivers/perf/arm_cspmu/nvidia_cspmu.c +++ b/drivers/perf/arm_cspmu/nvidia_cspmu.c @@ -112,6 +112,25 @@ static struct attribute *mcf_pmu_event_attrs[] =3D { NULL, }; =20 +static struct attribute *mcf_cnvlink_pmu_event_attrs[] =3D { + ARM_CSPMU_EVENT_ATTR(rd_bytes_cmem, 0x0), + ARM_CSPMU_EVENT_ATTR(rd_bytes_gmem, 0x1), + ARM_CSPMU_EVENT_ATTR(wr_bytes_cmem, 0x2), + ARM_CSPMU_EVENT_ATTR(wr_bytes_gmem, 0x3), + ARM_CSPMU_EVENT_ATTR(total_bytes_cmem, 0x4), + ARM_CSPMU_EVENT_ATTR(total_bytes_gmem, 0x5), + ARM_CSPMU_EVENT_ATTR(rd_req_cmem, 0x6), + ARM_CSPMU_EVENT_ATTR(rd_req_gmem, 0x7), + ARM_CSPMU_EVENT_ATTR(wr_req_cmem, 0x8), + ARM_CSPMU_EVENT_ATTR(wr_req_gmem, 0x9), + ARM_CSPMU_EVENT_ATTR(total_req_cmem, 0xa), + ARM_CSPMU_EVENT_ATTR(total_req_gmem, 0xb), + ARM_CSPMU_EVENT_ATTR(rd_cum_outs_cmem, 0xc), + ARM_CSPMU_EVENT_ATTR(rd_cum_outs_gmem, 0xd), + ARM_CSPMU_EVENT_ATTR(cycles, ARM_CSPMU_EVT_CYCLES_DEFAULT), + NULL, +}; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Sep 2024 22:00:09.8873 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1d112fcf-c67c-4593-f781-08dcd82d43ae X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH3PEPF00000009.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB7762 Content-Type: text/plain; charset="utf-8" Enable NVLINK-C2C port filtering to distinguish traffic from different GPUs connected to NVLINK-C2C. Signed-off-by: Besar Wicaksono --- Documentation/admin-guide/perf/nvidia-pmu.rst | 32 +++++++++++++++++++ drivers/perf/arm_cspmu/nvidia_cspmu.c | 7 ++-- 2 files changed, 36 insertions(+), 3 deletions(-) diff --git a/Documentation/admin-guide/perf/nvidia-pmu.rst b/Documentation/= admin-guide/perf/nvidia-pmu.rst index 2e0d47cfe7ea..6d1d3206b4ad 100644 --- a/Documentation/admin-guide/perf/nvidia-pmu.rst +++ b/Documentation/admin-guide/perf/nvidia-pmu.rst @@ -86,6 +86,22 @@ Example usage: =20 perf stat -a -e nvidia_nvlink_c2c0_pmu_3/event=3D0x0/ =20 +The NVLink-C2C has two ports that can be connected to one GPU (occupying b= oth +ports) or to two GPUs (one GPU per port). The user can use "port" bitmap +parameter to select the port(s) to monitor. Each bit represents the port n= umber, +e.g. "port=3D0x1" corresponds to port 0 and "port=3D0x3" is for port 0 and= 1. The +PMU will monitor both ports by default if not specified. + +Example for port filtering: + +* Count event id 0x0 from the GPU connected with socket 0 on port 0:: + + perf stat -a -e nvidia_nvlink_c2c0_pmu_0/event=3D0x0,port=3D0x1/ + +* Count event id 0x0 from the GPUs connected with socket 0 on port 0 and p= ort 1:: + + perf stat -a -e nvidia_nvlink_c2c0_pmu_0/event=3D0x0,port=3D0x3/ + NVLink-C2C1 PMU ------------------- =20 @@ -116,6 +132,22 @@ Example usage: =20 perf stat -a -e nvidia_nvlink_c2c1_pmu_3/event=3D0x0/ =20 +The NVLink-C2C has two ports that can be connected to one GPU (occupying b= oth +ports) or to two GPUs (one GPU per port). The user can use "port" bitmap +parameter to select the port(s) to monitor. Each bit represents the port n= umber, +e.g. "port=3D0x1" corresponds to port 0 and "port=3D0x3" is for port 0 and= 1. The +PMU will monitor both ports by default if not specified. + +Example for port filtering: + +* Count event id 0x0 from the GPU connected with socket 0 on port 0:: + + perf stat -a -e nvidia_nvlink_c2c1_pmu_0/event=3D0x0,port=3D0x1/ + +* Count event id 0x0 from the GPUs connected with socket 0 on port 0 and p= ort 1:: + + perf stat -a -e nvidia_nvlink_c2c1_pmu_0/event=3D0x0,port=3D0x3/ + CNVLink PMU --------------- =20 diff --git a/drivers/perf/arm_cspmu/nvidia_cspmu.c b/drivers/perf/arm_cspmu= /nvidia_cspmu.c index d1cd9975e71a..cd51177347e5 100644 --- a/drivers/perf/arm_cspmu/nvidia_cspmu.c +++ b/drivers/perf/arm_cspmu/nvidia_cspmu.c @@ -149,6 +149,7 @@ static struct attribute *pcie_pmu_format_attrs[] =3D { =20 static struct attribute *nvlink_c2c_pmu_format_attrs[] =3D { ARM_CSPMU_FORMAT_EVENT_ATTR, + ARM_CSPMU_FORMAT_ATTR(port, "config1:0-1"), NULL, }; =20 @@ -193,7 +194,7 @@ static u32 nv_cspmu_event_filter(const struct perf_even= t *event) const struct nv_cspmu_ctx *ctx =3D to_nv_cspmu_ctx(to_arm_cspmu(event->pmu)); =20 - if (ctx->filter_mask =3D=3D 0) + if (ctx->filter_mask =3D=3D 0 || event->attr.config1 =3D=3D 0) return ctx->filter_default_val; =20 return event->attr.config1 & ctx->filter_mask; @@ -229,7 +230,7 @@ static const struct nv_cspmu_match nv_cspmu_match[] =3D= { { .prodid =3D 0x104, .prodid_mask =3D NV_PRODID_MASK, - .filter_mask =3D 0x0, + .filter_mask =3D NV_NVL_C2C_FILTER_ID_MASK, .filter_default_val =3D NV_NVL_C2C_FILTER_ID_MASK, .name_pattern =3D "nvidia_nvlink_c2c1_pmu_%u", .name_fmt =3D NAME_FMT_SOCKET, @@ -239,7 +240,7 @@ static const struct nv_cspmu_match nv_cspmu_match[] =3D= { { .prodid =3D 0x105, .prodid_mask =3D NV_PRODID_MASK, - .filter_mask =3D 0x0, + .filter_mask =3D NV_NVL_C2C_FILTER_ID_MASK, .filter_default_val =3D NV_NVL_C2C_FILTER_ID_MASK, .name_pattern =3D "nvidia_nvlink_c2c0_pmu_%u", .name_fmt =3D NAME_FMT_SOCKET, --=20 2.34.1