From nobody Fri Nov 29 16:31:58 2024 Received: from mail-yw1-f201.google.com (mail-yw1-f201.google.com [209.85.128.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F19FF1CB336 for ; Wed, 18 Sep 2024 20:54:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726692843; cv=none; b=Ouoin+zO1FN5p+2TlXQxx3bipGt+eZlmWXeP6XfS400kyY5+JFzc9iOXu3IKRkitckIuQz6hbzPTPyMb9xyl0X3iI635qGPBBjl0aOicFSsx2qI67QvF/G8BZrXI9pa7tClsXkWmEVYD0EThwCjbdaojZiLF+l5aS9fDKMYJPqc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726692843; c=relaxed/simple; bh=p6MzaJUynW/JjkmeZKB5mW65nL3/Igk6OCMaHic7+aw=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=EGES8E+bN96GkGj29b2dE/E9bGdcHnTSMGoKBpd8+YV45WemG0lS2yO/P61L+/8R4GXQYftVO7nV1mBLHkSBVQHoYzUU2TrvGm5xUUbfyh1cy5aXzflHWDelWw2IxBDjRluBO90fPkCJ+th2W4YcTeZMyt9w6eIWs3LhF8+2l9o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--coltonlewis.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=SxvwbFWt; arc=none smtp.client-ip=209.85.128.201 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--coltonlewis.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="SxvwbFWt" Received: by mail-yw1-f201.google.com with SMTP id 00721157ae682-6ddcf7599ddso2271667b3.1 for ; Wed, 18 Sep 2024 13:54:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1726692841; x=1727297641; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=YwPgtOW129JrsQoACWdjEIl4s6WZlvFOhv3Du6OF+8U=; b=SxvwbFWtq/Snn8Opm0acT0QfMfIdgN1dq0W8sk1O7KOrYEPCwyEkmuiW1kTIvWw/Jp IMRiq8DB8T6ptwGLcouwfxB7Pm1aAMVjXQ4bR6RUOt355LAGotp0yGzwhpg0vup8qAa+ gglnsrl+GV7uDLG3i6+pq0MB1HZJt5DueTbO1QL9oW9EX4v/f8TTd3wR0efUPv2je4H+ ioinA2e/al6rHbRaVJ+A2HW3zD0JUCLioD/CD6B+ngTJeQLJaEBakg8Dpg/aBVPK5INy /tpcIfym8tvprxLN9qXEld4aQPprCAf38yxdCp69+C3878R0NSsAEnqQfmIMjShKV3eu 7RQA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726692841; x=1727297641; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=YwPgtOW129JrsQoACWdjEIl4s6WZlvFOhv3Du6OF+8U=; b=OYxwi4wIHdRPzUBzxcP3q8XCtaN7qd44iwC4u16FSb3fJwZo3nRJUmiKwYfbV5kjCf 2V/++IOE4WyNUgjE3JOpMAkJX1SYSQ65VSKhffDgAzV0TeQE07WWYfsADSTGaEtSENO2 hqGijLzGCeVZ2/KHlm5U9vjujmXpp+5Cx5bVjMDQE1dthxzd5GrZllzl0eaZruJ9ks4d WK6efRk9WLYUwIS4HfrAP/ynIlddDv9Dc3AxWb9WIz3JnD9VjD5kkft6vPrhSQPpQ0aP l1miNBnylNswT7i66AXaK1n80GB/Ecgw1aLD9pVnlUQb1N0ko3GcylGAKMhMfqKGsjth c8tA== X-Forwarded-Encrypted: i=1; AJvYcCUijC/BKST/kvIJ7IQwoHcAYNwIVmEIeCwARhQfrvBRGclRJSaiZYWWk755XP0IXinjByYWOsoTCZsO72o=@vger.kernel.org X-Gm-Message-State: AOJu0Yz6rqatbbA3P/ASp41VDdLZF14hCid3KIVcPF0iohTePuReS9gz TEY4M9LOtSs0R+055LB8o7CNqUkzJrqIPpcji0ROvWjOHEVSyJFMf9xD/1G0xBVbIIz+jp3UvLV cbhmFtckZ7wU7iVK9uDcVAA== X-Google-Smtp-Source: AGHT+IGRPIBH0lJ/zYqTw1ktDVZvUIdvA2LFZQYoQbGDgG/n34gqx1ZHStAZ7pNzlmKV4Cl93mXbQJCAfZuocHz/Dw== X-Received: from coltonlewis-kvm.c.googlers.com ([fda3:e722:ac3:cc00:11b:3898:ac11:fa18]) (user=coltonlewis job=sendgmr) by 2002:a81:cb07:0:b0:6db:e107:74cb with SMTP id 00721157ae682-6dbe1077640mr6957727b3.3.1726692840998; Wed, 18 Sep 2024 13:54:00 -0700 (PDT) Date: Wed, 18 Sep 2024 20:53:16 +0000 In-Reply-To: <20240918205319.3517569-1-coltonlewis@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240918205319.3517569-1-coltonlewis@google.com> X-Mailer: git-send-email 2.46.0.662.g92d0881bb0-goog Message-ID: <20240918205319.3517569-4-coltonlewis@google.com> Subject: [PATCH v2 3/6] KVM: x86: selftests: Set up AMD VM in pmu_counters_test From: Colton Lewis To: kvm@vger.kernel.org Cc: Mingwei Zhang , Jinrong Liang , Jim Mattson , Aaron Lewis , Sean Christopherson , Paolo Bonzini , Shuah Khan , linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, Colton Lewis Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Branch in main() depending on if the CPU is Intel or AMD. They are subject to vastly different requirements because the AMD PMU lacks many properties defined by the Intel PMU including the entire CPUID 0xa function where Intel stores all the PMU properties. AMD lacks this as well as any consistent notion of PMU versions as Intel does. Every feature is a separate flag and they aren't the same features as Intel. Set up a VM for testing core AMD counters and ensure proper CPUID features are set. Signed-off-by: Colton Lewis --- .../selftests/kvm/x86_64/pmu_counters_test.c | 104 ++++++++++++++---- 1 file changed, 83 insertions(+), 21 deletions(-) diff --git a/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c b/tools= /testing/selftests/kvm/x86_64/pmu_counters_test.c index 0e305e43a93b..5b240585edc5 100644 --- a/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c +++ b/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c @@ -30,10 +30,21 @@ #define NUM_INSNS_RETIRED (NUM_LOOPS * NUM_INSNS_PER_LOOP + NUM_EXTRA_INS= NS) =20 =20 +/* + * Limit testing to MSRs that are actually defined by Intel (in the SDM). = MSRs + * that aren't defined counter MSRs *probably* don't exist, but there's no + * guarantee that currently undefined MSR indices won't be used for someth= ing + * other than PMCs in the future. + */ +#define MAX_NR_GP_COUNTERS 8 +#define MAX_NR_FIXED_COUNTERS 3 +#define AMD_NR_CORE_COUNTERS 4 +#define AMD_NR_CORE_EXT_COUNTERS 6 + static uint8_t kvm_pmu_version; static bool kvm_has_perf_caps; =20 -static struct kvm_vm *pmu_vm_create_with_one_vcpu(struct kvm_vcpu **vcpu, +static struct kvm_vm *intel_pmu_vm_create(struct kvm_vcpu **vcpu, void *guest_code, uint8_t pmu_version, uint64_t perf_capabilities) @@ -303,7 +314,7 @@ static void test_arch_events(uint8_t pmu_version, uint6= 4_t perf_capabilities, if (!pmu_version) return; =20 - vm =3D pmu_vm_create_with_one_vcpu(&vcpu, guest_test_arch_events, + vm =3D intel_pmu_vm_create(&vcpu, guest_test_arch_events, pmu_version, perf_capabilities); =20 vcpu_set_cpuid_property(vcpu, X86_PROPERTY_PMU_EBX_BIT_VECTOR_LENGTH, @@ -316,15 +327,6 @@ static void test_arch_events(uint8_t pmu_version, uint= 64_t perf_capabilities, kvm_vm_free(vm); } =20 -/* - * Limit testing to MSRs that are actually defined by Intel (in the SDM). = MSRs - * that aren't defined counter MSRs *probably* don't exist, but there's no - * guarantee that currently undefined MSR indices won't be used for someth= ing - * other than PMCs in the future. - */ -#define MAX_NR_GP_COUNTERS 8 -#define MAX_NR_FIXED_COUNTERS 3 - #define GUEST_ASSERT_PMC_MSR_ACCESS(insn, msr, expect_gp, vector) \ __GUEST_ASSERT(expect_gp ? vector =3D=3D GP_VECTOR : !vector, \ "Expected %s on " #insn "(0x%x), got vector %u", \ @@ -463,7 +465,7 @@ static void test_gp_counters(uint8_t pmu_version, uint6= 4_t perf_capabilities, struct kvm_vcpu *vcpu; struct kvm_vm *vm; =20 - vm =3D pmu_vm_create_with_one_vcpu(&vcpu, guest_test_gp_counters, + vm =3D intel_pmu_vm_create(&vcpu, guest_test_gp_counters, pmu_version, perf_capabilities); =20 vcpu_set_cpuid_property(vcpu, X86_PROPERTY_PMU_NR_GP_COUNTERS, @@ -530,7 +532,7 @@ static void test_fixed_counters(uint8_t pmu_version, ui= nt64_t perf_capabilities, struct kvm_vcpu *vcpu; struct kvm_vm *vm; =20 - vm =3D pmu_vm_create_with_one_vcpu(&vcpu, guest_test_fixed_counters, + vm =3D intel_pmu_vm_create(&vcpu, guest_test_fixed_counters, pmu_version, perf_capabilities); =20 vcpu_set_cpuid_property(vcpu, X86_PROPERTY_PMU_FIXED_COUNTERS_BITMASK, @@ -627,18 +629,78 @@ static void test_intel_counters(void) } } =20 -int main(int argc, char *argv[]) +static uint8_t nr_core_counters(void) { - TEST_REQUIRE(kvm_is_pmu_enabled()); + uint8_t nr_counters =3D kvm_cpu_property(X86_PROPERTY_NUM_PERF_CTR_CORE); + bool core_ext =3D kvm_cpu_has(X86_FEATURE_PERF_CTR_EXT_CORE); + + if (nr_counters !=3D 0) + return nr_counters; + + if (core_ext) + return AMD_NR_CORE_EXT_COUNTERS; =20 - TEST_REQUIRE(host_cpu_is_intel); - TEST_REQUIRE(kvm_cpu_has_p(X86_PROPERTY_PMU_VERSION)); - TEST_REQUIRE(kvm_cpu_property(X86_PROPERTY_PMU_VERSION) > 0); + return AMD_NR_CORE_COUNTERS; =20 - kvm_pmu_version =3D kvm_cpu_property(X86_PROPERTY_PMU_VERSION); - kvm_has_perf_caps =3D kvm_cpu_has(X86_FEATURE_PDCM); +} + +static void guest_test_core_counters(void) +{ + GUEST_DONE(); +} + +static void test_core_counters(void) +{ + uint8_t nr_counters =3D nr_core_counters(); + bool core_ext =3D kvm_cpu_has(X86_FEATURE_PERF_CTR_EXT_CORE); + bool perfmon_v2 =3D kvm_cpu_has(X86_FEATURE_PERFMON_V2); + struct kvm_vcpu *vcpu; + struct kvm_vm *vm; + + for (uint8_t ce =3D 0; ce <=3D core_ext; ce++) { + for (uint8_t pm =3D 0; pm <=3D perfmon_v2; pm++) { + for (uint8_t nc =3D 0; nc <=3D nr_counters; nc++) { + vm =3D vm_create_with_one_vcpu(&vcpu, guest_test_core_counters); + + if (nc) + vcpu_set_cpuid_property( + vcpu, X86_PROPERTY_NUM_PERF_CTR_CORE, nc); + if (ce) + vcpu_set_cpuid_feature( + vcpu, X86_FEATURE_PERF_CTR_EXT_CORE); + if (pm) + vcpu_set_cpuid_feature( + vcpu, X86_FEATURE_PERFMON_V2); + + pr_info("Testing core counters: CoreExt =3D %u, PerfMonV2 =3D %u, NumC= ounters =3D %u\n", + ce, pm, nc); + run_vcpu(vcpu); + + kvm_vm_free(vm); + } + } + } +} + +static void test_amd_counters(void) +{ + test_core_counters(); +} =20 - test_intel_counters(); +int main(int argc, char *argv[]) +{ + TEST_REQUIRE(kvm_is_pmu_enabled()); + + if (host_cpu_is_intel) { + TEST_REQUIRE(kvm_cpu_has_p(X86_PROPERTY_PMU_VERSION)); + TEST_REQUIRE(kvm_cpu_property(X86_PROPERTY_PMU_VERSION) > 0); + kvm_pmu_version =3D kvm_cpu_property(X86_PROPERTY_PMU_VERSION); + kvm_has_perf_caps =3D kvm_cpu_has(X86_FEATURE_PDCM); + test_intel_counters(); + } else if (host_cpu_is_amd) { + /* AMD CPUs don't have the same properties to look at. */ + test_amd_counters(); + } =20 return 0; } --=20 2.46.0.662.g92d0881bb0-goog