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This SoM is used by W3 Board. LM7 features: - Rockchip RK3588 - LPDDR4x 4/8/16/32 GB - eMMC 16/32/64/128 GB Add devicetree binding for ArmSoM LM7 SoM. Signed-off-by: Jianfeng Liu Acked-by: Conor Dooley --- Documentation/devicetree/bindings/arm/rockchip.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Document= ation/devicetree/bindings/arm/rockchip.yaml index 687823e58c2..1ed72df971c 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -54,6 +54,13 @@ properties: - const: armsom,sige7 - const: rockchip,rk3588 =20 + - description: ArmSoM LM7 SoM + items: + - enum: + - armsom,w3 + - const: armsom,lm7 + - const: rockchip,rk3588 + - description: Asus Tinker board items: - const: asus,rk3288-tinker --=20 2.34.1 From nobody Fri Nov 29 14:38:29 2024 Received: from mail-pf1-f172.google.com (mail-pf1-f172.google.com [209.85.210.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B501D210EC; Wed, 18 Sep 2024 16:50:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" LM7 is an System on Module made by ArmSoM based on Rockchip RK3588. This SoM is used by W3 Board. LM7 features: - Rockchip RK3588 - LPDDR4x 4/8/16/32 GB - eMMC 16/32/64/128 GB Add support for ArmSoM LM7 SoM. Signed-off-by: Jianfeng Liu --- .../boot/dts/rockchip/rk3588-armsom-lm7.dtsi | 459 ++++++++++++++++++ 1 file changed, 459 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-armsom-lm7.dtsi diff --git a/arch/arm64/boot/dts/rockchip/rk3588-armsom-lm7.dtsi b/arch/arm= 64/boot/dts/rockchip/rk3588-armsom-lm7.dtsi new file mode 100644 index 00000000000..4e14c30c4ce --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-armsom-lm7.dtsi @@ -0,0 +1,459 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include +#include +#include "rk3588.dtsi" + +/ { + compatible =3D "armsom,lm7", "rockchip,rk3588"; + + aliases { + mmc0 =3D &sdhci; + }; + + chosen { + stdout-path =3D "serial2:1500000n8"; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1100000>; + regulator-max-microvolt =3D <1100000>; + vin-supply =3D <&vcc5v0_sys>; + }; +}; + +&cpu_b0 { + cpu-supply =3D <&vdd_cpu_big0_s0>; +}; + +&cpu_b1 { + cpu-supply =3D <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply =3D <&vdd_cpu_big1_s0>; +}; + +&cpu_b3 { + cpu-supply =3D <&vdd_cpu_big1_s0>; +}; + +&cpu_l0 { + cpu-supply =3D <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply =3D <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply =3D <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply =3D <&vdd_cpu_lit_s0>; +}; + +&gpu { + mali-supply =3D <&vdd_gpu_s0>; + status =3D "okay"; +}; + +&i2c0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c0m2_xfer>; + status =3D "okay"; + + vdd_cpu_big0_s0: regulator@42 { + compatible =3D "rockchip,rk8602"; + reg =3D <0x42>; + fcs,suspend-voltage-selector =3D <1>; + regulator-name =3D "vdd_cpu_big0_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <1050000>; + regulator-ramp-delay =3D <2300>; + vin-supply =3D <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: regulator@43 { + compatible =3D "rockchip,rk8603", "rockchip,rk8602"; + reg =3D <0x43>; + fcs,suspend-voltage-selector =3D <1>; + regulator-name =3D "vdd_cpu_big1_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <1050000>; + regulator-ramp-delay =3D <2300>; + vin-supply =3D <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&saradc { + vref-supply =3D <&avcc_1v8_s0>; + status =3D "okay"; +}; + +&sdhci { + bus-width =3D <8>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + no-sdio; + no-sd; + non-removable; + status =3D "okay"; +}; + +&spi2 { + status =3D "okay"; + assigned-clocks =3D <&cru CLK_SPI2>; + assigned-clock-rates =3D <200000000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&spi2m2_cs0 &spi2m2_pins>; + num-cs =3D <1>; + + pmic@0 { + compatible =3D "rockchip,rk806"; + spi-max-frequency =3D <1000000>; + reg =3D <0x0>; + + interrupt-parent =3D <&gpio0>; + interrupts =3D <7 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + + system-power-controller; + + vcc1-supply =3D <&vcc5v0_sys>; + vcc2-supply =3D <&vcc5v0_sys>; + vcc3-supply =3D <&vcc5v0_sys>; + vcc4-supply =3D <&vcc5v0_sys>; + vcc5-supply =3D <&vcc5v0_sys>; + vcc6-supply =3D <&vcc5v0_sys>; + vcc7-supply =3D <&vcc5v0_sys>; + vcc8-supply =3D <&vcc5v0_sys>; + vcc9-supply =3D <&vcc5v0_sys>; + vcc10-supply =3D <&vcc5v0_sys>; + vcc11-supply =3D <&vcc_2v0_pldo_s3>; + vcc12-supply =3D <&vcc5v0_sys>; + vcc13-supply =3D <&vcc_1v1_nldo_s3>; + vcc14-supply =3D <&vcc_1v1_nldo_s3>; + vcca-supply =3D <&vcc5v0_sys>; + + gpio-controller; + #gpio-cells =3D <2>; + + rk806_dvs1_null: dvs1-null-pins { + pins =3D "gpio_pwrctrl1"; + function =3D "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins =3D "gpio_pwrctrl2"; + function =3D "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins =3D "gpio_pwrctrl3"; + function =3D "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <950000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vdd_gpu_s0"; + regulator-enable-ramp-delay =3D <400>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <950000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vdd_cpu_lit_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <675000>; + regulator-max-microvolt =3D <750000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vdd_log_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt =3D <750000>; + }; + }; + + vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <950000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vdd_vdenc_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <675000>; + regulator-max-microvolt =3D <900000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vdd_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt =3D <850000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-name =3D "vdd2_ddr_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <2000000>; + regulator-max-microvolt =3D <2000000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vdd_2v0_pldo_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vcc_3v3_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <3300000>; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-always-on; + regulator-boot-on; + regulator-name =3D "vddq_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcc_1v8_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + avcc_1v8_s0: pldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "avcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: pldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + avdd_1v2_s0: pldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-name =3D "avdd_1v2_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s0: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vcc_3v3_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vccio_sd_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "pldo6_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <750000>; + regulator-max-microvolt =3D <750000>; + regulator-name =3D "vdd_0v75_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <750000>; + }; + }; + + vdd_ddr_pll_s0: nldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <850000>; + regulator-max-microvolt =3D <850000>; + regulator-name =3D "vdd_ddr_pll_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt =3D <850000>; + }; + }; + + avdd_0v75_s0: nldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <750000>; + regulator-max-microvolt =3D <750000>; + regulator-name =3D "avdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v85_s0: nldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <850000>; + regulator-max-microvolt =3D <850000>; + regulator-name =3D "vdd_0v85_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v75_s0: nldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <750000>; + regulator-max-microvolt =3D <750000>; + regulator-name =3D "vdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&tsadc { + status =3D "okay"; +}; --=20 2.34.1 From nobody Fri Nov 29 14:38:29 2024 Received: from mail-pg1-f180.google.com (mail-pg1-f180.google.com [209.85.215.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 42C061C9DD2; Wed, 18 Sep 2024 16:50:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.215.180 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726678237; cv=none; b=Frq9TCjmAvM8a5Yvtc8+FwtabfYKbLJ19VdjwT+0EbUxH8lZomuC2xTgZJxGehzpyb2RGZZvM3OVCgh/4HdsNVn3pWcvatvrxJuNgwMvkCjOiEqC2mtFm9eykv+TlhLYE1zsxjE5/q6xxtvaxoFEbLqyOw4EUbSX2SGozFzidkg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726678237; c=relaxed/simple; bh=L194GVPqlhEKTAjInwLGnwQ9t2gUkt6Las6bQjzBuic=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; 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charset="utf-8" W3 is the carrier board for LM7 System on Module. W3 features: - 1x 2.5GbE Realtek RTL8125 Ethernet - 2x HDMI Type A out - 1x HDMI Type A in - 1x USB 3.1 Type C - 2x USB 2.0 Type A - 2x USB 3.0 Type A - 1x PCIE 2.0 M.2 E Key (1 lane) - 1x PCIE 3.0 PCIe (4 lanes) - 1x TF scard slot - 1x MIPI CSI - 1x MIPI DSI - 1x ES8316 audio jack - 1x FAN connector - 1x RTC - 40-pin expansion header Add support for ArmSoM LM7 board. Signed-off-by: Jianfeng Liu --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../boot/dts/rockchip/rk3588-armsom-w3.dts | 408 ++++++++++++++++++ 2 files changed, 409 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-armsom-w3.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/ro= ckchip/Makefile index 09423070c99..b0ed12f41f0 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -125,6 +125,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-wolfvision-pf5.= dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-wolfvision-pf5-display-vz.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-wolfvision-pf5-io-expander.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-armsom-sige7.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-armsom-w3.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-coolpi-cm5-evb.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-coolpi-cm5-genbook.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-edgeble-neu6a-io.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3588-armsom-w3.dts b/arch/arm64= /boot/dts/rockchip/rk3588-armsom-w3.dts new file mode 100644 index 00000000000..321a44f081c --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-armsom-w3.dts @@ -0,0 +1,408 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include +#include +#include "rk3588-armsom-lm7.dtsi" + +/ { + model =3D "ArmSoM W3"; + compatible =3D "armsom,w3", "armsom,lm7", "rockchip,rk3588"; + + aliases { + mmc1 =3D &sdmmc; + mmc2 =3D &sdio; + }; + + analog-sound { + compatible =3D "audio-graph-card"; + label =3D "rk3588-es8316"; + + widgets =3D "Microphone", "Mic Jack", + "Headphone", "Headphones"; + + routing =3D "MIC2", "Mic Jack", + "Headphones", "HPOL", + "Headphones", "HPOR"; + + dais =3D <&i2s0_8ch_p0>; + hp-det-gpio =3D <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&hp_detect>; + }; + + leds { + compatible =3D "gpio-leds"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&led_rgb_b>; + + led_rgb_b { + function =3D LED_FUNCTION_STATUS; + color =3D ; + gpios =3D <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + linux,default-trigger =3D "heartbeat"; + }; + + led_rgb_r { + function =3D LED_FUNCTION_STATUS; + color =3D ; + gpios =3D <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>; + linux,default-trigger =3D "none"; + }; + }; + + fan: pwm-fan { + compatible =3D "pwm-fan"; + cooling-levels =3D <0 120 150 180 210 240 255>; + fan-supply =3D <&vcc5v0_sys>; + pwms =3D <&pwm1 0 50000 0>; + #cooling-cells =3D <2>; + }; + + rfkill { + compatible =3D "rfkill-gpio"; + label =3D "rfkill-pcie-wlan"; + radio-type =3D "wlan"; + shutdown-gpios =3D <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + }; + + rfkill-bt { + compatible =3D "rfkill-gpio"; + label =3D "rfkill-m2-bt"; + radio-type =3D "bluetooth"; + shutdown-gpios =3D <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; + }; + + vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0-regulator { + compatible =3D "regulator-fixed"; + enable-active-high; + gpios =3D <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie2_0_vcc3v3_en>; + regulator-name =3D "vcc3v3_pcie2x1l0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + startup-delay-us =3D <50000>; + vin-supply =3D <&vcc5v0_sys>; + }; + + vcc3v3_pcie2x1l2: vcc3v3-pcie2x1l2-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc3v3_pcie2x1l2"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + startup-delay-us =3D <5000>; + vin-supply =3D <&vcc_3v3_s3>; + }; + + vcc3v3_pcie30: vcc3v3-pcie30-regulator { + compatible =3D "regulator-fixed"; + enable-active-high; + gpios =3D <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie3_vcc3v3_en>; + regulator-name =3D "vcc3v3_pcie30"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + startup-delay-us =3D <5000>; + vin-supply =3D <&vcc5v0_sys>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + enable-active-high; + gpio =3D <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&vcc5v0_host_en>; + vin-supply =3D <&vcc5v0_sys>; + }; +}; + +&combphy0_ps { + status =3D "okay"; +}; + +&combphy1_ps { + status =3D "okay"; +}; + +&combphy2_psu { + status =3D "okay"; +}; + +&i2c6 { + status =3D "okay"; + + hym8563: rtc@51 { + compatible =3D "haoyu,hym8563"; + reg =3D <0x51>; + #clock-cells =3D <0>; + clock-output-names =3D "hym8563"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&hym8563_int>; + interrupt-parent =3D <&gpio0>; + interrupts =3D ; + wakeup-source; + }; +}; + +&i2c7 { + status =3D "okay"; + + es8316: audio-codec@11 { + compatible =3D "everest,es8316"; + reg =3D <0x11>; + clocks =3D <&cru I2S0_8CH_MCLKOUT>; + clock-names =3D "mclk"; + assigned-clocks =3D <&cru I2S0_8CH_MCLKOUT>; + assigned-clock-rates =3D <12288000>; + #sound-dai-cells =3D <0>; + + port { + es8316_p0_0: endpoint { + remote-endpoint =3D <&i2s0_8ch_p0_0>; + }; + }; + }; +}; + +&i2s0_8ch { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2s0_lrck + &i2s0_mclk + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; + status =3D "okay"; + + i2s0_8ch_p0: port { + i2s0_8ch_p0_0: endpoint { + dai-format =3D "i2s"; + mclk-fs =3D <256>; + remote-endpoint =3D <&es8316_p0_0>; + }; + }; +}; + +&package_thermal { + polling-delay =3D <1000>; + + trips { + package_fan0: package-fan0 { + temperature =3D <55000>; + hysteresis =3D <2000>; + type =3D "active"; + }; + + package_fan1: package-fan1 { + temperature =3D <65000>; + hysteresis =3D <2000>; + type =3D "active"; + }; + }; + + cooling-maps { + map1 { + trip =3D <&package_fan0>; + cooling-device =3D <&fan THERMAL_NO_LIMIT 1>; + }; + + map2 { + trip =3D <&package_fan1>; + cooling-device =3D <&fan 2 THERMAL_NO_LIMIT>; + }; + }; +}; + +&pcie2x1l0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie2_0_rst>; + reset-gpios =3D <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply =3D <&vcc3v3_pcie2x1l0>; + status =3D "okay"; +}; + +&pcie2x1l2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie2_2_rst>; + reset-gpios =3D <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply =3D <&vcc3v3_pcie2x1l2>; + status =3D "okay"; +}; + +&pcie30phy { + status =3D "okay"; +}; + +&pcie3x4 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie3_rst>; + reset-gpios =3D <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply =3D <&vcc3v3_pcie30>; + status =3D "okay"; +}; + +&pinctrl { + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins =3D <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + led_rgb_b: led-rgb-b { + rockchip,pins =3D <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sound { + hp_detect: hp-detect { + rockchip,pins =3D <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie2 { + pcie2_0_rst: pcie2-0-rst { + rockchip,pins =3D <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie2_0_vcc3v3_en: pcie2-0-vcc-en { + rockchip,pins =3D <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie2_2_rst: pcie2-2-rst { + rockchip,pins =3D <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie3 { + pcie3_rst: pcie3-rst { + rockchip,pins =3D <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie3_vcc3v3_en: pcie3-vcc3v3-en { + rockchip,pins =3D <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins =3D <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm1 { + status =3D "okay"; +}; + +&sdmmc { + max-frequency =3D <200000000>; + no-sdio; + no-mmc; + bus-width =3D <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + cd-gpios =3D <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + disable-wp; + sd-uhs-sdr104; + vmmc-supply =3D <&vcc_3v3_s3>; + vqmmc-supply =3D <&vccio_sd_s0>; + status =3D "okay"; +}; + +&sdio { + max-frequency =3D <200000000>; + no-sd; + no-mmc; + non-removable; + bus-width =3D <4>; + cap-sdio-irq; + disable-wp; + keep-power-in-suspend; + wakeup-source; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + vmmc-supply =3D <&vcc3v3_pcie2x1l0>; + vqmmc-supply =3D <&vcc_1v8_s3>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&sdiom0_pins>; + status =3D "okay"; +}; + +&uart6 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart6m1_xfer &uart6m1_ctsn &uart6m1_rtsn>; + status =3D "okay"; +}; + +&uart2 { + pinctrl-0 =3D <&uart2m0_xfer>; + status =3D "okay"; +}; + +&u2phy1 { + status =3D "okay"; +}; + +&u2phy1_otg { + status =3D "okay"; +}; + +&u2phy2 { + status =3D "okay"; +}; + +&u2phy2_host { + /* connected to USB hub, which is powered by vcc5v0_sys */ + phy-supply =3D <&vcc5v0_sys>; + status =3D "okay"; +}; + +&u2phy3 { + status =3D "okay"; +}; + +&u2phy3_host { + phy-supply =3D <&vcc5v0_host>; + status =3D "okay"; +}; + +&usbdp_phy1 { + status =3D "okay"; +}; + +&usb_host0_ehci { + status =3D "okay"; +}; + +&usb_host0_ohci { + status =3D "okay"; +}; + +&usb_host1_ehci { + status =3D "okay"; +}; + +&usb_host1_ohci { + status =3D "okay"; +}; + +&usb_host1_xhci { + dr_mode =3D "host"; + status =3D "okay"; +}; + +&usb_host2_xhci { + status =3D "okay"; +}; --=20 2.34.1