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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Sep 2024 10:58:38.8378 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9f82eb01-cfc7-4ead-7352-08dcd7d0d9f9 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF00000205.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB6655 Content-Type: text/plain; charset="utf-8" AMD SoC has HID2 SPI controller in addition to the existing SPI0 controller(AMDI0062). Add HID2 SPI controller's ACPI ID AMDI0063 with its version ID to the list of supported devices. And, use the version ID to differentiate the register offsets. Co-developed-by: Akshata MukundShetty Signed-off-by: Akshata MukundShetty Signed-off-by: Raju Rangoju --- drivers/spi/spi-amd.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-amd.c b/drivers/spi/spi-amd.c index c265e37cebc4..ccad969f501f 100644 --- a/drivers/spi/spi-amd.c +++ b/drivers/spi/spi-amd.c @@ -55,10 +55,12 @@ * enum amd_spi_versions - SPI controller versions * @AMD_SPI_V1: AMDI0061 hardware version * @AMD_SPI_V2: AMDI0062 hardware version + * @AMD_HID2_SPI: AMDI0063 hardware version */ enum amd_spi_versions { AMD_SPI_V1 =3D 1, AMD_SPI_V2, + AMD_HID2_SPI, }; =20 enum amd_spi_speed { @@ -167,6 +169,7 @@ static int amd_spi_set_opcode(struct amd_spi *amd_spi, = u8 cmd_opcode) AMD_SPI_OPCODE_MASK); return 0; case AMD_SPI_V2: + case AMD_HID2_SPI: amd_spi_writereg8(amd_spi, AMD_SPI_OPCODE_REG, cmd_opcode); return 0; default: @@ -194,6 +197,7 @@ static int amd_spi_busy_wait(struct amd_spi *amd_spi) reg =3D AMD_SPI_CTRL0_REG; break; case AMD_SPI_V2: + case AMD_HID2_SPI: reg =3D AMD_SPI_STATUS_REG; break; default: @@ -219,6 +223,7 @@ static int amd_spi_execute_opcode(struct amd_spi *amd_s= pi) AMD_SPI_EXEC_CMD); return 0; case AMD_SPI_V2: + case AMD_HID2_SPI: /* Trigger the command execution */ amd_spi_setclear_reg8(amd_spi, AMD_SPI_CMD_TRIGGER_REG, AMD_SPI_TRIGGER_CMD, AMD_SPI_TRIGGER_CMD); @@ -360,6 +365,7 @@ static inline int amd_spi_fifo_xfer(struct amd_spi *amd= _spi, case AMD_SPI_V1: break; case AMD_SPI_V2: + case AMD_HID2_SPI: amd_spi_clear_chip(amd_spi, spi_get_chipselect(message->spi, 0)); break; default: @@ -541,7 +547,7 @@ static int amd_spi_probe(struct platform_device *pdev) amd_spi->version =3D (uintptr_t) device_get_match_data(dev); =20 /* Initialize the spi_controller fields */ - host->bus_num =3D 0; + host->bus_num =3D (amd_spi->version =3D=3D AMD_HID2_SPI) ? 2 : 0; host->num_chipselect =3D 4; host->mode_bits =3D SPI_TX_DUAL | SPI_TX_QUAD | SPI_RX_DUAL | SPI_RX_QUAD; host->flags =3D SPI_CONTROLLER_HALF_DUPLEX; @@ -565,6 +571,7 @@ static int amd_spi_probe(struct platform_device *pdev) static const struct acpi_device_id spi_acpi_match[] =3D { { "AMDI0061", AMD_SPI_V1 }, { "AMDI0062", AMD_SPI_V2 }, + { "AMDI0063", AMD_HID2_SPI }, {}, }; MODULE_DEVICE_TABLE(acpi, spi_acpi_match); --=20 2.34.1