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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Sep 2024 10:58:34.9355 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 341c52f6-cd08-475b-9f76-08dcd7d0d7a3 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF00000209.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB5885 Content-Type: text/plain; charset="utf-8" AMD SPI TX and RX counter registers are 1-byte length registers. The existing value will be overwritten during register write, so masking is not required. Co-developed-by: Krishnamoorthi M Signed-off-by: Krishnamoorthi M Co-developed-by: Akshata MukundShetty Signed-off-by: Akshata MukundShetty Signed-off-by: Raju Rangoju --- drivers/spi/spi-amd.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-amd.c b/drivers/spi/spi-amd.c index 11ae910bb420..eb16063ba121 100644 --- a/drivers/spi/spi-amd.c +++ b/drivers/spi/spi-amd.c @@ -165,12 +165,12 @@ static int amd_spi_set_opcode(struct amd_spi *amd_spi= , u8 cmd_opcode) =20 static inline void amd_spi_set_rx_count(struct amd_spi *amd_spi, u8 rx_cou= nt) { - amd_spi_setclear_reg8(amd_spi, AMD_SPI_RX_COUNT_REG, rx_count, 0xff); + amd_spi_writereg8(amd_spi, AMD_SPI_RX_COUNT_REG, rx_count); } =20 static inline void amd_spi_set_tx_count(struct amd_spi *amd_spi, u8 tx_cou= nt) { - amd_spi_setclear_reg8(amd_spi, AMD_SPI_TX_COUNT_REG, tx_count, 0xff); + amd_spi_writereg8(amd_spi, AMD_SPI_TX_COUNT_REG, tx_count); } =20 static int amd_spi_busy_wait(struct amd_spi *amd_spi) --=20 2.34.1