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Lin" , Singo Chang , "Nancy Lin" , Subject: [PATCH v3] drm/mediatek: ovl: Add fmt_convert function pointer to driver data Date: Wed, 18 Sep 2024 00:44:34 +0800 Message-ID: <20240917164434.17794-1-jason-jh.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--12.162200-8.000000 X-TMASE-MatchedRID: 4LZxuBlJqUUzP1+hKLmUcMu00lnG8+PWIaLR+2xKRDLb6Y+fnTZULz94 HX24gqtCCInppypKAT/VoxB0j4x40LQ9EkyAW8JW2OSj4qJA9QbeHKxRMJ4P8diCsYPC4Ul22ft v/5jXki+muE8sHNH+0RUh680kRJ0sVWO7fs8MQC7k7k9yXJiqqhZO94uK1VSBWabPstVV86l6gt iEqf13+84WZ2e8JNtqZmkxQVgZGGRLdmeL82hot98tWTI1R8ep/5QRvrl2CZDzYcyIF7RSVb5Sd /nplJIc4vM1YF6AJbbCCfuIMF6xLSAHAopEd76vOhFpIr55H3NVjx/3+Flhi5F2YlOFSiZmwi3T t1ZQFjCcb1Pw5XWcDw== X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--12.162200-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 4048DE2440AFB7BC677F4ECD18AB14426478FB263DF3AD24EB84EE36FFD723D02000:8 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" OVL_CON_CLRFMT_MAN is a configuration for extending color format settings of DISP_REG_OVL_CON(n). It will change some of the original color format settings. Take the settings of (3 << 12) for example. - If OVL_CON_CLRFMT_MAN =3D 0 means OVL_CON_CLRFMT_RGBA8888. - If OVL_CON_CLRFMT_MAN =3D 1 means OVL_CON_CLRFMT_PARGB8888. Since OVL_CON_CLRFMT_MAN is not supported on previous SoCs, It breaks the OVL color format setting of MT8173. Therefore, the fmt_convert function pointer is added to the driver data and mtk_ovl_fmt_convert_with_blend is implemented for MT8192 and MT8195 that support OVL_CON_CLRFMT_MAN, and mtk_ovl_fmt_convert is implemented for other SoCs that do not support it to solve the degradation problem. Fixes: a3f7f7ef4bfe ("drm/mediatek: Support "Pre-multiplied" blending in OV= L") Signed-off-by: Jason-JH.Lin Tested-by: Alper Nebi Yasak Reviewed-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 63 ++++++++++++++++++++++--- 1 file changed, 56 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/medi= atek/mtk_disp_ovl.c index 89b439dcf3a6..4948f269fb81 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -143,6 +143,7 @@ struct mtk_disp_ovl_data { unsigned int addr; unsigned int gmc_bits; unsigned int layer_nr; + unsigned int (*fmt_convert)(struct device *dev, struct mtk_plane_state *s= tate); bool fmt_rgb565_is_0; bool smi_id_en; bool supports_afbc; @@ -386,13 +387,54 @@ void mtk_ovl_layer_off(struct device *dev, unsigned i= nt idx, DISP_REG_OVL_RDMA_CTRL(idx)); } =20 -static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, unsigned int= fmt, - unsigned int blend_mode) +static unsigned int mtk_ovl_fmt_convert(struct device *dev, struct mtk_pla= ne_state *state) { - /* The return value in switch "MEM_MODE_INPUT_FORMAT_XXX" - * is defined in mediatek HW data sheet. - * The alphabet order in XXX is no relation to data - * arrangement in memory. + struct mtk_disp_ovl *ovl =3D dev_get_drvdata(dev); + unsigned int fmt =3D state->pending.format; + + switch (fmt) { + default: + case DRM_FORMAT_RGB565: + return OVL_CON_CLRFMT_RGB565(ovl); + case DRM_FORMAT_BGR565: + return OVL_CON_CLRFMT_RGB565(ovl) | OVL_CON_BYTE_SWAP; + case DRM_FORMAT_RGB888: + return OVL_CON_CLRFMT_RGB888(ovl); + case DRM_FORMAT_BGR888: + return OVL_CON_CLRFMT_RGB888(ovl) | OVL_CON_BYTE_SWAP; + case DRM_FORMAT_RGBX8888: + case DRM_FORMAT_RGBA8888: + case DRM_FORMAT_RGBX1010102: + case DRM_FORMAT_RGBA1010102: + return OVL_CON_CLRFMT_RGBA8888; + case DRM_FORMAT_XRGB8888: + case DRM_FORMAT_ARGB8888: + case DRM_FORMAT_XRGB2101010: + case DRM_FORMAT_ARGB2101010: + return OVL_CON_CLRFMT_ARGB8888; + case DRM_FORMAT_XBGR8888: + case DRM_FORMAT_ABGR8888: + case DRM_FORMAT_XBGR2101010: + case DRM_FORMAT_ABGR2101010: + return OVL_CON_CLRFMT_ABGR8888; + case DRM_FORMAT_UYVY: + return OVL_CON_CLRFMT_UYVY | OVL_CON_MTX_YUV_TO_RGB; + case DRM_FORMAT_YUYV: + return OVL_CON_CLRFMT_YUYV | OVL_CON_MTX_YUV_TO_RGB; + } +} + +static unsigned int mtk_ovl_fmt_convert_with_blend(struct device *dev, + struct mtk_plane_state *state) +{ + struct mtk_disp_ovl *ovl =3D dev_get_drvdata(dev); + unsigned int fmt =3D state->pending.format; + unsigned int blend_mode =3D state->base.pixel_blend_mode; + + /* + * For the platforms where OVL_CON_CLRFMT_MAN is defined in the + * hardware data sheet and supports premultiplied color formats + * such as OVL_CON_CLRFMT_PRGB8888. */ switch (fmt) { default: @@ -471,7 +513,7 @@ void mtk_ovl_layer_config(struct device *dev, unsigned = int idx, return; } =20 - con =3D ovl_fmt_convert(ovl, fmt, blend_mode); + con =3D ovl->data->fmt_convert(dev, state); if (state->base.fb) { con |=3D OVL_CON_AEN; con |=3D state->base.alpha & OVL_CON_ALPHA; @@ -625,6 +667,7 @@ static const struct mtk_disp_ovl_data mt2701_ovl_driver= _data =3D { .addr =3D DISP_REG_OVL_ADDR_MT2701, .gmc_bits =3D 8, .layer_nr =3D 4, + .fmt_convert =3D mtk_ovl_fmt_convert, .fmt_rgb565_is_0 =3D false, .formats =3D mt8173_formats, .num_formats =3D ARRAY_SIZE(mt8173_formats), @@ -634,6 +677,7 @@ static const struct mtk_disp_ovl_data mt8173_ovl_driver= _data =3D { .addr =3D DISP_REG_OVL_ADDR_MT8173, .gmc_bits =3D 8, .layer_nr =3D 4, + .fmt_convert =3D mtk_ovl_fmt_convert, .fmt_rgb565_is_0 =3D true, .formats =3D mt8173_formats, .num_formats =3D ARRAY_SIZE(mt8173_formats), @@ -643,6 +687,7 @@ static const struct mtk_disp_ovl_data mt8183_ovl_driver= _data =3D { .addr =3D DISP_REG_OVL_ADDR_MT8173, .gmc_bits =3D 10, .layer_nr =3D 4, + .fmt_convert =3D mtk_ovl_fmt_convert, .fmt_rgb565_is_0 =3D true, .formats =3D mt8173_formats, .num_formats =3D ARRAY_SIZE(mt8173_formats), @@ -652,6 +697,7 @@ static const struct mtk_disp_ovl_data mt8183_ovl_2l_dri= ver_data =3D { .addr =3D DISP_REG_OVL_ADDR_MT8173, .gmc_bits =3D 10, .layer_nr =3D 2, + .fmt_convert =3D mtk_ovl_fmt_convert, .fmt_rgb565_is_0 =3D true, .formats =3D mt8173_formats, .num_formats =3D ARRAY_SIZE(mt8173_formats), @@ -661,6 +707,7 @@ static const struct mtk_disp_ovl_data mt8192_ovl_driver= _data =3D { .addr =3D DISP_REG_OVL_ADDR_MT8173, .gmc_bits =3D 10, .layer_nr =3D 4, + .fmt_convert =3D mtk_ovl_fmt_convert_with_blend, .fmt_rgb565_is_0 =3D true, .smi_id_en =3D true, .formats =3D mt8173_formats, @@ -671,6 +718,7 @@ static const struct mtk_disp_ovl_data mt8192_ovl_2l_dri= ver_data =3D { .addr =3D DISP_REG_OVL_ADDR_MT8173, .gmc_bits =3D 10, .layer_nr =3D 2, + .fmt_convert =3D mtk_ovl_fmt_convert_with_blend, .fmt_rgb565_is_0 =3D true, .smi_id_en =3D true, .formats =3D mt8173_formats, @@ -681,6 +729,7 @@ static const struct mtk_disp_ovl_data mt8195_ovl_driver= _data =3D { .addr =3D DISP_REG_OVL_ADDR_MT8173, .gmc_bits =3D 10, .layer_nr =3D 4, + .fmt_convert =3D mtk_ovl_fmt_convert_with_blend, .fmt_rgb565_is_0 =3D true, .smi_id_en =3D true, .supports_afbc =3D true, --=20 2.43.0