From nobody Fri Nov 29 18:33:15 2024 Received: from uho.ysoft.cz (uho.ysoft.cz [81.19.3.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 873A51A0B0F; Tue, 17 Sep 2024 15:11:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=81.19.3.130 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726585877; cv=none; b=OUzN7KSoedDan5/sxy6unYu5ssSCd5rCgFpc8IeaSW2VLsDi0jnQ7UWsFS4Z+eE5eohfjSN9lJAHtO85dwgQqXmLK6mU+woiNh84VWg3t0AYQj2nfKosMLGnURJR5zTCmL0Eh3qCe1rWZQciLGmFkfRdym4SNi9CMZ2JPpogES0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726585877; c=relaxed/simple; bh=MSDE1YisBDhBfclGcQGQr63axeklACb9lpmz5biYqYU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=MoX15i6dWunBzVWyrVxLpiyAg0x1UF5IOj6t0wYW/rIDfNvUUpKDZe8hBv49zoBJuxnRM6a5F44Bs+N/Gxv8tIRBankoLCaxa02xBEsZAZpS5PCjcoaNXaErFd5qLaO3+/6fWFpfzMWOPxs5mguCNKWw9fr9RtEnZqcGRB9SLQY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ysoft.com; spf=pass smtp.mailfrom=ysoft.com; dkim=pass (1024-bit key) header.d=ysoft.com header.i=@ysoft.com header.b=OUB9N7Mm; arc=none smtp.client-ip=81.19.3.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ysoft.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ysoft.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ysoft.com header.i=@ysoft.com header.b="OUB9N7Mm" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ysoft.com; s=20160406-ysoft-com; t=1726585874; bh=n2EsA9zRqXjD/m3Iloey1Ttl1cv8J/KbWK52Kpw1a98=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=OUB9N7MmwMjBMBSiwqhs+AOK/tu726pvSwG84VgZn0cADLlgl/Rh1ZXtid4vM6JLx W/t5AAk8tKTUsF4CWhB4daZEY0YqezeeeCC6pcN5xShjYA9YS7JMWgP4WR+Dx4Sg+V CtE7gMNAiLJA7dOoK6GufkLHUlCYVaVmbamAW7rw= Received: from vokac-nb.ysoft.local (unknown [10.1.8.111]) by uho.ysoft.cz (Postfix) with ESMTP id C54F3A1B72; Tue, 17 Sep 2024 17:11:13 +0200 (CEST) From: =?UTF-8?q?Michal=20Vok=C3=A1=C4=8D?= To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Greg Kroah-Hartman , Shawn Guo , Petr Benes Cc: Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Herburger , Hiago De Franco , Hugo Villeneuve , Joao Paulo Goncalves , Michael Walle , Alexander Stein , Mathieu Othacehe , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, =?UTF-8?q?Michal=20Vok=C3=A1=C4=8D?= Subject: [PATCH 2/4] arm64: dts: imx: Add imx8mp-iota2-lumpy board Date: Tue, 17 Sep 2024 17:09:59 +0200 Message-ID: <20240917151001.1289399-3-michal.vokac@ysoft.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240917151001.1289399-1-michal.vokac@ysoft.com> References: <20240917151001.1289399-1-michal.vokac@ysoft.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The IOTA2 Lumpy board is based on the i.MX8MPlus EVK. Basic features are: - 4GB LPDDR4 - 64GB eMMC - 2x 1GB Ethernet - USB 3.0 Type-C dual role port, without power delivery - USB 3.0 Type-A host port - RGB LED - PWM driven - speaker - PWM driven - RTC with super capacitor backup Signed-off-by: Michal Vok=C3=A1=C4=8D --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../boot/dts/freescale/imx8mp-iota2-lumpy.dts | 425 ++++++++++++++++++ 2 files changed, 426 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-iota2-lumpy.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/f= reescale/Makefile index f04c22b7de72..421c36c5ae68 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -171,6 +171,7 @@ dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-dhcom-pdk2.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-dhcom-pdk3.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-evk.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-icore-mx8mp-edimm2.2.dtb +dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-iota2-lumpy.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-msc-sm2s-ep1.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-navqp.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-phyboard-pollux-rdk.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mp-iota2-lumpy.dts b/arch/ar= m64/boot/dts/freescale/imx8mp-iota2-lumpy.dts new file mode 100644 index 000000000000..21d0899cabd5 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-iota2-lumpy.dts @@ -0,0 +1,425 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2023 Y Soft + */ + +/dts-v1/; + +#include "imx8mp.dtsi" + +/ { + model =3D "Y Soft i.MX8MPlus IOTA2 Lumpy board"; + compatible =3D "ysoft,imx8mp-iota2-lumpy", "fsl,imx8mp"; + + chosen { + stdout-path =3D &uart2; + }; + + beeper { + compatible =3D "pwm-beeper"; + pwms =3D <&pwm4 0 500000 0>; + }; + + gpio_keys: gpio-keys { + compatible =3D "gpio-keys"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_gpio_keys>; + + button-reset { + label =3D "Factory RESET"; + linux,code =3D ; + gpios =3D <&gpio1 7 GPIO_ACTIVE_LOW>; + }; + }; + + memory@40000000 { + device_type =3D "memory"; + reg =3D <0x0 0x40000000 0 0x80000000>, + <0x1 0x00000000 0 0x80000000>; + }; + + reg_usb_host: regulator-usb-host { + compatible =3D "regulator-fixed"; + enable-active-high; + gpio =3D <&gpio1 14 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_usb_host_vbus>; + regulator-max-microvolt =3D <5000000>; + regulator-min-microvolt =3D <5000000>; + regulator-name =3D "usb-host"; + }; +}; + +&A53_0 { + cpu-supply =3D <®_arm>; +}; + +&A53_1 { + cpu-supply =3D <®_arm>; +}; + +&A53_2 { + cpu-supply =3D <®_arm>; +}; + +&A53_3 { + cpu-supply =3D <®_arm>; +}; + +&eqos { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_eqos>; + phy-mode =3D "rgmii-id"; + phy-handle =3D <ðphy0>; + status =3D "okay"; + + mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + ethphy0: ethernet-phy@0 { + pinctrl-0 =3D <&pinctrl_ethphy0>; + pinctrl-names =3D "default"; + reg =3D <0>; + interrupt-parent =3D <&gpio3>; + interrupts =3D <21 IRQ_TYPE_LEVEL_LOW>; + micrel,led-mode =3D <0>; + reset-gpios =3D <&gpio3 22 GPIO_ACTIVE_LOW>; + reset-assert-us =3D <1000>; + reset-deassert-us =3D <1000>; + }; + }; +}; + +&fec { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_fec>; + phy-mode =3D "rgmii-id"; + phy-handle =3D <ðphy1>; + fsl,magic-packet; + status =3D "okay"; + + mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + + ethphy1: ethernet-phy@0 { + pinctrl-0 =3D <&pinctrl_ethphy1>; + pinctrl-names =3D "default"; + reg =3D <0>; + interrupt-parent =3D <&gpio3>; + interrupts =3D <19 IRQ_TYPE_LEVEL_LOW>; + micrel,led-mode =3D <0>; + reset-gpios =3D <&gpio3 20 GPIO_ACTIVE_LOW>; + reset-assert-us =3D <1000>; + reset-deassert-us =3D <1000>; + }; + }; +}; + +&i2c1 { + clock-frequency =3D <400000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_i2c1>; + status =3D "okay"; + + pmic@25 { + compatible =3D "nxp,pca9450c"; + reg =3D <0x25>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_pmic>; + interrupt-parent =3D <&gpio1>; + interrupts =3D <3 IRQ_TYPE_LEVEL_LOW>; + + regulators { + BUCK1 { + regulator-name =3D "BUCK1"; + regulator-min-microvolt =3D <720000>; + regulator-max-microvolt =3D <1000000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay =3D <3125>; + }; + + reg_arm: BUCK2 { + regulator-name =3D "BUCK2"; + regulator-min-microvolt =3D <720000>; + regulator-max-microvolt =3D <1025000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay =3D <3125>; + nxp,dvs-run-voltage =3D <950000>; + nxp,dvs-standby-voltage =3D <850000>; + }; + + BUCK4 { + regulator-name =3D "BUCK4"; + regulator-min-microvolt =3D <3000000>; + regulator-max-microvolt =3D <3600000>; + regulator-boot-on; + regulator-always-on; + }; + + BUCK5 { + regulator-name =3D "BUCK5"; + regulator-min-microvolt =3D <1650000>; + regulator-max-microvolt =3D <1950000>; + regulator-boot-on; + regulator-always-on; + }; + + BUCK6 { + regulator-name =3D "BUCK6"; + regulator-min-microvolt =3D <1045000>; + regulator-max-microvolt =3D <1155000>; + regulator-boot-on; + regulator-always-on; + }; + + LDO1 { + regulator-name =3D "LDO1"; + regulator-min-microvolt =3D <1650000>; + regulator-max-microvolt =3D <1950000>; + regulator-boot-on; + regulator-always-on; + }; + + LDO3 { + regulator-name =3D "LDO3"; + regulator-min-microvolt =3D <1710000>; + regulator-max-microvolt =3D <1890000>; + regulator-boot-on; + regulator-always-on; + }; + + LDO4 { + regulator-name =3D "LDO4"; + regulator-min-microvolt =3D <850000>; + regulator-max-microvolt =3D <950000>; + regulator-boot-on; + regulator-always-on; + }; + + LDO5 { + regulator-name =3D "LDO5"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&i2c2 { + clock-frequency =3D <400000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_i2c2>; + status =3D "okay"; + + rtc: rtc@68 { + compatible =3D "dallas,ds1341"; + reg =3D <0x68>; + }; +}; + +&pwm4 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_pwm4>; + pwm-gpios =3D <&gpio5 2 GPIO_ACTIVE_HIGH>; + status =3D "okay"; +}; + +&uart2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart2>; + status =3D "okay"; +}; + +&usb3_phy1 { + vbus-supply =3D <®_usb_host>; + status =3D "okay"; +}; + +&usb3_1 { + status =3D "okay"; +}; + +&usb_dwc3_1 { + pinctrl-names =3D "default"; + dr_mode =3D "host"; + status =3D "okay"; +}; + +&usdhc3 { + assigned-clocks =3D <&clk IMX8MP_CLK_USDHC3>; + assigned-clock-rates =3D <400000000>; + pinctrl-names =3D "default", "state_100mhz", "state_200mhz"; + pinctrl-0 =3D <&pinctrl_usdhc3>; + pinctrl-1 =3D <&pinctrl_usdhc3_100mhz>; + pinctrl-2 =3D <&pinctrl_usdhc3_200mhz>; + bus-width =3D <8>; + non-removable; + status =3D "okay"; +}; + +&wdog1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_wdog>; + fsl,ext-reset-output; + status =3D "okay"; +}; + +&iomuxc { + pinctrl_eqos: eqosgrp { + fsl,pins =3D < + MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 + MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2 + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90 + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90 + MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90 + MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90 + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90 + MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90 + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16 + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16 + MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16 + MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16 + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16 + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16 + >; + }; + + pinctrl_ethphy0: ethphy0grp { + fsl,pins =3D < + MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x10 + MX8MP_IOMUXC_SAI5_RXD1__GPIO3_IO22 0x10 + >; + }; + + pinctrl_ethphy1: ethphy1grp { + fsl,pins =3D < + MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x10 + MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x10 + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins =3D < + MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x2 + MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x2 + MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90 + MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90 + MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90 + MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90 + MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90 + MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90 + MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16 + MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16 + MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16 + MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16 + MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16 + MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16 + >; + }; + + pinctrl_gpio_keys: gpiokeysgrp { + fsl,pins =3D < + MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x80 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins =3D < + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins =3D < + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins =3D < + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins =3D < + MX8MP_IOMUXC_SAI3_MCLK__PWM4_OUT 0x102 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins =3D < + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x0 + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x0 + >; + }; + + pinctrl_usb_host_vbus: usb1grp { + fsl,pins =3D < + MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins =3D < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins =3D < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins =3D < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins =3D < + MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166 + >; + }; +}; --=20 2.43.0