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Tue, 17 Sep 2024 13:24:50 GMT Received: from smtpav04.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 77D5A20043; Tue, 17 Sep 2024 13:24:50 +0000 (GMT) Received: from smtpav04.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id BA8D520040; Tue, 17 Sep 2024 13:24:48 +0000 (GMT) Received: from ltc-wspoon17.aus.stglabs.ibm.com (unknown [9.3.101.49]) by smtpav04.fra02v.mail.ibm.com (Postfix) with ESMTP; Tue, 17 Sep 2024 13:24:48 +0000 (GMT) From: Narayana Murty N To: linuxppc-dev@lists.ozlabs.org, mpe@ellerman.id.au, linux-kernel@vger.kernel.org Cc: mahesh@linux.ibm.com, oohall@gmail.com, npiggin@gmail.com, christophe.leroy@csgroup.eu, naveen@kernel.org, vaibhav@linux.ibm.com, ganeshgr@linux.ibm.com, sbhat@linux.ibm.com Subject: [PATCH] powerpc/pseries/eeh: move pseries_eeh_err_inject() outside CONFIG_DEBUG_FS block Date: Tue, 17 Sep 2024 09:24:45 -0400 Message-Id: <20240917132445.3868016-1-nnmlinux@linux.ibm.com> X-Mailer: git-send-email 2.39.2 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: FtQ074m2Rfo7OijiNExjd6AeztopPfs4 X-Proofpoint-GUID: 0axfa_oxoiyn_dZJi0weoiAiqHLdxOI1 Content-Transfer-Encoding: quoted-printable X-Proofpoint-UnRewURL: 0 URL was un-rewritten Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1051,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-17_05,2024-09-16_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 mlxlogscore=999 adultscore=0 phishscore=0 spamscore=0 lowpriorityscore=0 clxscore=1015 bulkscore=0 suspectscore=0 mlxscore=0 impostorscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2408220000 definitions=main-2409170094 Content-Type: text/plain; charset="utf-8" Makes pseries_eeh_err_inject() available even when debugfs is disabled (CONFIG_DEBUG_FS=3Dn). It moves eeh_debugfs_break_device() and eeh_pe_inject_mmio_error() out of the CONFIG_DEBUG_FS block and renames it as eeh_break_device(). Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202409170509.VWC6jadC-lkp@int= el.com/ Fixes: b0e2b828dfca ("powerpc/pseries/eeh: Fix pseries_eeh_err_inject") Signed-off-by: Narayana Murty N Reviewed-by: Ritesh Harjani (IBM) --- arch/powerpc/kernel/eeh.c | 198 +++++++++++++++++++------------------- 1 file changed, 99 insertions(+), 99 deletions(-) diff --git a/arch/powerpc/kernel/eeh.c b/arch/powerpc/kernel/eeh.c index 49ab11a287a3..0fe25e907ea6 100644 --- a/arch/powerpc/kernel/eeh.c +++ b/arch/powerpc/kernel/eeh.c @@ -1574,6 +1574,104 @@ static int proc_eeh_show(struct seq_file *m, void *= v) } #endif /* CONFIG_PROC_FS */ =20 +static int eeh_break_device(struct pci_dev *pdev) +{ + struct resource *bar =3D NULL; + void __iomem *mapped; + u16 old, bit; + int i, pos; + + /* Do we have an MMIO BAR to disable? */ + for (i =3D 0; i <=3D PCI_STD_RESOURCE_END; i++) { + struct resource *r =3D &pdev->resource[i]; + + if (!r->flags || !r->start) + continue; + if (r->flags & IORESOURCE_IO) + continue; + if (r->flags & IORESOURCE_UNSET) + continue; + + bar =3D r; + break; + } + + if (!bar) { + pci_err(pdev, "Unable to find Memory BAR to cause EEH with\n"); + return -ENXIO; + } + + pci_err(pdev, "Going to break: %pR\n", bar); + + if (pdev->is_virtfn) { +#ifndef CONFIG_PCI_IOV + return -ENXIO; +#else + /* + * VFs don't have a per-function COMMAND register, so the best + * we can do is clear the Memory Space Enable bit in the PF's + * SRIOV control reg. + * + * Unfortunately, this requires that we have a PF (i.e doesn't + * work for a passed-through VF) and it has the potential side + * effect of also causing an EEH on every other VF under the + * PF. Oh well. + */ + pdev =3D pdev->physfn; + if (!pdev) + return -ENXIO; /* passed through VFs have no PF */ + + pos =3D pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV); + pos +=3D PCI_SRIOV_CTRL; + bit =3D PCI_SRIOV_CTRL_MSE; +#endif /* !CONFIG_PCI_IOV */ + } else { + bit =3D PCI_COMMAND_MEMORY; + pos =3D PCI_COMMAND; + } + + /* + * Process here is: + * + * 1. Disable Memory space. + * + * 2. Perform an MMIO to the device. This should result in an error + * (CA / UR) being raised by the device which results in an EEH + * PE freeze. Using the in_8() accessor skips the eeh detection hook + * so the freeze hook so the EEH Detection machinery won't be + * triggered here. This is to match the usual behaviour of EEH + * where the HW will asynchronously freeze a PE and it's up to + * the kernel to notice and deal with it. + * + * 3. Turn Memory space back on. This is more important for VFs + * since recovery will probably fail if we don't. For normal + * the COMMAND register is reset as a part of re-initialising + * the device. + * + * Breaking stuff is the point so who cares if it's racy ;) + */ + pci_read_config_word(pdev, pos, &old); + + mapped =3D ioremap(bar->start, PAGE_SIZE); + if (!mapped) { + pci_err(pdev, "Unable to map MMIO BAR %pR\n", bar); + return -ENXIO; + } + + pci_write_config_word(pdev, pos, old & ~bit); + in_8(mapped); + pci_write_config_word(pdev, pos, old); + + iounmap(mapped); + + return 0; +} + +int eeh_pe_inject_mmio_error(struct pci_dev *pdev) +{ + return eeh_break_device(pdev); +} + #ifdef CONFIG_DEBUG_FS =20 =20 @@ -1727,99 +1825,6 @@ static const struct file_operations eeh_dev_check_fo= ps =3D { .read =3D eeh_debugfs_dev_usage, }; =20 -static int eeh_debugfs_break_device(struct pci_dev *pdev) -{ - struct resource *bar =3D NULL; - void __iomem *mapped; - u16 old, bit; - int i, pos; - - /* Do we have an MMIO BAR to disable? */ - for (i =3D 0; i <=3D PCI_STD_RESOURCE_END; i++) { - struct resource *r =3D &pdev->resource[i]; - - if (!r->flags || !r->start) - continue; - if (r->flags & IORESOURCE_IO) - continue; - if (r->flags & IORESOURCE_UNSET) - continue; - - bar =3D r; - break; - } - - if (!bar) { - pci_err(pdev, "Unable to find Memory BAR to cause EEH with\n"); - return -ENXIO; - } - - pci_err(pdev, "Going to break: %pR\n", bar); - - if (pdev->is_virtfn) { -#ifndef CONFIG_PCI_IOV - return -ENXIO; -#else - /* - * VFs don't have a per-function COMMAND register, so the best - * we can do is clear the Memory Space Enable bit in the PF's - * SRIOV control reg. - * - * Unfortunately, this requires that we have a PF (i.e doesn't - * work for a passed-through VF) and it has the potential side - * effect of also causing an EEH on every other VF under the - * PF. Oh well. - */ - pdev =3D pdev->physfn; - if (!pdev) - return -ENXIO; /* passed through VFs have no PF */ - - pos =3D pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV); - pos +=3D PCI_SRIOV_CTRL; - bit =3D PCI_SRIOV_CTRL_MSE; -#endif /* !CONFIG_PCI_IOV */ - } else { - bit =3D PCI_COMMAND_MEMORY; - pos =3D PCI_COMMAND; - } - - /* - * Process here is: - * - * 1. Disable Memory space. - * - * 2. Perform an MMIO to the device. This should result in an error - * (CA / UR) being raised by the device which results in an EEH - * PE freeze. Using the in_8() accessor skips the eeh detection hook - * so the freeze hook so the EEH Detection machinery won't be - * triggered here. This is to match the usual behaviour of EEH - * where the HW will asynchronously freeze a PE and it's up to - * the kernel to notice and deal with it. - * - * 3. Turn Memory space back on. This is more important for VFs - * since recovery will probably fail if we don't. For normal - * the COMMAND register is reset as a part of re-initialising - * the device. - * - * Breaking stuff is the point so who cares if it's racy ;) - */ - pci_read_config_word(pdev, pos, &old); - - mapped =3D ioremap(bar->start, PAGE_SIZE); - if (!mapped) { - pci_err(pdev, "Unable to map MMIO BAR %pR\n", bar); - return -ENXIO; - } - - pci_write_config_word(pdev, pos, old & ~bit); - in_8(mapped); - pci_write_config_word(pdev, pos, old); - - iounmap(mapped); - - return 0; -} - static ssize_t eeh_dev_break_write(struct file *filp, const char __user *user_buf, size_t count, loff_t *ppos) @@ -1831,7 +1836,7 @@ static ssize_t eeh_dev_break_write(struct file *filp, if (IS_ERR(pdev)) return PTR_ERR(pdev); =20 - ret =3D eeh_debugfs_break_device(pdev); + ret =3D eeh_break_device(pdev); pci_dev_put(pdev); =20 if (ret < 0) @@ -1847,11 +1852,6 @@ static const struct file_operations eeh_dev_break_fo= ps =3D { .read =3D eeh_debugfs_dev_usage, }; =20 -int eeh_pe_inject_mmio_error(struct pci_dev *pdev) -{ - return eeh_debugfs_break_device(pdev); -} - static ssize_t eeh_dev_can_recover(struct file *filp, const char __user *user_buf, size_t count, loff_t *ppos) --=20 2.39.2