From nobody Fri Nov 29 16:49:54 2024 Received: from chessie.everett.org (chessie.fmt1.pfcs.com [66.220.13.234]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 2C65433998; Tue, 17 Sep 2024 09:50:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=66.220.13.234 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726566645; cv=none; b=FbqyT8nAqCoDPa9jG5zRag6xGVlsUuaq/EOZ8h3CO9S8PQjF2KCguufMPDTwPLc9q5RKwH83g0Vwl/QeTYU/rwTTHuFpdb8/xzhAPkAYm1pLC/rczlx/TbSXElsZb6XND7MYSWHOvt3KkK46kod0T7NNEHtXxapcDriOv3rrSa8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726566645; c=relaxed/simple; bh=sktSXyAN1GCJtuklMPBB+KGenD0/dlyP/YcC3hPG+Jk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=oUEGmmgjIODPJ+1nxLyvDFLxaIPk68hJvbujHVptYnOIetQnrvZq4eSj4m93XpX6Xy6s6jaSk2Y2bSjaEDkR0WAxHbBwTstxEr2slGKlt/hXV1uF9MXRwWjuTX44Olld1S4RuT3Q7j60n8i32b40HTT76ghk0r0sQm2Y57rgy7Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=nwtime.org; spf=pass smtp.mailfrom=nwtime.org; arc=none smtp.client-ip=66.220.13.234 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=nwtime.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nwtime.org Received: from localhost.localdomain (unknown [31.16.248.93]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by chessie.everett.org (Postfix) with ESMTPSA id 4X7H8S1Ls9zMR5Q; Tue, 17 Sep 2024 09:50:32 +0000 (UTC) From: Erez Geva To: linux-mtd@lists.infradead.org, Tudor Ambarus , Pratyush Yadav , Michael Walle Cc: linux-kernel@vger.kernel.org, Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , devicetree@vger.kernel.org, Rob Herring , Krzysztof Kozlowski , Conor Dooley , Esben Haabendal , Erez Geva Subject: [PATCH v4 1/5] mtd: spi-nor: core: add manufacturer flags Date: Tue, 17 Sep 2024 11:49:52 +0200 Message-Id: <20240917094956.437078-2-erezgeva@nwtime.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20240917094956.437078-1-erezgeva@nwtime.org> References: <20240917094956.437078-1-erezgeva@nwtime.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Erez Geva Add flag for always trying reading SFDP: Some vendors reuse all JEDEC IDs on manufacture table with new chips that support SFDP. Add flag for reading OTP parameters from device tree. Some vendors reuse JEDEC IDs with several chips with different OTP parameters. Alternatively we read parameters from SFDP. But the OTP parameters are absent from the SFDP. So there is not other way but to add the OTP parameters in the device tree. In this patch series we use the new flags with Macronix. Signed-off-by: Erez Geva --- drivers/mtd/spi-nor/core.c | 36 ++++++++++++++++++++++++++++++----- drivers/mtd/spi-nor/core.h | 7 ++++++- drivers/mtd/spi-nor/otp.c | 6 +++--- drivers/mtd/spi-nor/winbond.c | 2 +- 4 files changed, 41 insertions(+), 10 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index e0c4efc424f4..23e3d5720ec0 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -2891,10 +2891,11 @@ static void spi_nor_init_params_deprecated(struct s= pi_nor *nor) =20 spi_nor_manufacturer_init_params(nor); =20 - if (nor->info->no_sfdp_flags & (SPI_NOR_DUAL_READ | - SPI_NOR_QUAD_READ | - SPI_NOR_OCTAL_READ | - SPI_NOR_OCTAL_DTR_READ)) + if ((nor->info->no_sfdp_flags & (SPI_NOR_DUAL_READ | + SPI_NOR_QUAD_READ | + SPI_NOR_OCTAL_READ | + SPI_NOR_OCTAL_DTR_READ)) || + nor->manufacturer->flags & SPI_NOR_MANUFACT_TRY_SFDP) spi_nor_sfdp_init_params_deprecated(nor); } =20 @@ -2911,7 +2912,32 @@ static void spi_nor_init_default_params(struct spi_n= or *nor) struct device_node *np =3D spi_nor_get_flash_node(nor); =20 params->quad_enable =3D spi_nor_sr2_bit1_quad_enable; - params->otp.org =3D info->otp; + memset(¶ms->otp.org, 0, sizeof(struct spi_nor_otp_organization)); + if (info->otp) { + memcpy(¶ms->otp.org, info->otp, sizeof(struct spi_nor_otp_organizati= on)); + } else if (nor->manufacturer->flags & SPI_NOR_MANUFACT_DT_OTP) { + /* Check for OTP information on device tree */ + u32 n_regions, len; + + if (!of_property_read_u32(np, "opt_n_regions", &n_regions) && + n_regions > 0 && + !of_property_read_u32(np, "otp_len", &len) && + len > 0) { + u32 base, offset =3D 0; + + if (n_regions > 1) { + /* If offset is not defined use length as offset */ + if (of_property_read_u32(np, "otp_offset", &offset)) + offset =3D len; + } + if (of_property_read_u32(np, "otp_base", &base)) + base =3D 0; + params->otp.org.n_regions =3D n_regions; + params->otp.org.offset =3D offset; + params->otp.org.base =3D base; + params->otp.org.len =3D len; + } + } =20 /* Default to 16-bit Write Status (01h) Command */ nor->flags |=3D SNOR_F_HAS_16BIT_SR; diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index 1516b6d0dc37..c862e42c844f 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -326,7 +326,7 @@ struct spi_nor_otp_ops { * @ops: OTP access ops */ struct spi_nor_otp { - const struct spi_nor_otp_organization *org; + struct spi_nor_otp_organization org; const struct spi_nor_otp_ops *ops; }; =20 @@ -560,12 +560,17 @@ struct flash_info { * @parts: array of parts supported by this manufacturer * @nparts: number of entries in the parts array * @fixups: hooks called at various points in time during spi_nor_scan() + * @flags: manufacturer flags */ struct spi_nor_manufacturer { const char *name; const struct flash_info *parts; unsigned int nparts; const struct spi_nor_fixups *fixups; + + u8 flags; +#define SPI_NOR_MANUFACT_TRY_SFDP BIT(0) +#define SPI_NOR_MANUFACT_DT_OTP BIT(0) }; =20 /** diff --git a/drivers/mtd/spi-nor/otp.c b/drivers/mtd/spi-nor/otp.c index 9a729aa3452d..ffb7ffeb9030 100644 --- a/drivers/mtd/spi-nor/otp.c +++ b/drivers/mtd/spi-nor/otp.c @@ -11,8 +11,8 @@ =20 #include "core.h" =20 -#define spi_nor_otp_region_len(nor) ((nor)->params->otp.org->len) -#define spi_nor_otp_n_regions(nor) ((nor)->params->otp.org->n_regions) +#define spi_nor_otp_region_len(nor) ((nor)->params->otp.org.len) +#define spi_nor_otp_n_regions(nor) ((nor)->params->otp.org.n_regions) =20 /** * spi_nor_otp_read_secr() - read security register @@ -222,7 +222,7 @@ int spi_nor_otp_is_locked_sr2(struct spi_nor *nor, unsi= gned int region) =20 static loff_t spi_nor_otp_region_start(const struct spi_nor *nor, unsigned= int region) { - const struct spi_nor_otp_organization *org =3D nor->params->otp.org; + const struct spi_nor_otp_organization *org =3D &nor->params->otp.org; =20 return org->base + region * org->offset; } diff --git a/drivers/mtd/spi-nor/winbond.c b/drivers/mtd/spi-nor/winbond.c index e065e4fd42a3..15af62aacc9a 100644 --- a/drivers/mtd/spi-nor/winbond.c +++ b/drivers/mtd/spi-nor/winbond.c @@ -307,7 +307,7 @@ static int winbond_nor_late_init(struct spi_nor *nor) { struct spi_nor_flash_parameter *params =3D nor->params; =20 - if (params->otp.org) + if (params->otp.org.n_regions) params->otp.ops =3D &winbond_nor_otp_ops; =20 /* --=20 2.39.5 From nobody Fri Nov 29 16:49:54 2024 Received: from chessie.everett.org (chessie.fmt1.pfcs.com [66.220.13.234]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 7AFD414831C; Tue, 17 Sep 2024 09:50:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=66.220.13.234 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726566647; cv=none; b=sPK5zq/9xkxzexlOVCplQ5yEDptSTQjoueaxxCeth49OVbd29yjKlArS+DR3HJUdGPBglicuutP7TlmyIgmjm48eyasomVbYpyjjW63Ump5KeMmZrX5ZNP7FYsPqBiBDG0X6wQZ9tDUXys5Z6JtFwnxXW+7x3S93ZRJ7AeW3g4k= ARC-Message-Signature: i=1; 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Tue, 17 Sep 2024 09:50:35 +0000 (UTC) From: Erez Geva To: linux-mtd@lists.infradead.org, Tudor Ambarus , Pratyush Yadav , Michael Walle Cc: linux-kernel@vger.kernel.org, Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , devicetree@vger.kernel.org, Rob Herring , Krzysztof Kozlowski , Conor Dooley , Esben Haabendal , Erez Geva Subject: [PATCH v4 2/5] mtd: spi-nor: core: add generic functions Date: Tue, 17 Sep 2024 11:49:53 +0200 Message-Id: <20240917094956.437078-3-erezgeva@nwtime.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20240917094956.437078-1-erezgeva@nwtime.org> References: <20240917094956.437078-1-erezgeva@nwtime.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Erez Geva Create a new internal function, spi_nor_send_cmd_internal() to reduce duplicate code. Add generic functions for use by vendor callbacks. The functions contain dispatching for using SPIMEM or using an SPI controller. It is better to leave this kind of dispatcher, out side of vendor specific code. In this patch series we use the new functions in Macronix new OTP callbacks. The new added functions: - Send an opcode without address or data. - Read a register value. - Write a register value. Signed-off-by: Erez Geva --- drivers/mtd/spi-nor/core.c | 130 +++++++++++++++++++++++++++---------- drivers/mtd/spi-nor/core.h | 27 +------- 2 files changed, 99 insertions(+), 58 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 23e3d5720ec0..47d5d21d7291 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -354,53 +354,134 @@ int spi_nor_write_any_volatile_reg(struct spi_nor *n= or, struct spi_mem_op *op, } =20 /** - * spi_nor_write_enable() - Set write enable latch with Write Enable comma= nd. + * spi_nor_send_cmd_internal() - Send instruction without address or data = to the chip. * @nor: pointer to 'struct spi_nor'. + * @opcode: Command to send * * Return: 0 on success, -errno otherwise. */ -int spi_nor_write_enable(struct spi_nor *nor) +static inline int spi_nor_send_cmd_internal(struct spi_nor *nor, u8 opcode) { int ret; =20 if (nor->spimem) { - struct spi_mem_op op =3D SPI_NOR_WREN_OP; + struct spi_mem_op op =3D SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 0), + SPI_MEM_OP_NO_ADDR, + SPI_MEM_OP_NO_DUMMY, + SPI_MEM_OP_NO_DATA); =20 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); =20 ret =3D spi_mem_exec_op(nor->spimem, &op); } else { - ret =3D spi_nor_controller_ops_write_reg(nor, SPINOR_OP_WREN, - NULL, 0); + ret =3D spi_nor_controller_ops_write_reg(nor, opcode, NULL, 0); } =20 - if (ret) - dev_dbg(nor->dev, "error %d on Write Enable\n", ret); + return ret; +} + +/** + * spi_nor_send_cmd() - Send instruction without address or data to the ch= ip. + * @nor: pointer to 'struct spi_nor'. + * @opcode: Command to send + * + * Return: 0 on success, -errno otherwise. + */ +int spi_nor_send_cmd(struct spi_nor *nor, u8 opcode) +{ + int ret; + + ret =3D spi_nor_send_cmd_internal(nor, opcode); =20 return ret; } =20 /** - * spi_nor_write_disable() - Send Write Disable instruction to the chip. + * spi_nor_read_reg() - Send instruction without address or data to the ch= ip. * @nor: pointer to 'struct spi_nor'. + * @opcode: Command to send + * @len: register value length * * Return: 0 on success, -errno otherwise. */ -int spi_nor_write_disable(struct spi_nor *nor) +int spi_nor_read_reg(struct spi_nor *nor, u8 opcode, size_t len) { int ret; =20 if (nor->spimem) { - struct spi_mem_op op =3D SPI_NOR_WRDI_OP; + struct spi_mem_op op =3D SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 0), + SPI_MEM_OP_NO_ADDR, + SPI_MEM_OP_NO_DUMMY, + SPI_MEM_OP_DATA_IN(len, nor->bouncebuf, 0)); =20 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); =20 ret =3D spi_mem_exec_op(nor->spimem, &op); } else { - ret =3D spi_nor_controller_ops_write_reg(nor, SPINOR_OP_WRDI, - NULL, 0); + ret =3D spi_nor_controller_ops_read_reg(nor, opcode, nor->bouncebuf, len= ); } =20 + return ret; +} + +/* + * spi_nor_write_reg() - Send instruction without address or data to the c= hip. + * @nor: pointer to 'struct spi_nor'. + * @opcode: Command to send + * @len: register value length + * + * Return: 0 on success, -errno otherwise. + */ +int spi_nor_write_reg(struct spi_nor *nor, u8 opcode, size_t len) +{ + int ret; + + if (nor->spimem) { + struct spi_mem_op op =3D SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 0), + SPI_MEM_OP_NO_ADDR, + SPI_MEM_OP_NO_DUMMY, + SPI_MEM_OP_DATA_OUT(len, nor->bouncebuf, 0)); + + spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); + + ret =3D spi_mem_exec_op(nor->spimem, &op); + } else { + ret =3D spi_nor_controller_ops_write_reg(nor, opcode, nor->bouncebuf, le= n); + } + + return ret; +} + +/** + * spi_nor_write_enable() - Set write enable latch with Write Enable comma= nd. + * @nor: pointer to 'struct spi_nor'. + * + * Return: 0 on success, -errno otherwise. + */ +int spi_nor_write_enable(struct spi_nor *nor) +{ + int ret; + + ret =3D spi_nor_send_cmd_internal(nor, SPINOR_OP_WREN); + + if (ret) + dev_dbg(nor->dev, "error %d on Write Enable\n", ret); + + return ret; +} + +/** + * spi_nor_write_disable() - Send Write Disable instruction to the chip. + * @nor: pointer to 'struct spi_nor'. + * + * Return: 0 on success, -errno otherwise. + */ +int spi_nor_write_disable(struct spi_nor *nor) +{ + int ret; + + ret =3D spi_nor_send_cmd_internal(nor, SPINOR_OP_WRDI); + if (ret) dev_dbg(nor->dev, "error %d on Write Disable\n", ret); =20 @@ -521,18 +602,8 @@ int spi_nor_set_4byte_addr_mode_en4b_ex4b(struct spi_n= or *nor, bool enable) { int ret; =20 - if (nor->spimem) { - struct spi_mem_op op =3D SPI_NOR_EN4B_EX4B_OP(enable); - - spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); - - ret =3D spi_mem_exec_op(nor->spimem, &op); - } else { - ret =3D spi_nor_controller_ops_write_reg(nor, - enable ? SPINOR_OP_EN4B : - SPINOR_OP_EX4B, - NULL, 0); - } + ret =3D spi_nor_send_cmd_internal(nor, enable ? SPINOR_OP_EN4B : + SPINOR_OP_EX4B); =20 if (ret) dev_dbg(nor->dev, "error %d setting 4-byte mode\n", ret); @@ -765,16 +836,7 @@ int spi_nor_global_block_unlock(struct spi_nor *nor) if (ret) return ret; =20 - if (nor->spimem) { - struct spi_mem_op op =3D SPI_NOR_GBULK_OP; - - spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); - - ret =3D spi_mem_exec_op(nor->spimem, &op); - } else { - ret =3D spi_nor_controller_ops_write_reg(nor, SPINOR_OP_GBULK, - NULL, 0); - } + ret =3D spi_nor_send_cmd_internal(nor, SPINOR_OP_GBULK); =20 if (ret) { dev_dbg(nor->dev, "error %d on Global Block Unlock\n", ret); diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index c862e42c844f..615c399dfb6e 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -25,18 +25,6 @@ SPI_MEM_OP_DUMMY(ndummy, 0), \ SPI_MEM_OP_DATA_IN(len, buf, 0)) =20 -#define SPI_NOR_WREN_OP \ - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WREN, 0), \ - SPI_MEM_OP_NO_ADDR, \ - SPI_MEM_OP_NO_DUMMY, \ - SPI_MEM_OP_NO_DATA) - -#define SPI_NOR_WRDI_OP \ - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRDI, 0), \ - SPI_MEM_OP_NO_ADDR, \ - SPI_MEM_OP_NO_DUMMY, \ - SPI_MEM_OP_NO_DATA) - #define SPI_NOR_RDSR_OP(buf) \ SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDSR, 0), \ SPI_MEM_OP_NO_ADDR, \ @@ -67,24 +55,12 @@ SPI_MEM_OP_NO_DUMMY, \ SPI_MEM_OP_DATA_IN(1, buf, 0)) =20 -#define SPI_NOR_EN4B_EX4B_OP(enable) \ - SPI_MEM_OP(SPI_MEM_OP_CMD(enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B, 0), \ - SPI_MEM_OP_NO_ADDR, \ - SPI_MEM_OP_NO_DUMMY, \ - SPI_MEM_OP_NO_DATA) - #define SPI_NOR_BRWR_OP(buf) \ SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_BRWR, 0), \ SPI_MEM_OP_NO_ADDR, \ SPI_MEM_OP_NO_DUMMY, \ SPI_MEM_OP_DATA_OUT(1, buf, 0)) =20 -#define SPI_NOR_GBULK_OP \ - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_GBULK, 0), \ - SPI_MEM_OP_NO_ADDR, \ - SPI_MEM_OP_NO_DUMMY, \ - SPI_MEM_OP_NO_DATA) - #define SPI_NOR_DIE_ERASE_OP(opcode, addr_nbytes, addr, dice) \ SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 0), \ SPI_MEM_OP_ADDR(dice ? addr_nbytes : 0, addr, 0), \ @@ -604,6 +580,9 @@ extern const struct attribute_group *spi_nor_sysfs_grou= ps[]; void spi_nor_spimem_setup_op(const struct spi_nor *nor, struct spi_mem_op *op, const enum spi_nor_protocol proto); +int spi_nor_send_cmd(struct spi_nor *nor, u8 opcode); +int spi_nor_read_reg(struct spi_nor *nor, u8 opcode, size_t len); +int spi_nor_write_reg(struct spi_nor *nor, u8 opcode, size_t len); int spi_nor_write_enable(struct spi_nor *nor); int spi_nor_write_disable(struct spi_nor *nor); int spi_nor_set_4byte_addr_mode_en4b_ex4b(struct spi_nor *nor, bool enable= ); --=20 2.39.5 From nobody Fri Nov 29 16:49:54 2024 Received: from chessie.everett.org (chessie.fmt1.pfcs.com [66.220.13.234]) by smtp.subspace.kernel.org (Postfix) with ESMTP id F382415F41B; Tue, 17 Sep 2024 09:50:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=66.220.13.234 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726566649; cv=none; b=Q0w6Tk0Xa3qZVdu6tcodmNWa+NCsqS6eKKiY+0US12c4n6s/z+aELQWrWwsTzUbQ1Ul1TUqsWySdRcOBucjo1PPMYBedynphuT6Txgu3tLso0zPBeZyUAvPkvgXjWcFxcQOMmzR4igsKNVYBQGBDT0BlxrC1ux3vqtqK5inHbLc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726566649; c=relaxed/simple; bh=guGl3BlrqNv+pV6KuIUaBuZzzAE6v1eurl18wx/Xh4E=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=j76pN80+TwfNRvWoK7GpsIgR1wtwVF08h7hXZhv/bRoqq033Z3OHdhHBGk6gpSwKb5biF3aiTWRgEk2WBUou6fiPUv2SLBcZnkVBpnyFRRJWt63rU0/P1rmeREYPVxdxc+vBkJkpHhPdFX9DtidQaxDGkLGEmpVNjeOYyKgRvtw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=nwtime.org; spf=pass smtp.mailfrom=nwtime.org; arc=none smtp.client-ip=66.220.13.234 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=nwtime.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nwtime.org Received: from localhost.localdomain (unknown [31.16.248.93]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by chessie.everett.org (Postfix) with ESMTPSA id 4X7H8Z2M2lzMR5s; Tue, 17 Sep 2024 09:50:38 +0000 (UTC) From: Erez Geva To: linux-mtd@lists.infradead.org, Tudor Ambarus , Pratyush Yadav , Michael Walle Cc: linux-kernel@vger.kernel.org, Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , devicetree@vger.kernel.org, Rob Herring , Krzysztof Kozlowski , Conor Dooley , Esben Haabendal , Erez Geva Subject: [PATCH v4 3/5] dt-bindings: mtd: spi-nor: add OTP parameters Date: Tue, 17 Sep 2024 11:49:54 +0200 Message-Id: <20240917094956.437078-4-erezgeva@nwtime.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20240917094956.437078-1-erezgeva@nwtime.org> References: <20240917094956.437078-1-erezgeva@nwtime.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Erez Geva Some flash devices need OTP parameters in device tree. As we can not deduce the parameters based on JEDEC ID or SFDP. Signed-off-by: Erez Geva --- .../bindings/mtd/jedec,spi-nor.yaml | 37 +++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml b/Doc= umentation/devicetree/bindings/mtd/jedec,spi-nor.yaml index 6e3afb42926e..d502b7fab2ce 100644 --- a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml +++ b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml @@ -90,6 +90,43 @@ properties: the SRWD bit while writing the status register. WP# signal hard stra= pped to GND can be a valid use case. =20 + opt_n_regions: + type: u32 + description: + Some flash devices need OTP parameters in the device tree. + As we can not deduce the parameters based on JEDEC ID or SFDP. + This parameter indicates the number of OTP regions. + The value must be larger than 1 and mandatory for OTP. + + otp_len: + type: u32 + description: + Some flash devices need OTP parameters in the device tree. + As we can not deduce the parameters based on JEDEC ID or SFDP. + This parameter indicates the size (length) in bytes of an OTP region. + Currently the driver supports symmetric OTP, + which means all regions must use the same size. + The value must be positive and mandatory for OTP. + + otp_offset: + type: u32 + description: + Some flash devices need OTP parameters in the device tree. + As we can not deduce the parameters based on JEDEC ID or SFDP. + This parameter indicates the offset in bytes of + an OTP region relative to its previous. + User can omit it if the offset equals the length. + Or in case we have a single OTP region. + + otp_base: + type: u32 + description: + Some flash devices need OTP parameters in the device tree. + As we can not deduce the parameters based on JEDEC ID or SFDP. + This parameter indicates the base in bytes of the first OTP region. + User can omit it if the base is zero. + I.e. the address of the first OTP region starts from 0. + reset-gpios: description: A GPIO line connected to the RESET (active low) signal of the device. --=20 2.39.5 From nobody Fri Nov 29 16:49:54 2024 Received: from chessie.everett.org (chessie.fmt1.pfcs.com [66.220.13.234]) by smtp.subspace.kernel.org (Postfix) with ESMTP id A17AD165EED; Tue, 17 Sep 2024 09:50:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=66.220.13.234 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726566654; cv=none; b=j7qUrIoSXGs4FIEwRBK8tJ4j7ZvZFsPw0ayC2s4eihi+h9Ctr2qOdxEuLbD6fUEbzcAenAZniWRU3Vn1dUJo3uDrGJTRkviUg0EzdMIWZSeS4iXMHT1bLuowttVrb7rfL7Ly50zvJHDajLmd55CEV8LGdvfogPJ3pjbesvuZrUs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726566654; c=relaxed/simple; bh=9hsifZHo+jNzG7HnFv2SlQq6WgrK3ateaOFRSVBxWjc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ssEWrGDt8AwW1KXlvWD3N1yza6cHGBXWXrLd6N4f+P1VHSTqyq5cIbQ4ouQZlMet90yL08Go0dEXW+EugBXnPb/cvaZkYy98S7lwNAQbJFZVmUzpoUbXI88eZw5vUZTBbWWLApOc7k4QOZNYVfJm7IGQF8nJ+f7sSCPOabS9lpY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=nwtime.org; spf=pass smtp.mailfrom=nwtime.org; arc=none smtp.client-ip=66.220.13.234 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=nwtime.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nwtime.org Received: from localhost.localdomain (unknown [31.16.248.93]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by chessie.everett.org (Postfix) with ESMTPSA id 4X7H8d2MjQzMR62; Tue, 17 Sep 2024 09:50:41 +0000 (UTC) From: Erez Geva To: linux-mtd@lists.infradead.org, Tudor Ambarus , Pratyush Yadav , Michael Walle Cc: linux-kernel@vger.kernel.org, Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , devicetree@vger.kernel.org, Rob Herring , Krzysztof Kozlowski , Conor Dooley , Esben Haabendal , Erez Geva Subject: [PATCH v4 4/5] mtd: spi-nor: macronix: add support for OTP Date: Tue, 17 Sep 2024 11:49:55 +0200 Message-Id: <20240917094956.437078-5-erezgeva@nwtime.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20240917094956.437078-1-erezgeva@nwtime.org> References: <20240917094956.437078-1-erezgeva@nwtime.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Erez Geva Macronix SPI-NOR support OTP. Add callbacks to read, write and lock the OTP. Notice Macronix OTP do not support erase. Every bit written with '0', can not be changed further. Notice Macronix OTP do not support single region lock! The locking include all regions at once! Signed-off-by: Erez Geva --- drivers/mtd/spi-nor/macronix.c | 167 +++++++++++++++++++++++++++++++++ include/linux/mtd/spi-nor.h | 9 ++ 2 files changed, 176 insertions(+) diff --git a/drivers/mtd/spi-nor/macronix.c b/drivers/mtd/spi-nor/macronix.c index ea6be95e75a5..02aa844d641b 100644 --- a/drivers/mtd/spi-nor/macronix.c +++ b/drivers/mtd/spi-nor/macronix.c @@ -8,6 +8,162 @@ =20 #include "core.h" =20 +/** + * macronix_nor_otp_enter() - Send Enter Secured OTP instruction to the ch= ip. + * @nor: pointer to 'struct spi_nor'. + * + * Return: 0 on success, -errno otherwise. + */ +static int macronix_nor_otp_enter(struct spi_nor *nor) +{ + int error; + + error =3D spi_nor_send_cmd(nor, SPINOR_OP_ENSO); + if (error) + dev_dbg(nor->dev, "error %d on Macronix Enter Secured OTP\n", error); + + return error; +} + +/** + * macronix_nor_otp_exit() - Send Exit Secured OTP instruction to the chip. + * @nor: pointer to 'struct spi_nor'. + * + * Return: 0 on success, -errno otherwise. + */ +static int macronix_nor_otp_exit(struct spi_nor *nor) +{ + int error; + + error =3D spi_nor_send_cmd(nor, SPINOR_OP_EXSO); + if (error) + dev_dbg(nor->dev, "error %d on Macronix Exit Secured OTP\n", error); + + return error; +} + +/** + * macronix_nor_otp_read() - read security register + * @nor: pointer to 'struct spi_nor' + * @addr: offset to read from + * @len: number of bytes to read + * @buf: pointer to dst buffer + * + * Return: number of bytes read successfully, -errno otherwise + */ +static int macronix_nor_otp_read(struct spi_nor *nor, loff_t addr, size_t = len, u8 *buf) +{ + int ret, error; + + error =3D macronix_nor_otp_enter(nor); + if (error) + return error; + + ret =3D spi_nor_read_data(nor, addr, len, buf); + + error =3D macronix_nor_otp_exit(nor); + + if (ret < 0) + dev_dbg(nor->dev, "error %d on Macronix read OTP data\n", ret); + else if (error) + return error; + + return ret; +} + +/** + * macronix_nor_otp_write() - write security register + * @nor: pointer to 'struct spi_nor' + * @addr: offset to write to + * @len: number of bytes to write + * @buf: pointer to src buffer + * + * Return: number of bytes written successfully, -errno otherwise + */ +static int macronix_nor_otp_write(struct spi_nor *nor, loff_t addr, size_t= len, const u8 *buf) +{ + int error, ret =3D 0; + + error =3D macronix_nor_otp_enter(nor); + if (error) + return error; + + error =3D spi_nor_write_enable(nor); + if (error) + goto otp_write_err; + + ret =3D spi_nor_write_data(nor, addr, len, buf); + if (ret < 0) { + dev_dbg(nor->dev, "error %d on Macronix write OTP data\n", ret); + goto otp_write_err; + } + + error =3D spi_nor_wait_till_ready(nor); + if (error) + dev_dbg(nor->dev, "error %d on Macronix waiting write OTP finish\n", err= or); + +otp_write_err: + + error =3D macronix_nor_otp_exit(nor); + + return ret; +} + +/** + * macronix_nor_otp_lock() - lock the OTP region + * @nor: pointer to 'struct spi_nor' + * @region: OTP region + * + * Return: 0 on success, -errno otherwise. + */ +static int macronix_nor_otp_lock(struct spi_nor *nor, unsigned int region) +{ + int error; + u8 *rdscur =3D nor->bouncebuf; + + error =3D spi_nor_read_reg(nor, SPINOR_OP_RDSCUR, 1); + if (error) { + dev_dbg(nor->dev, "error %d on read security register\n", error); + return error; + } + + if (rdscur[0] & SEC_REG_LDSO) + return 0; + + error =3D spi_nor_write_enable(nor); + if (error) { + dev_dbg(nor->dev, "error %d on enable write before update security regis= ter\n", + error); + return error; + } + + error =3D spi_nor_send_cmd(nor, SPINOR_OP_WRSCUR); + if (error) + dev_dbg(nor->dev, "error %d on update security register\n", error); + + return error; +} + +/** + * macronix_nor_otp_is_locked() - get the OTP region lock status + * @nor: pointer to 'struct spi_nor' + * @region: OTP region + * + * Return: 1 on lock, 0 on not locked, -errno otherwise. + */ +static int macronix_nor_otp_is_locked(struct spi_nor *nor, unsigned int re= gion) +{ + int error; + u8 *rdscur =3D nor->bouncebuf; + + error =3D spi_nor_read_reg(nor, SPINOR_OP_RDSCUR, 1); + if (error) { + dev_dbg(nor->dev, "error %d on read security register\n", error); + return error; + } + return rdscur[0] & SEC_REG_LDSO ? 1 : 0; +} + static int mx25l25635_post_bfpt_fixups(struct spi_nor *nor, const struct sfdp_parameter_header *bfpt_header, @@ -190,8 +346,19 @@ static void macronix_nor_default_init(struct spi_nor *= nor) nor->params->quad_enable =3D spi_nor_sr1_bit6_quad_enable; } =20 +static const struct spi_nor_otp_ops macronix_nor_otp_ops =3D { + .read =3D macronix_nor_otp_read, + .write =3D macronix_nor_otp_write, + /* .erase =3D Macronix OTP do not support erase, */ + .lock =3D macronix_nor_otp_lock, + .is_locked =3D macronix_nor_otp_is_locked, +}; + static int macronix_nor_late_init(struct spi_nor *nor) { + if (nor->params->otp.org.n_regions) + nor->params->otp.ops =3D ¯onix_nor_otp_ops; + if (!nor->params->set_4byte_addr_mode) nor->params->set_4byte_addr_mode =3D spi_nor_set_4byte_addr_mode_en4b_ex= 4b; =20 diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index cdcfe0fd2e7d..ef834e7fc0ac 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -81,6 +81,15 @@ #define SPINOR_OP_BP 0x02 /* Byte program */ #define SPINOR_OP_AAI_WP 0xad /* Auto address increment word program */ =20 +/* Macronix OTP registers. */ +#define SPINOR_OP_RDSCUR 0x2b /* read security register */ +#define SPINOR_OP_WRSCUR 0x2f /* write security register */ +#define SPINOR_OP_ENSO 0xb1 /* enter secured OTP */ +#define SPINOR_OP_EXSO 0xc1 /* exit secured OTP */ + +/* Macronix security register values */ +#define SEC_REG_LDSO BIT(1) /* Lock-down Secured OTP */ + /* Used for Macronix and Winbond flashes. */ #define SPINOR_OP_EN4B 0xb7 /* Enter 4-byte mode */ #define SPINOR_OP_EX4B 0xe9 /* Exit 4-byte mode */ --=20 2.39.5 From nobody Fri Nov 29 16:49:54 2024 Received: from chessie.everett.org (chessie.fmt1.pfcs.com [66.220.13.234]) by smtp.subspace.kernel.org (Postfix) with ESMTP id A110115B10C; Tue, 17 Sep 2024 09:50:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=66.220.13.234 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726566658; cv=none; b=mDXds6uFJKxX2g5iHUfPGFz5Kn1utNaxF1Pmhh66sbfuJcPWGf7HhEzw8k7ybiILtatUa/Nt4fssFLKhHKJwIm1tGbJlldqrrrBTZXM6kYHz4cZGfuuTjlXsfaPj2QpnVj4uhnAiNF/3jb5dnui8CyPcgerAeZNb1I4DGnFIj0Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726566658; c=relaxed/simple; bh=eWv8FFAF66yZo1Jtx2qsOXeX9rjacOvpnZok8MaHeE4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=qCwJ/4RfnMM9E3H+PmG5fDUZp5GIfZaQZr8cl6vkMSUcy3tJjC1xgS1jeXF3okAnrQzqMn7psMSFAERkUiyPlHesANs/d2bY85qF+Yb8nQ4N9ckjZ/WXbt2np+3PnQ1nGZijMz0jUCDGqxS58L4sPo7pXkmXFBVh3baYUPFoZl4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=nwtime.org; spf=pass smtp.mailfrom=nwtime.org; arc=none smtp.client-ip=66.220.13.234 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=nwtime.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nwtime.org Received: from localhost.localdomain (unknown [31.16.248.93]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by chessie.everett.org (Postfix) with ESMTPSA id 4X7H8h2QgLzMR67; Tue, 17 Sep 2024 09:50:44 +0000 (UTC) From: Erez Geva To: linux-mtd@lists.infradead.org, Tudor Ambarus , Pratyush Yadav , Michael Walle Cc: linux-kernel@vger.kernel.org, Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , devicetree@vger.kernel.org, Rob Herring , Krzysztof Kozlowski , Conor Dooley , Esben Haabendal , Erez Geva Subject: [PATCH v4 5/5] mtd: spi-nor: macronix: add manufacturer flags Date: Tue, 17 Sep 2024 11:49:56 +0200 Message-Id: <20240917094956.437078-6-erezgeva@nwtime.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20240917094956.437078-1-erezgeva@nwtime.org> References: <20240917094956.437078-1-erezgeva@nwtime.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Erez Geva Add flag for always trying reading SFDP: All new chips from Macronix support SFDP. All old chips in the IDs table were reused by new chips. Add flag for reading OTP parameters from device tree. As Macronix reuse JEDEC IDs, there is no way to determine OTP parameters. Allow users to define the OTP parameters in device tree. Signed-off-by: Erez Geva --- Notes: * My initial Macronix OTP code was tested with MX25l12833F. * As I no longer have that hardware. =20 * I now testing with MX25L3233F connected to my BeagleBone Black * through an 8-PIN SOP (200mil). * The BeagleBone Black runs with Debian GNU/Linux 12. * And use Kernel 6.6.32-ti-arm32-r5 build with * arm-linux-gnueabihf-gcc gcc version 12.2.0 (Debian 12.2.0-14). =20 $ cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id c22016 $ cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer macronix $ cat /sys/bus/spi/devices/spi0.0/spi-nor/partname mx25l3205d $ xxd -p /sys/bus/spi/devices/spi0.0/spi-nor/sfdp 53464450000101ff00000109300000ffc2000104600000ffffffffffffff ffffffffffffffffffffffffffffffffffffe520f1ffffffff0144eb086b 083b04bbeeffffffffff00ffffff00ff0c200f5210d800ffffffffffffff ffffffffffff003650269ef97764fecfffffffffffff $ sha256sum /sys/bus/spi/devices/spi0.0/spi-nor/sfdp 22d5d34af77c3628300056a0fc4bfbeafa027f544998852cf27f7cebf7881196 /sys/= bus/spi/devices/spi0.0/spi-nor/sfdp =20 $ cat /sys/kernel/debug/spi-nor/spi0.0/capabilities Supported read modes by the flash 1S-1S-1S opcode 0x03 mode cycles 0 dummy cycles 0 1S-1S-2S opcode 0x3b mode cycles 0 dummy cycles 8 1S-2S-2S opcode 0xbb mode cycles 0 dummy cycles 4 1S-1S-4S opcode 0x6b mode cycles 0 dummy cycles 8 1S-4S-4S opcode 0xeb mode cycles 2 dummy cycles 4 =20 Supported page program modes by the flash 1S-1S-1S opcode 0x02 =20 $ cat /sys/kernel/debug/spi-nor/spi0.0/params name mx25l3205d id c2 20 16 c2 20 16 size 4.00 MiB write size 1 page size 256 address nbytes 3 flags HAS_16BIT_SR =20 opcodes read 0x03 dummy cycles 0 erase 0x20 program 0x02 8D extension none =20 protocols read 1S-1S-1S write 1S-1S-1S register 1S-1S-1S =20 erase commands 20 (4.00 KiB) [1] 52 (32.0 KiB) [2] d8 (64.0 KiB) [3] c7 (4.00 MiB) =20 sector map region (in hex) | erase mask | flags ------------------+------------+---------- 00000000-003fffff | [ 123] | =20 # mtd_debug info /dev/mtd0 mtd.type =3D MTD_NORFLASH mtd.flags =3D MTD_CAP_NORFLASH mtd.size =3D 4194304 (4M) mtd.erasesize =3D 4096 (4K) mtd.writesize =3D 1 mtd.oobsize =3D 0 regions =3D 0 =20 * The BeagleBone Black SPI is very slow, Tests are slow. =20 # dd if=3D/dev/urandom of=3D./spi_test bs=3D1M count=3D2 2+0 records in 2+0 records out 2097152 bytes (2.1 MB, 2.0 MiB) copied, 0.0682607 s, 30.7 MB/s =20 # time mtd_debug erase /dev/mtd0 0 2097152 Erased 2097152 bytes from address 0x00000000 in flash =20 real 0m12.703s user 0m0.000s sys 0m12.692s =20 # time mtd_debug read /dev/mtd0 0 2097152 spi_read Copied 2097152 bytes from address 0x00000000 in flash to spi_read =20 real 0m1.942s user 0m0.000s sys 0m0.053s =20 # hexdump spi_read 0000000 ffff ffff ffff ffff ffff ffff ffff ffff * 0200000 =20 # sha256sum spi_read 4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5 spi_r= ead =20 # time mtd_debug write /dev/mtd0 0 2097152 spi_test Copied 2097152 bytes from spi_test to address 0x00000000 in flash =20 real 0m5.883s user 0m0.006s sys 0m3.970s =20 # time mtd_debug read /dev/mtd0 0 2097152 spi_read Copied 2097152 bytes from address 0x00000000 in flash to spi_read =20 real 0m2.208s user 0m0.003s sys 0m0.063s =20 # sha256sum spi* f4f5d1d0a4fef487037cdb3f1be0f9aab68ca32f2dbe8782c927f03adf623ec3 spi_r= ead f4f5d1d0a4fef487037cdb3f1be0f9aab68ca32f2dbe8782c927f03adf623ec3 spi_t= est =20 # time mtd_debug erase /dev/mtd0 0 2097152 Erased 2097152 bytes from address 0x00000000 in flash =20 real 0m12.126s user 0m0.001s sys 0m12.115s =20 # time mtd_debug read /dev/mtd0 0 2097152 spi_read Copied 2097152 bytes from address 0x00000000 in flash to spi_read =20 real 0m2.611s user 0m0.000s sys 0m0.064s =20 # sha256sum spi* 4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5 spi_r= ead f4f5d1d0a4fef487037cdb3f1be0f9aab68ca32f2dbe8782c927f03adf623ec3 spi_t= est =20 * MX25L3233F OTP uses 1 region of size of 4096 bits =20 $ git diff -U1 diff --git a/arch/arm/boot/dts/ti/omap/BB-SPINOR-00A0.dtso b/arch/arm/b= oot/dts/ti/omap/BB-SPINOR-00A0.dtso index 333a6b9556ed..adaddfaa8091 100644 --- a/arch/arm/boot/dts/ti/omap/BB-SPINOR-00A0.dtso +++ b/arch/arm/boot/dts/ti/omap/BB-SPINOR-00A0.dtso @@ -63,6 +63,8 @@ channel@0 { compatible =3D "jedec,spi-nor"; + otp_len =3D <512>; + opt_n_regions =3D <1>; =20 # flash_otp_info -u /dev/mtd0 Number of OTP user blocks on /dev/mtd0: 1 block 0: offset =3D 0x0000 size =3D 512 bytes [unlocked] =20 # flash_otp_dump -u /dev/mtd0 OTP user data for /dev/mtd0 0x0000: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 0x0010: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 0x0020: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 0x0030: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 0x0040: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 0x0050: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 0x0060: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 0x0070: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 0x0080: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 0x0090: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 0x00a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 0x00b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 0x00c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 0x00d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 0x00e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 0x00f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 0x0100: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 0x0110: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 0x0120: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 0x0130: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 0x0140: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 0x0150: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 0x0160: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 0x0170: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 0x0180: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 0x0190: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 0x01a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 0x01b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 0x01c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 0x01d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 0x01e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 0x01f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff =20 * Macronix OTP does not support erase! * flash_otp_erase =20 # printf '\xde\xad%.0s' {1..256} | flash_otp_write -u /dev/mtd0 0 Writing OTP user data on /dev/mtd0 at offset 0x0 Wrote 512 bytes of OTP user data =20 # flash_otp_dump -u /dev/mtd0 OTP user data for /dev/mtd0 0x0000: de ad de ad de ad de ad de ad de ad de ad de ad 0x0010: de ad de ad de ad de ad de ad de ad de ad de ad 0x0020: de ad de ad de ad de ad de ad de ad de ad de ad 0x0030: de ad de ad de ad de ad de ad de ad de ad de ad 0x0040: de ad de ad de ad de ad de ad de ad de ad de ad 0x0050: de ad de ad de ad de ad de ad de ad de ad de ad 0x0060: de ad de ad de ad de ad de ad de ad de ad de ad 0x0070: de ad de ad de ad de ad de ad de ad de ad de ad 0x0080: de ad de ad de ad de ad de ad de ad de ad de ad 0x0090: de ad de ad de ad de ad de ad de ad de ad de ad 0x00a0: de ad de ad de ad de ad de ad de ad de ad de ad 0x00b0: de ad de ad de ad de ad de ad de ad de ad de ad 0x00c0: de ad de ad de ad de ad de ad de ad de ad de ad 0x00d0: de ad de ad de ad de ad de ad de ad de ad de ad 0x00e0: de ad de ad de ad de ad de ad de ad de ad de ad 0x00f0: de ad de ad de ad de ad de ad de ad de ad de ad 0x0100: de ad de ad de ad de ad de ad de ad de ad de ad 0x0110: de ad de ad de ad de ad de ad de ad de ad de ad 0x0120: de ad de ad de ad de ad de ad de ad de ad de ad 0x0130: de ad de ad de ad de ad de ad de ad de ad de ad 0x0140: de ad de ad de ad de ad de ad de ad de ad de ad 0x0150: de ad de ad de ad de ad de ad de ad de ad de ad 0x0160: de ad de ad de ad de ad de ad de ad de ad de ad 0x0170: de ad de ad de ad de ad de ad de ad de ad de ad 0x0180: de ad de ad de ad de ad de ad de ad de ad de ad 0x0190: de ad de ad de ad de ad de ad de ad de ad de ad 0x01a0: de ad de ad de ad de ad de ad de ad de ad de ad 0x01b0: de ad de ad de ad de ad de ad de ad de ad de ad 0x01c0: de ad de ad de ad de ad de ad de ad de ad de ad 0x01d0: de ad de ad de ad de ad de ad de ad de ad de ad 0x01e0: de ad de ad de ad de ad de ad de ad de ad de ad 0x01f0: de ad de ad de ad de ad de ad de ad de ad de ad =20 # flash_otp_info -u /dev/mtd0 Number of OTP user blocks on /dev/mtd0: 1 block 0: offset =3D 0x0000 size =3D 512 bytes [unlocked] =20 # printf '\xff\xff%.0s' {1..256} | flash_otp_write -u /dev/mtd0 0 Writing OTP user data on /dev/mtd0 at offset 0x0 Wrote 512 bytes of OTP user data =20 # We cannot overwrite '0' with '1'! =20 # flash_otp_dump -u /dev/mtd0 OTP user data for /dev/mtd0 0x0000: de ad de ad de ad de ad de ad de ad de ad de ad 0x0010: de ad de ad de ad de ad de ad de ad de ad de ad 0x0020: de ad de ad de ad de ad de ad de ad de ad de ad 0x0030: de ad de ad de ad de ad de ad de ad de ad de ad 0x0040: de ad de ad de ad de ad de ad de ad de ad de ad 0x0050: de ad de ad de ad de ad de ad de ad de ad de ad 0x0060: de ad de ad de ad de ad de ad de ad de ad de ad 0x0070: de ad de ad de ad de ad de ad de ad de ad de ad 0x0080: de ad de ad de ad de ad de ad de ad de ad de ad 0x0090: de ad de ad de ad de ad de ad de ad de ad de ad 0x00a0: de ad de ad de ad de ad de ad de ad de ad de ad 0x00b0: de ad de ad de ad de ad de ad de ad de ad de ad 0x00c0: de ad de ad de ad de ad de ad de ad de ad de ad 0x00d0: de ad de ad de ad de ad de ad de ad de ad de ad 0x00e0: de ad de ad de ad de ad de ad de ad de ad de ad 0x00f0: de ad de ad de ad de ad de ad de ad de ad de ad 0x0100: de ad de ad de ad de ad de ad de ad de ad de ad 0x0110: de ad de ad de ad de ad de ad de ad de ad de ad 0x0120: de ad de ad de ad de ad de ad de ad de ad de ad 0x0130: de ad de ad de ad de ad de ad de ad de ad de ad 0x0140: de ad de ad de ad de ad de ad de ad de ad de ad 0x0150: de ad de ad de ad de ad de ad de ad de ad de ad 0x0160: de ad de ad de ad de ad de ad de ad de ad de ad 0x0170: de ad de ad de ad de ad de ad de ad de ad de ad 0x0180: de ad de ad de ad de ad de ad de ad de ad de ad 0x0190: de ad de ad de ad de ad de ad de ad de ad de ad 0x01a0: de ad de ad de ad de ad de ad de ad de ad de ad 0x01b0: de ad de ad de ad de ad de ad de ad de ad de ad 0x01c0: de ad de ad de ad de ad de ad de ad de ad de ad 0x01d0: de ad de ad de ad de ad de ad de ad de ad de ad 0x01e0: de ad de ad de ad de ad de ad de ad de ad de ad 0x01f0: de ad de ad de ad de ad de ad de ad de ad de ad =20 # flash_otp_lock -u /dev/mtd0 0 512 About to lock OTP user data on /dev/mtd0 from 0x0 to 0x200 flash_otp_lock: Are you sure? (y/N) y Done. =20 # flash_otp_info -u /dev/mtd0 Number of OTP user blocks on /dev/mtd0: 1 block 0: offset =3D 0x0000 size =3D 512 bytes [locked] =20 # printf '\x00\x00%.0s' {1..256} | flash_otp_write -u /dev/mtd0 0 Writing OTP user data on /dev/mtd0 at offset 0x0 write(): Read-only file system =20 # flash_otp_dump -u /dev/mtd0 OTP user data for /dev/mtd0 0x0000: de ad de ad de ad de ad de ad de ad de ad de ad 0x0010: de ad de ad de ad de ad de ad de ad de ad de ad 0x0020: de ad de ad de ad de ad de ad de ad de ad de ad 0x0030: de ad de ad de ad de ad de ad de ad de ad de ad 0x0040: de ad de ad de ad de ad de ad de ad de ad de ad 0x0050: de ad de ad de ad de ad de ad de ad de ad de ad 0x0060: de ad de ad de ad de ad de ad de ad de ad de ad 0x0070: de ad de ad de ad de ad de ad de ad de ad de ad 0x0080: de ad de ad de ad de ad de ad de ad de ad de ad 0x0090: de ad de ad de ad de ad de ad de ad de ad de ad 0x00a0: de ad de ad de ad de ad de ad de ad de ad de ad 0x00b0: de ad de ad de ad de ad de ad de ad de ad de ad 0x00c0: de ad de ad de ad de ad de ad de ad de ad de ad 0x00d0: de ad de ad de ad de ad de ad de ad de ad de ad 0x00e0: de ad de ad de ad de ad de ad de ad de ad de ad 0x00f0: de ad de ad de ad de ad de ad de ad de ad de ad 0x0100: de ad de ad de ad de ad de ad de ad de ad de ad 0x0110: de ad de ad de ad de ad de ad de ad de ad de ad 0x0120: de ad de ad de ad de ad de ad de ad de ad de ad 0x0130: de ad de ad de ad de ad de ad de ad de ad de ad 0x0140: de ad de ad de ad de ad de ad de ad de ad de ad 0x0150: de ad de ad de ad de ad de ad de ad de ad de ad 0x0160: de ad de ad de ad de ad de ad de ad de ad de ad 0x0170: de ad de ad de ad de ad de ad de ad de ad de ad 0x0180: de ad de ad de ad de ad de ad de ad de ad de ad 0x0190: de ad de ad de ad de ad de ad de ad de ad de ad 0x01a0: de ad de ad de ad de ad de ad de ad de ad de ad 0x01b0: de ad de ad de ad de ad de ad de ad de ad de ad 0x01c0: de ad de ad de ad de ad de ad de ad de ad de ad 0x01d0: de ad de ad de ad de ad de ad de ad de ad de ad 0x01e0: de ad de ad de ad de ad de ad de ad de ad de ad 0x01f0: de ad de ad de ad de ad de ad de ad de ad de ad =20 * Test that mimic old Macronix chip lack SFDP. * In order to check how will the driver cope with an old Macronix chip. * As we do not posses such an old chip, we will change RDSFDP to an unu= sed opcode. =20 $ git diff -U0 diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index 4ebc527aadc1..784cba9b2d0d 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -47 +47 @@ -#define SPINOR_OP_RDSFDP 0x5a /* Read SFDP */ +#define SPINOR_OP_RDSFDP 0x57 /* Read SFDP */ =20 # dmesg | grep spi [ 42.436974] spi-nor spi0.0: mx25l3205d (4096 Kbytes) =20 * No error in kernel log! =20 # ls /sys/bus/spi/devices/spi0.0/spi-nor/ jedec_id manufacturer partname =20 * No SFDP, as expected! =20 $ cat /sys/kernel/debug/spi-nor/spi0.0/capabilities Supported read modes by the flash 1S-1S-1S opcode 0x03 mode cycles 0 dummy cycles 0 =20 Supported page program modes by the flash 1S-1S-1S opcode 0x02 =20 $ cat /sys/kernel/debug/spi-nor/spi0.0/params name mx25l3205d id c2 20 16 c2 20 16 size 4.00 MiB write size 1 page size 256 address nbytes 3 flags HAS_16BIT_SR =20 opcodes read 0x03 dummy cycles 0 erase 0x20 program 0x02 8D extension none =20 protocols read 1S-1S-1S write 1S-1S-1S register 1S-1S-1S =20 erase commands 20 (4.00 KiB) [0] d8 (64.0 KiB) [1] c7 (4.00 MiB) =20 sector map region (in hex) | erase mask | flags ------------------+------------+---------- 00000000-003fffff | [01 ] | drivers/mtd/spi-nor/macronix.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mtd/spi-nor/macronix.c b/drivers/mtd/spi-nor/macronix.c index 02aa844d641b..f79033e9efa5 100644 --- a/drivers/mtd/spi-nor/macronix.c +++ b/drivers/mtd/spi-nor/macronix.c @@ -375,4 +375,5 @@ const struct spi_nor_manufacturer spi_nor_macronix =3D { .parts =3D macronix_nor_parts, .nparts =3D ARRAY_SIZE(macronix_nor_parts), .fixups =3D ¯onix_nor_fixups, + .flags =3D SPI_NOR_MANUFACT_TRY_SFDP | SPI_NOR_MANUFACT_DT_OTP, }; --=20 2.39.5