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charset="utf-8" X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20240917094452epcas5p2c6ea2af1bc0e0f8daf50218b37eb1936 References: <20240917094355.37887-1-inbaraj.e@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Number of clocks supported by Linux drivers might vary - sometimes we add new clocks, not exposed previously. Therefore these numbers of clocks should not be in the bindings, as that prevents changing them. Define number of clocks per each clock controller inside the driver directly. Signed-off-by: Inbaraj E --- drivers/clk/samsung/clk-fsd.c | 23 ++++++++++++++++------- 1 file changed, 16 insertions(+), 7 deletions(-) diff --git a/drivers/clk/samsung/clk-fsd.c b/drivers/clk/samsung/clk-fsd.c index 6f984cfcd33c..9a6006c298c2 100644 --- a/drivers/clk/samsung/clk-fsd.c +++ b/drivers/clk/samsung/clk-fsd.c @@ -82,6 +82,15 @@ #define GAT_CMU_NS_BRDG_CMU_IPCLKPORT_CLK__PSOC_CMU__CLK_CMU 0x205c #define GAT_CMU_SYSREG_CMU_IPCLKPORT_PCLK 0x2060 =20 +/* NOTE: Must be equal to the last clock ID increased by one */ +#define CLKS_NR_CMU (GAT_CMU_FSYS0_SHARED0DIV4 + 1) +#define CLKS_NR_PERIC (PERIC_DOUT_RGMII_CLK + 1) +#define CLKS_NR_FSYS0 (FSYS0_DOUT_FSYS0_PERIBUS_GRP + 1) +#define CLKS_NR_FSYS1 (PCIE_LINK1_IPCLKPORT_SLV_ACLK + 1) +#define CLKS_NR_IMEM (IMEM_TMU_GT_IPCLKPORT_I_CLK_TS + 1) +#define CLKS_NR_MFC (MFC_MFC_IPCLKPORT_ACLK + 1) +#define CLKS_NR_CAM_CSI (CAM_CSI2_3_IPCLKPORT_I_ACLK + 1) + static const unsigned long cmu_clk_regs[] __initconst =3D { PLL_LOCKTIME_PLL_SHARED0, PLL_LOCKTIME_PLL_SHARED1, @@ -300,7 +309,7 @@ static const struct samsung_cmu_info cmu_cmu_info __ini= tconst =3D { .nr_div_clks =3D ARRAY_SIZE(cmu_div_clks), .gate_clks =3D cmu_gate_clks, .nr_gate_clks =3D ARRAY_SIZE(cmu_gate_clks), - .nr_clk_ids =3D CMU_NR_CLK, + .nr_clk_ids =3D CLKS_NR_CMU, .clk_regs =3D cmu_clk_regs, .nr_clk_regs =3D ARRAY_SIZE(cmu_clk_regs), }; @@ -665,7 +674,7 @@ static const struct samsung_cmu_info peric_cmu_info __i= nitconst =3D { .nr_gate_clks =3D ARRAY_SIZE(peric_gate_clks), .fixed_clks =3D peric_fixed_clks, .nr_fixed_clks =3D ARRAY_SIZE(peric_fixed_clks), - .nr_clk_ids =3D PERIC_NR_CLK, + .nr_clk_ids =3D CLKS_NR_PERIC, .clk_regs =3D peric_clk_regs, .nr_clk_regs =3D ARRAY_SIZE(peric_clk_regs), .clk_name =3D "dout_cmu_pll_shared0_div4", @@ -964,7 +973,7 @@ static const struct samsung_cmu_info fsys0_cmu_info __i= nitconst =3D { .nr_gate_clks =3D ARRAY_SIZE(fsys0_gate_clks), .fixed_clks =3D fsys0_fixed_clks, .nr_fixed_clks =3D ARRAY_SIZE(fsys0_fixed_clks), - .nr_clk_ids =3D FSYS0_NR_CLK, + .nr_clk_ids =3D CLKS_NR_FSYS0, .clk_regs =3D fsys0_clk_regs, .nr_clk_regs =3D ARRAY_SIZE(fsys0_clk_regs), .clk_name =3D "dout_cmu_fsys0_shared1div4", @@ -1136,7 +1145,7 @@ static const struct samsung_cmu_info fsys1_cmu_info _= _initconst =3D { .nr_gate_clks =3D ARRAY_SIZE(fsys1_gate_clks), .fixed_clks =3D fsys1_fixed_clks, .nr_fixed_clks =3D ARRAY_SIZE(fsys1_fixed_clks), - .nr_clk_ids =3D FSYS1_NR_CLK, + .nr_clk_ids =3D CLKS_NR_FSYS1, .clk_regs =3D fsys1_clk_regs, .nr_clk_regs =3D ARRAY_SIZE(fsys1_clk_regs), .clk_name =3D "dout_cmu_fsys1_shared0div4", @@ -1413,7 +1422,7 @@ static const struct samsung_cmu_info imem_cmu_info __= initconst =3D { .nr_div_clks =3D ARRAY_SIZE(imem_div_clks), .gate_clks =3D imem_gate_clks, .nr_gate_clks =3D ARRAY_SIZE(imem_gate_clks), - .nr_clk_ids =3D IMEM_NR_CLK, + .nr_clk_ids =3D CLKS_NR_IMEM, .clk_regs =3D imem_clk_regs, .nr_clk_regs =3D ARRAY_SIZE(imem_clk_regs), }; @@ -1538,7 +1547,7 @@ static const struct samsung_cmu_info mfc_cmu_info __i= nitconst =3D { .nr_div_clks =3D ARRAY_SIZE(mfc_div_clks), .gate_clks =3D mfc_gate_clks, .nr_gate_clks =3D ARRAY_SIZE(mfc_gate_clks), - .nr_clk_ids =3D MFC_NR_CLK, + .nr_clk_ids =3D CLKS_NR_MFC, .clk_regs =3D mfc_clk_regs, .nr_clk_regs =3D ARRAY_SIZE(mfc_clk_regs), }; @@ -1742,7 +1751,7 @@ static const struct samsung_cmu_info cam_csi_cmu_info= __initconst =3D { .nr_div_clks =3D ARRAY_SIZE(cam_csi_div_clks), .gate_clks =3D cam_csi_gate_clks, .nr_gate_clks =3D ARRAY_SIZE(cam_csi_gate_clks), - .nr_clk_ids =3D CAM_CSI_NR_CLK, + .nr_clk_ids =3D CLKS_NR_CAM_CSI, .clk_regs =3D cam_csi_clk_regs, .nr_clk_regs =3D ARRAY_SIZE(cam_csi_clk_regs), }; --=20 2.17.1 From nobody Fri Nov 29 16:48:30 2024 Received: from mailout1.samsung.com (mailout1.samsung.com [203.254.224.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EA87E61FCE for ; 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Tue, 17 Sep 2024 18:44:54 +0900 (KST) Received: from cheetah.sa.corp.samsungelectronics.net (unknown [107.109.115.53]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20240917094452epsmtip16146db8d027b6c51417cc96143e79deb~1-uUbSUAH2415624156epsmtip1a; Tue, 17 Sep 2024 09:44:52 +0000 (GMT) From: Inbaraj E To: krzk@kernel.org, s.nawrocki@samsung.com, cw00.choi@samsung.com, alim.akhtar@samsung.com, mturquette@baylibre.com, sboyd@kernel.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, robh@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org Cc: pankaj.dubey@samsung.com, gost.dev@samsung.com, Inbaraj E Subject: [PATCH 2/2] dt-bindings: clock: samsung: remove define with number of clocks for FSD Date: Tue, 17 Sep 2024 15:13:55 +0530 Message-Id: <20240917094355.37887-3-inbaraj.e@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240917094355.37887-1-inbaraj.e@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmpik+LIzCtJLcpLzFFi42LZdlhTU/dT1Ms0g5bnbBYP5m1js1iz9xyT xfUvz1kt5h85x2px88BOJou7fyaxWZw/v4Hd4mPPPVaLy7vmsFnMOL+PyeLiKVeLRVu/sFv8 37OD3eLwm3ZWi3/XNrI48Hu8v9HK7rFpVSebR9+WVYwenzfJBbBEZdtkpCampBYppOYl56dk 5qXbKnkHxzvHm5oZGOoaWlqYKynkJeam2iq5+AToumXmAB2qpFCWmFMKFApILC5W0rezKcov LUlVyMgvLrFVSi1IySkwKdArTswtLs1L18tLLbEyNDAwMgUqTMjOeP67nbFgt0DFtQ1HWBsY 9/J2MXJySAiYSJy70cfcxcjFISSwm1FizpqlbBDOJ0aJTeufMcM53b9OM8K0LGt8xwZiCwns ZJTo2M8HUdTKJNGzYSdYEZuAusSG7u9go0QE1jBJrJ59ghUkwSwQLnFu+kUwW1ggXuLb3yvM IDaLgKrErckvwWxeASuJt79fMENsk5dYveEAmM0pYC3x7udvsJMkBL6yS9zY1swOUeQiMbd7 G9R5whKvjm+BiktJvOxvg7J9JPbP+QVVkyFxbPtyVgjbXuLAlTksXYwcQMdpSqzfpQ8RlpWY emodE8TNfBK9v58wQcR5JXbMg7GVJWYeuc8GYUtK7Ly8E2yMhICHxIFeY0ig9DFKfH23g3kC o9wshA0LGBlXMUqmFhTnpqcmmxYY5qWWw2MtOT93EyM4MWq57GC8Mf+f3iFGJg7GQ4wSHMxK Iry2v5+mCfGmJFZWpRblxxeV5qQWH2I0BYbfRGYp0eR8YGrOK4k3NLE0MDEzMzOxNDYzVBLn fd06N0VIID2xJDU7NbUgtQimj4mDU6qBid/u3bZunk+Hl32/GbXniPy/mK/F9fZOLTYab78e OjGjOCfb5e/r+2uVrs+1PBWrsf7tpDc94lmM6bxf2CSOFrReXhC9Pdf1R6n+1YU8C5tn+Og9 X3FSRnzTCzWW35Ve4Wy1PI4v9ZM0FybqK69cUmqiyK1r1JNvtJeD7eDG3f7xa/SrT+3dZJ0/ 86pEpORDn1V3diu3FDk1ZNiZbePpdgwwPZIlmaHz8FfFvhVb4u396yamJea8+Ni277pq5JGp 08LT8q/2ui9b/ptzaVck50fNa/Va6Zrxyucm7JqfJ8km1H22NuDv+mceIXJXTMPvlhdUf1zz 4/dG+/osq/xcweMGbv+0Dwl+j/2b7NqpxFKckWioxVxUnAgA+0cSHxUEAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrKLMWRmVeSWpSXmKPExsWy7bCSnO40/5dpBpvf8lo8mLeNzWLN3nNM Fte/PGe1mH/kHKvFzQM7mSzu/pnEZnH+/AZ2i48991gtLu+aw2Yx4/w+JouLp1wtFm39wm7x f88OdovDb9pZLf5d28jiwO/x/kYru8emVZ1sHn1bVjF6fN4kF8ASxWWTkpqTWZZapG+XwJXx /Hc7Y8FugYprG46wNjDu5e1i5OSQEDCRWNb4jg3EFhLYziixcE0aRFxSYvbv6ewQtrDEyn/P gWwuoJpmJonmzYdZQBJsAuoSG7q/s4EkRAR2MUlMX7ydESTBLBAp8aN9K1i3sECsxJ0/PWA2 i4CqxK3JL5lBbF4BK4m3v18wQ2yQl1i94QCYzSlgLfHu529miIusJHr2zWOewMi3gJFhFaNo akFxbnpucoGhXnFibnFpXrpecn7uJkZwyGoF7WBctv6v3iFGJg7GQ4wSHMxKIry2v5+mCfGm JFZWpRblxxeV5qQWH2KU5mBREudVzulMERJITyxJzU5NLUgtgskycXBKNTCZl2mvTZaz4rjy TdN3ffaVGzKT0p9ZuSrMjrT0jFig/aul+u7231H3Wbbp2fvvfdOaGaz2ULjj7fv/OVvXTpea 9OBJyomZh05bzvbPnn538/aG86VJe8/PunAhVsG9artQtuDmKbwni9xW/ku1nuwftGLOvhXR eUFJde4zpC/kRQYFJ+sleq/9v5mNL+WC/tY974+k7JHTT+i+vv5H4kWfnDq+Davcm7TWtOyw Pxov+XZ2Er9Kx+pzzz7de6f49QJPTXuu95GDoZGu6keifVbd/pX+SLS3QuVxgHiRWGHErg3L c6bN5nvF7MrF8TxD9+KimlMnGLb7rfx4NGX3fVP/NInwsEePtY0Dzpt8EzugxFKckWioxVxU nAgAm3Rj18gCAAA= X-CMS-MailID: 20240917094454epcas5p22a75e3bb5a09b12eb269f1dcde573741 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20240917094454epcas5p22a75e3bb5a09b12eb269f1dcde573741 References: <20240917094355.37887-1-inbaraj.e@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Number of clocks supported by Linux drivers might vary - sometimes we add new clocks, not exposed previously. Therefore these numbers of clocks should not be in the bindings, as that prevents changing them. Remove it entirely from the bindings, once Linux drivers stopped using them. Signed-off-by: Inbaraj E Acked-by: Rob Herring (Arm) --- include/dt-bindings/clock/fsd-clk.h | 7 ------- 1 file changed, 7 deletions(-) diff --git a/include/dt-bindings/clock/fsd-clk.h b/include/dt-bindings/cloc= k/fsd-clk.h index c8a2af1dd1ad..3f7b64d93558 100644 --- a/include/dt-bindings/clock/fsd-clk.h +++ b/include/dt-bindings/clock/fsd-clk.h @@ -28,7 +28,6 @@ #define DOUT_CMU_IMEM_ACLK 13 #define DOUT_CMU_IMEM_DMACLK 14 #define GAT_CMU_FSYS0_SHARED0DIV4 15 -#define CMU_NR_CLK 16 =20 /* PERIC */ #define PERIC_SCLK_UART0 1 @@ -76,7 +75,6 @@ #define PERIC_EQOS_PHYRXCLK_MUX 43 #define PERIC_EQOS_PHYRXCLK 44 #define PERIC_DOUT_RGMII_CLK 45 -#define PERIC_NR_CLK 46 =20 /* FSYS0 */ #define UFS0_MPHY_REFCLK_IXTAL24 1 @@ -101,7 +99,6 @@ #define FSYS0_EQOS_TOP0_IPCLKPORT_RGMII_CLK_I 20 #define FSYS0_EQOS_TOP0_IPCLKPORT_CLK_RX_I 21 #define FSYS0_DOUT_FSYS0_PERIBUS_GRP 22 -#define FSYS0_NR_CLK 23 =20 /* FSYS1 */ #define PCIE_LINK0_IPCLKPORT_DBI_ACLK 1 @@ -112,7 +109,6 @@ #define PCIE_LINK1_IPCLKPORT_AUX_ACLK 6 #define PCIE_LINK1_IPCLKPORT_MSTR_ACLK 7 #define PCIE_LINK1_IPCLKPORT_SLV_ACLK 8 -#define FSYS1_NR_CLK 9 =20 /* IMEM */ #define IMEM_DMA0_IPCLKPORT_ACLK 1 @@ -126,11 +122,9 @@ #define IMEM_TMU_TOP_IPCLKPORT_I_CLK_TS 9 #define IMEM_TMU_GPU_IPCLKPORT_I_CLK_TS 10 #define IMEM_TMU_GT_IPCLKPORT_I_CLK_TS 11 -#define IMEM_NR_CLK 12 =20 /* MFC */ #define MFC_MFC_IPCLKPORT_ACLK 1 -#define MFC_NR_CLK 2 =20 /* CAM_CSI */ #define CAM_CSI0_0_IPCLKPORT_I_ACLK 1 @@ -145,6 +139,5 @@ #define CAM_CSI2_1_IPCLKPORT_I_ACLK 10 #define CAM_CSI2_2_IPCLKPORT_I_ACLK 11 #define CAM_CSI2_3_IPCLKPORT_I_ACLK 12 -#define CAM_CSI_NR_CLK 13 =20 #endif /*_DT_BINDINGS_CLOCK_FSD_H */ --=20 2.17.1