From nobody Thu Sep 19 23:06:47 2024 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 13BF915AACA; Tue, 17 Sep 2024 09:11:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726564300; cv=none; b=jtBnyqvVeirry1NK7X5agPp4bTNmePUQBgpbJHz19AbIaGvdW8Te9FgQR/DumrK2rPgKCcWTWAb3sZF7tHdafFJxmOeiazFd9dJ0GaROUjir6bWJnkngCqnOejjhs7juyfN1Bs6Yx6rnlU4ryynYNfBjlDLavonSDJV6nk7fhhM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726564300; c=relaxed/simple; bh=CmBOrOWMOO93CuLcWjDRjEaUDrbCyW9xdULFfDPOC8E=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=rKlnh5Z5e/87JBAx0rrENc/mWb4+447Cl2Y1jcmtOrIjed+Y69+xQKxTSvns/c+bO6JrDmmd2Cif19V6oFh0Oayf6hzsF/3VT4Fx1uANR0XxoF6+ggD24VqtUYJCma7doNCjwOdS5EX/zh6NHEI+i/F+z6l3ys3o5/Lp4GUup/g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=mUjkdxI9; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="mUjkdxI9" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1726564297; bh=CmBOrOWMOO93CuLcWjDRjEaUDrbCyW9xdULFfDPOC8E=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mUjkdxI92OKogmFv2ioV4lARuuwB/8U1GJ6Odx4FuHWDrfD2G401S6ZXXHrN9I4f+ Ajeu+j8suXW0DGcWDPxKJKksXOT7m3pb+PPebwGjwprHd65/UpHmqLFccxApj9DmJN yWUbTjpgbZ2n8e9JIeUk6aVuCcJel9ARttKnrJmo40Pz53b6ZTqImR2oEGvvOqMIYY Ilr8VYo/BmSo9jiAMDnQrd/5vbD8arWg+kWfkprdIVNDn/8cT7fOWtEADW4UuKoW1q kXs4FMXvhpY1BqLKW5o5mjzOvwt+yBwruLAxKip/ahD3K8v1aF0fKH1tvtZruS09sE lLKMuMuN5N56g== Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by bali.collaboradmins.com (Postfix) with ESMTPSA id CB01F17E1097; Tue, 17 Sep 2024 11:11:36 +0200 (CEST) From: AngeloGioacchino Del Regno To: linux-pci@vger.kernel.org Cc: ryder.lee@mediatek.com, jianjun.wang@mediatek.com, lpieralisi@kernel.org, kw@linux.com, robh@kernel.org, bhelgaas@google.com, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kernel@collabora.com Subject: [PATCH v2 2/2] PCI: mediatek-gen3: Add support for restricting link width Date: Tue, 17 Sep 2024 11:11:32 +0200 Message-ID: <20240917091132.286582-3-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20240917091132.286582-1-angelogioacchino.delregno@collabora.com> References: <20240917091132.286582-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for restricting the port's link width by specifying the num-lanes devicetree property in the PCIe node. The setting is done in the GEN_SETTINGS register (in the driver named as PCIE_SETTING_REG), where each set bit in [11:8] activates a set of lanes (from bits 11 to 8 respectively, x16/x8/x4/x2). Signed-off-by: AngeloGioacchino Del Regno --- drivers/pci/controller/pcie-mediatek-gen3.c | 22 ++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/cont= roller/pcie-mediatek-gen3.c index e1d1fb39d5c6..e2c9802a230c 100644 --- a/drivers/pci/controller/pcie-mediatek-gen3.c +++ b/drivers/pci/controller/pcie-mediatek-gen3.c @@ -32,6 +32,7 @@ #define PCIE_BASE_CFG_SPEED_MASK GENMASK(15, 8) =20 #define PCIE_SETTING_REG 0x80 +#define PCIE_SETTING_LINK_WIDTH GENMASK(11, 8) #define PCIE_SETTING_GEN_SUPPORT_MASK GENMASK(14, 12) #define PCIE_PCI_IDS_1 0x9c #define PCI_CLASS(class) (class << 8) @@ -168,6 +169,7 @@ struct mtk_msi_set { * @clks: PCIe clocks * @num_clks: PCIe clocks count for this port * @max_link_speed: Maximum link speed (PCIe Gen) for this port + * @num_lanes: Number of PCIe lanes for this port * @irq: PCIe controller interrupt number * @saved_irq_state: IRQ enable state saved at suspend time * @irq_lock: lock protecting IRQ register access @@ -189,6 +191,7 @@ struct mtk_gen3_pcie { struct clk_bulk_data *clks; int num_clks; u8 max_link_speed; + u8 num_lanes; =20 int irq; u32 saved_irq_state; @@ -390,7 +393,7 @@ static int mtk_pcie_startup_port(struct mtk_gen3_pcie *= pcie) int err; u32 val; =20 - /* Set as RC mode and set controller PCIe Gen speed restriction, if any*/ + /* Set as RC mode and set controller PCIe Gen speed/lanes restriction, if= any */ val =3D readl_relaxed(pcie->base + PCIE_SETTING_REG); val |=3D PCIE_RC_MODE; if (pcie->max_link_speed) { @@ -401,6 +404,14 @@ static int mtk_pcie_startup_port(struct mtk_gen3_pcie = *pcie) val |=3D FIELD_PREP(PCIE_SETTING_GEN_SUPPORT_MASK, GENMASK(pcie->max_link_speed - 2, 0)); } + if (pcie->num_lanes) { + val &=3D ~PCIE_SETTING_LINK_WIDTH; + + /* Zero means one lane, each bit activates x2/x4/x8/x16 */ + if (pcie->num_lanes > 1) + val |=3D FIELD_PREP(PCIE_SETTING_LINK_WIDTH, + GENMASK(pcie->num_lanes >> 1, 0)); + }; writel_relaxed(val, pcie->base + PCIE_SETTING_REG); =20 /* Set Link Control 2 (LNKCTL2) speed restriction, if any */ @@ -838,6 +849,7 @@ static int mtk_pcie_parse_port(struct mtk_gen3_pcie *pc= ie) struct device *dev =3D pcie->dev; struct platform_device *pdev =3D to_platform_device(dev); struct resource *regs; + u32 num_lanes; =20 regs =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "pcie-mac"); if (!regs) @@ -883,6 +895,14 @@ static int mtk_pcie_parse_port(struct mtk_gen3_pcie *p= cie) return pcie->num_clks; } =20 + ret =3D of_property_read_u32(dev->of_node, "num-lanes", &num_lanes); + if (ret =3D=3D 0) { + if (num_lanes =3D=3D 0 || num_lanes > 16 || (num_lanes !=3D 1 && num_lan= es % 2)) + dev_warn(dev, "Invalid num-lanes, using controller defaults\n"); + else + pcie->num_lanes =3D num_lanes; + } + return 0; } =20 --=20 2.46.0