From nobody Thu Sep 19 23:14:04 2024 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 62E83158522; Tue, 17 Sep 2024 09:11:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726564300; cv=none; b=YDma2JySgXR2svuHWQel7F2yWNJFkZ3ZPdr3na51yE319fa6UiLDa/D2czzBbuIhaCM+FVLlNWLzlez/AjGxgRKUntGmalqAoNVSk8KMAqLHDkfiZhdz1PBGRZpBQdlX76tYUrbe70q+geLToLUDmEKPOePWXpLDKuw+YvHbbmE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726564300; c=relaxed/simple; bh=DDGjXLDt//obUfmTFGsB6+P0sXaVu0K/ZWJn0M/7/2c=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=nKWx4iGvTn4ec5xuAz11BnxL+2X34H5AiRbLnuy9T9vPjTZ8mi5/w3G3Cicifp/yb0HFvczDfVvk9bdfpe/IocOvGnyKN98KBlX2QH8i1SMmTqv1WfH3/8hXUnuTdgguJyNl3m9kWSlZL0bnH8NKsKYRMdTWDzgggmmKUOutAwU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=FKYBUF4H; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="FKYBUF4H" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1726564296; bh=DDGjXLDt//obUfmTFGsB6+P0sXaVu0K/ZWJn0M/7/2c=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=FKYBUF4HcL6O+OunGAoUQV8jZUV8s911znNM7ipN2CqyUhczbvyp6oDzw6rgAMowP A8lS+hRu+jrk3y6do7aB3ScwnRUx48R9skG+CcDeP98ahDySyfTVfXdVeG9rXMyb19 +/CiE4/ADD3+LgjAbm2dyg2YYjFv+y8PB19YJ4dqhpnrc3VfZSzZ0aVbzb9QdpnXUx zVMZEzokYXH5zVC+5uk7xPybQ9+VKUq7FUb9CMkvkuD1H+2P5gXKNf9Yl1Y0+Lm13J WV6uGcjfB8khggbvxTMdRGJ7IQX0MhMBTKdJNOfWv5pei2NCtB84uND1odAC3QjTGE iDAAN6zYzQZug== Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by bali.collaboradmins.com (Postfix) with ESMTPSA id 367A917E1088; Tue, 17 Sep 2024 11:11:36 +0200 (CEST) From: AngeloGioacchino Del Regno To: linux-pci@vger.kernel.org Cc: ryder.lee@mediatek.com, jianjun.wang@mediatek.com, lpieralisi@kernel.org, kw@linux.com, robh@kernel.org, bhelgaas@google.com, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kernel@collabora.com Subject: [PATCH v2 1/2] PCI: mediatek-gen3: Add support for setting max-link-speed limit Date: Tue, 17 Sep 2024 11:11:31 +0200 Message-ID: <20240917091132.286582-2-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20240917091132.286582-1-angelogioacchino.delregno@collabora.com> References: <20240917091132.286582-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for respecting the max-link-speed devicetree property, forcing a maximum speed (Gen) for a PCI-Express port. Since the MediaTek PCIe Gen3 controllers also expose the maximum supported link speed in the PCIE_BASE_CFG register, if property max-link-speed is specified in devicetree, validate it against the controller capabilities and proceed setting the limitations only if the wanted Gen is lower than the maximum one that is supported by the controller itself (otherwise it makes no sense!). Signed-off-by: AngeloGioacchino Del Regno --- drivers/pci/controller/pcie-mediatek-gen3.c | 55 ++++++++++++++++++++- 1 file changed, 53 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/cont= roller/pcie-mediatek-gen3.c index 66ce4b5d309b..e1d1fb39d5c6 100644 --- a/drivers/pci/controller/pcie-mediatek-gen3.c +++ b/drivers/pci/controller/pcie-mediatek-gen3.c @@ -28,7 +28,11 @@ =20 #include "../pci.h" =20 +#define PCIE_BASE_CFG_REG 0x14 +#define PCIE_BASE_CFG_SPEED_MASK GENMASK(15, 8) + #define PCIE_SETTING_REG 0x80 +#define PCIE_SETTING_GEN_SUPPORT_MASK GENMASK(14, 12) #define PCIE_PCI_IDS_1 0x9c #define PCI_CLASS(class) (class << 8) #define PCIE_RC_MODE BIT(0) @@ -125,6 +129,9 @@ =20 struct mtk_gen3_pcie; =20 +#define PCIE_CONF_LINK2_CTL_STS 0x10b0 +#define PCIE_CONF_LINK2_LCR2_LINK_SPEED GENMASK(3, 0) + /** * struct mtk_gen3_pcie_pdata - differentiate between host generations * @power_up: pcie power_up callback @@ -160,6 +167,7 @@ struct mtk_msi_set { * @phy: PHY controller block * @clks: PCIe clocks * @num_clks: PCIe clocks count for this port + * @max_link_speed: Maximum link speed (PCIe Gen) for this port * @irq: PCIe controller interrupt number * @saved_irq_state: IRQ enable state saved at suspend time * @irq_lock: lock protecting IRQ register access @@ -180,6 +188,7 @@ struct mtk_gen3_pcie { struct phy *phy; struct clk_bulk_data *clks; int num_clks; + u8 max_link_speed; =20 int irq; u32 saved_irq_state; @@ -381,11 +390,27 @@ static int mtk_pcie_startup_port(struct mtk_gen3_pcie= *pcie) int err; u32 val; =20 - /* Set as RC mode */ + /* Set as RC mode and set controller PCIe Gen speed restriction, if any*/ val =3D readl_relaxed(pcie->base + PCIE_SETTING_REG); val |=3D PCIE_RC_MODE; + if (pcie->max_link_speed) { + val &=3D ~PCIE_SETTING_GEN_SUPPORT_MASK; + + /* Can enable link speed support only from Gen2 onwards */ + if (pcie->max_link_speed >=3D 2) + val |=3D FIELD_PREP(PCIE_SETTING_GEN_SUPPORT_MASK, + GENMASK(pcie->max_link_speed - 2, 0)); + } writel_relaxed(val, pcie->base + PCIE_SETTING_REG); =20 + /* Set Link Control 2 (LNKCTL2) speed restriction, if any */ + if (pcie->max_link_speed) { + val =3D readl_relaxed(pcie->base + PCIE_CONF_LINK2_CTL_STS); + val &=3D PCIE_CONF_LINK2_LCR2_LINK_SPEED; + val |=3D FIELD_PREP(PCIE_CONF_LINK2_LCR2_LINK_SPEED, pcie->max_link_spee= d); + writel_relaxed(val, pcie->base + PCIE_CONF_LINK2_CTL_STS); + } + /* Set class code */ val =3D readl_relaxed(pcie->base + PCIE_PCI_IDS_1); val &=3D ~GENMASK(31, 8); @@ -1004,9 +1029,21 @@ static void mtk_pcie_power_down(struct mtk_gen3_pcie= *pcie) reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, pcie->phy_res= ets); } =20 +static int mtk_pcie_get_controller_max_link_speed(struct mtk_gen3_pcie *pc= ie) +{ + u32 val; + int ret; + + val =3D readl_relaxed(pcie->base + PCIE_BASE_CFG_REG); + val =3D FIELD_GET(PCIE_BASE_CFG_SPEED_MASK, val); + ret =3D fls(val); + + return ret > 0 ? ret : -EINVAL; +} + static int mtk_pcie_setup(struct mtk_gen3_pcie *pcie) { - int err; + int max_speed, err; =20 err =3D mtk_pcie_parse_port(pcie); if (err) @@ -1031,6 +1068,20 @@ static int mtk_pcie_setup(struct mtk_gen3_pcie *pcie) if (err) return err; =20 + err =3D of_pci_get_max_link_speed(pcie->dev->of_node); + if (err > 0) { + /* Get the maximum speed supported by the controller */ + max_speed =3D mtk_pcie_get_controller_max_link_speed(pcie); + + /* Set max_link_speed only if the controller supports it */ + if (max_speed >=3D 0 && max_speed <=3D err) { + pcie->max_link_speed =3D err; + dev_dbg(pcie->dev, + "Max controller link speed Gen%u, override to Gen%u", + max_speed, pcie->max_link_speed); + } + } + /* Try link up */ err =3D mtk_pcie_startup_port(pcie); if (err) --=20 2.46.0