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[82.51.105.30]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a90612e1a55sm430745166b.157.2024.09.17.04.14.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Sep 2024 04:14:16 -0700 (PDT) From: Antonino Maniscalco Date: Tue, 17 Sep 2024 13:14:11 +0200 Subject: [PATCH v4 01/11] drm/msm: Fix bv_fence being used as bv_rptr Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240917-preemption-a750-t-v4-1-95d48012e0ac@gmail.com> References: <20240917-preemption-a750-t-v4-0-95d48012e0ac@gmail.com> In-Reply-To: <20240917-preemption-a750-t-v4-0-95d48012e0ac@gmail.com> To: Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Jonathan Corbet Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Antonino Maniscalco , Akhil P Oommen , Neil Armstrong X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1726571652; l=1564; i=antomani103@gmail.com; s=20240815; h=from:subject:message-id; bh=V6jkAeJmIPNRJFej3NR/GIrK2ICQj0XykO4lOq0cjkM=; b=8uPB0FH7LZTwiL8pSn6PqMzESFVVqmDiWrjTqy1UsNfeHhJZtkUQjX2qg/TP5hSTOR21VRZt3 PoACEWqiaVkDSINz8O8HZp/5pkQ4sALnF7Cly9ae5qbgXuvdV9ZgOE3 X-Developer-Key: i=antomani103@gmail.com; a=ed25519; pk=0zicFb38tVla+iHRo4kWpOMsmtUrpGBEa7LkFF81lyY= The bv_fence field of rbmemptrs was being used incorrectly as the BV rptr shadow pointer in some places. Add a bv_rptr field and change the code to use that instead. Signed-off-by: Antonino Maniscalco Reviewed-by: Akhil P Oommen Tested-by: Neil Armstrong # on SM8650-QRD Tested-by: Neil Armstrong # on SM8450-HDK Tested-by: Neil Armstrong # on SM8550-QRD --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +- drivers/gpu/drm/msm/msm_ringbuffer.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index bcaec86ac67a..32a4faa93d7f 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -1132,7 +1132,7 @@ static int hw_init(struct msm_gpu *gpu) /* ..which means "always" on A7xx, also for BV shadow */ if (adreno_is_a7xx(adreno_gpu)) { gpu_write64(gpu, REG_A7XX_CP_BV_RB_RPTR_ADDR, - rbmemptr(gpu->rb[0], bv_fence)); + rbmemptr(gpu->rb[0], bv_rptr)); } =20 /* Always come up on rb 0 */ diff --git a/drivers/gpu/drm/msm/msm_ringbuffer.h b/drivers/gpu/drm/msm/msm= _ringbuffer.h index 0d6beb8cd39a..40791b2ade46 100644 --- a/drivers/gpu/drm/msm/msm_ringbuffer.h +++ b/drivers/gpu/drm/msm/msm_ringbuffer.h @@ -31,6 +31,7 @@ struct msm_rbmemptrs { volatile uint32_t rptr; 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[82.51.105.30]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a90612e1a55sm430745166b.157.2024.09.17.04.14.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Sep 2024 04:14:18 -0700 (PDT) From: Antonino Maniscalco Date: Tue, 17 Sep 2024 13:14:12 +0200 Subject: [PATCH v4 02/11] drm/msm/A6XX: Track current_ctx_seqno per ring Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240917-preemption-a750-t-v4-2-95d48012e0ac@gmail.com> References: <20240917-preemption-a750-t-v4-0-95d48012e0ac@gmail.com> In-Reply-To: <20240917-preemption-a750-t-v4-0-95d48012e0ac@gmail.com> To: Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Jonathan Corbet Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Antonino Maniscalco X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1726571652; l=7762; i=antomani103@gmail.com; s=20240815; h=from:subject:message-id; bh=V0P15+a6cDLiwlZrHWu9wIpktg4pJmPIMCVG1h+FwSw=; b=fItI8aLcFqlGvOY9j/1qGOdn3mfMH3NNo5qqe8kwSGiC2WODCftgQtcAOLLmCfIFvcsaehTmV Qa2HJaxiFDxAiuWeEhMlA/2dazBWzu1XBCzEyx3tn0d+h+6rT+rEuuZ X-Developer-Key: i=antomani103@gmail.com; a=ed25519; pk=0zicFb38tVla+iHRo4kWpOMsmtUrpGBEa7LkFF81lyY= With preemption it is not enough to track the current_ctx_seqno globally as execution might switch between rings. This is especially problematic when current_ctx_seqno is used to determine whether a page table switch is necessary as it might lead to security bugs. Track current context per ring. Signed-off-by: Antonino Maniscalco Tested-by: Neil Armstrong # on SM8450-HDK Tested-by: Neil Armstrong # on SM8550-QRD --- drivers/gpu/drm/msm/adreno/a2xx_gpu.c | 2 +- drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 2 +- drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 2 +- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 6 +++--- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 10 ++++++---- drivers/gpu/drm/msm/msm_gpu.c | 2 +- drivers/gpu/drm/msm/msm_gpu.h | 11 ----------- drivers/gpu/drm/msm/msm_ringbuffer.h | 10 ++++++++++ 8 files changed, 23 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a2xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a2xx_gpu.c index 0dc255ddf5ce..379a3d346c30 100644 --- a/drivers/gpu/drm/msm/adreno/a2xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a2xx_gpu.c @@ -22,7 +22,7 @@ static void a2xx_submit(struct msm_gpu *gpu, struct msm_g= em_submit *submit) break; case MSM_SUBMIT_CMD_CTX_RESTORE_BUF: /* ignore if there has not been a ctx switch: */ - if (gpu->cur_ctx_seqno =3D=3D submit->queue->ctx->seqno) + if (ring->cur_ctx_seqno =3D=3D submit->queue->ctx->seqno) break; fallthrough; case MSM_SUBMIT_CMD_BUF: diff --git a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a3xx_gpu.c index 5273dc849838..945fe64f835c 100644 --- a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c @@ -40,7 +40,7 @@ static void a3xx_submit(struct msm_gpu *gpu, struct msm_g= em_submit *submit) break; case MSM_SUBMIT_CMD_CTX_RESTORE_BUF: /* ignore if there has not been a ctx switch: */ - if (gpu->cur_ctx_seqno =3D=3D submit->queue->ctx->seqno) + if (ring->cur_ctx_seqno =3D=3D submit->queue->ctx->seqno) break; fallthrough; case MSM_SUBMIT_CMD_BUF: diff --git a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a4xx_gpu.c index 8b4cdf95f445..50c490b492f0 100644 --- a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c @@ -34,7 +34,7 @@ static void a4xx_submit(struct msm_gpu *gpu, struct msm_g= em_submit *submit) break; case MSM_SUBMIT_CMD_CTX_RESTORE_BUF: /* ignore if there has not been a ctx switch: */ - if (gpu->cur_ctx_seqno =3D=3D submit->queue->ctx->seqno) + if (ring->cur_ctx_seqno =3D=3D submit->queue->ctx->seqno) break; fallthrough; case MSM_SUBMIT_CMD_BUF: diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a5xx_gpu.c index c0b5373e90d7..80b441fe8e3a 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -75,7 +75,7 @@ static void a5xx_submit_in_rb(struct msm_gpu *gpu, struct= msm_gem_submit *submit case MSM_SUBMIT_CMD_IB_TARGET_BUF: break; case MSM_SUBMIT_CMD_CTX_RESTORE_BUF: - if (gpu->cur_ctx_seqno =3D=3D submit->queue->ctx->seqno) + if (ring->cur_ctx_seqno =3D=3D submit->queue->ctx->seqno) break; fallthrough; case MSM_SUBMIT_CMD_BUF: @@ -129,7 +129,7 @@ static void a5xx_submit(struct msm_gpu *gpu, struct msm= _gem_submit *submit) unsigned int i, ibs =3D 0; =20 if (IS_ENABLED(CONFIG_DRM_MSM_GPU_SUDO) && submit->in_rb) { - gpu->cur_ctx_seqno =3D 0; + ring->cur_ctx_seqno =3D 0; a5xx_submit_in_rb(gpu, submit); return; } @@ -164,7 +164,7 @@ static void a5xx_submit(struct msm_gpu *gpu, struct msm= _gem_submit *submit) case MSM_SUBMIT_CMD_IB_TARGET_BUF: break; case MSM_SUBMIT_CMD_CTX_RESTORE_BUF: - if (gpu->cur_ctx_seqno =3D=3D submit->queue->ctx->seqno) + if (ring->cur_ctx_seqno =3D=3D submit->queue->ctx->seqno) break; fallthrough; case MSM_SUBMIT_CMD_BUF: diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index 32a4faa93d7f..6e065500b64d 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -109,7 +109,7 @@ static void a6xx_set_pagetable(struct a6xx_gpu *a6xx_gp= u, u32 asid; u64 memptr =3D rbmemptr(ring, ttbr0); =20 - if (ctx->seqno =3D=3D a6xx_gpu->base.base.cur_ctx_seqno) + if (ctx->seqno =3D=3D ring->cur_ctx_seqno) return; =20 if (msm_iommu_pagetable_params(ctx->aspace->mmu, &ttbr, &asid)) @@ -219,7 +219,7 @@ static void a6xx_submit(struct msm_gpu *gpu, struct msm= _gem_submit *submit) case MSM_SUBMIT_CMD_IB_TARGET_BUF: break; case MSM_SUBMIT_CMD_CTX_RESTORE_BUF: - if (gpu->cur_ctx_seqno =3D=3D submit->queue->ctx->seqno) + if (ring->cur_ctx_seqno =3D=3D submit->queue->ctx->seqno) break; fallthrough; case MSM_SUBMIT_CMD_BUF: @@ -305,7 +305,7 @@ static void a7xx_submit(struct msm_gpu *gpu, struct msm= _gem_submit *submit) case MSM_SUBMIT_CMD_IB_TARGET_BUF: break; case MSM_SUBMIT_CMD_CTX_RESTORE_BUF: - if (gpu->cur_ctx_seqno =3D=3D submit->queue->ctx->seqno) + if (ring->cur_ctx_seqno =3D=3D submit->queue->ctx->seqno) break; fallthrough; case MSM_SUBMIT_CMD_BUF: @@ -843,6 +843,7 @@ static int hw_init(struct msm_gpu *gpu) struct a6xx_gpu *a6xx_gpu =3D to_a6xx_gpu(adreno_gpu); struct a6xx_gmu *gmu =3D &a6xx_gpu->gmu; u64 gmem_range_min; + unsigned int i; int ret; =20 if (!adreno_has_gmu_wrapper(adreno_gpu)) { @@ -1138,7 +1139,8 @@ static int hw_init(struct msm_gpu *gpu) /* Always come up on rb 0 */ a6xx_gpu->cur_ring =3D gpu->rb[0]; =20 - gpu->cur_ctx_seqno =3D 0; + for (i =3D 0; i < gpu->nr_rings; i++) + gpu->rb[i]->cur_ctx_seqno =3D 0; =20 /* Enable the SQE_to start the CP engine */ gpu_write(gpu, REG_A6XX_CP_SQE_CNTL, 1); diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c index 3666b42b4ecd..c063b3896dc1 100644 --- a/drivers/gpu/drm/msm/msm_gpu.c +++ b/drivers/gpu/drm/msm/msm_gpu.c @@ -783,7 +783,7 @@ void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem= _submit *submit) mutex_unlock(&gpu->active_lock); =20 gpu->funcs->submit(gpu, submit); - gpu->cur_ctx_seqno =3D submit->queue->ctx->seqno; + submit->ring->cur_ctx_seqno =3D submit->queue->ctx->seqno; =20 pm_runtime_put(&gpu->pdev->dev); hangcheck_timer_reset(gpu); diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h index 1f02bb9956be..7cabc8480d7c 100644 --- a/drivers/gpu/drm/msm/msm_gpu.h +++ b/drivers/gpu/drm/msm/msm_gpu.h @@ -193,17 +193,6 @@ struct msm_gpu { */ refcount_t sysprof_active; =20 - /** - * cur_ctx_seqno: - * - * The ctx->seqno value of the last context to submit rendering, - * and the one with current pgtables installed (for generations - * that support per-context pgtables). Tracked by seqno rather - * than pointer value to avoid dangling pointers, and cases where - * a ctx can be freed and a new one created with the same address. - */ - int cur_ctx_seqno; - /** * lock: * diff --git a/drivers/gpu/drm/msm/msm_ringbuffer.h b/drivers/gpu/drm/msm/msm= _ringbuffer.h index 40791b2ade46..174f83137a49 100644 --- a/drivers/gpu/drm/msm/msm_ringbuffer.h +++ b/drivers/gpu/drm/msm/msm_ringbuffer.h @@ -100,6 +100,16 @@ struct msm_ringbuffer { * preemption. Can be aquired from irq context. */ spinlock_t preempt_lock; + + /** + * cur_ctx_seqno: + * + * The ctx->seqno value of the last context to submit to this ring + * Tracked by seqno rather than pointer value to avoid dangling + * pointers, and cases where a ctx can be freed and a new one created + * with the same address. + */ + int cur_ctx_seqno; }; =20 struct msm_ringbuffer *msm_ringbuffer_new(struct msm_gpu *gpu, int id, --=20 2.46.0 From nobody Fri Nov 29 16:28:56 2024 Received: from mail-ej1-f44.google.com (mail-ej1-f44.google.com [209.85.218.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 77AA21714D8; Tue, 17 Sep 2024 11:14:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.44 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726571664; cv=none; b=JTHIYENeR7+gnC9GFvUOD32d1vW0i5V0Vo3P305DKUD/K0cnkg3DovLXezepeRjrACn/owvGq62H9WLtD5+hyBRPb4e0drLcoDTiYHJvyoxyDQPXNYfMiSVzId/FBiUTmsNVWK0BVmLKkHHVqfslN87+6jRhMasE26jlJBNSwVg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726571664; c=relaxed/simple; bh=xA2R7+V+qAfyd3M9fHuSXLIyku8IvZQlPct7Zfu1oEw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Sskh9A3+SgCWGrFQZLmuIxckKVTEN5V+h0+b2PBMNKgJn9FkR1bxbwUSdISXcaW8nZbZib3naoQZhyf9xijwmCtXrwi9+uXfLLvTHAFiMJ/5YtBcEGncRQONZ2pq0YmTaUB0g3AYOsAz4CT4G7wpeFXB7IG07LeogDJW7AbCVnk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=IlJ5nKzB; arc=none smtp.client-ip=209.85.218.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="IlJ5nKzB" Received: by mail-ej1-f44.google.com with SMTP id a640c23a62f3a-a8d4093722bso778925866b.0; Tue, 17 Sep 2024 04:14:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1726571661; x=1727176461; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=OJMYlnyS1LZRaHdNncK1wWBqiV76KGsJGAYtBN7J5io=; b=IlJ5nKzBNpJqWf7COARMxw936cPesSd/sP+o6OQtDbBCGWmXUqC5Mlp0zGYVzwFf/+ aZIFG3dskh0TLRAdoYt2D2Tfb1ZEfhOGp4/0d4w/sJIRQ5Vp1Y2Wofue0AJHzD9haXWd gNCJPfXDcBtlb3R3XnxQeYhvLikuFgJVDruUBl51OmEsewMbZ6YHwqkErB0TpUtk/bzx 4m8JGeKOFL3bcwRXrOTRb9n8kZHOb+F9VOjxes8NH1UhLzeHuAwovx+jREQyW12wZeZL kdVO4wFRc6xripKAwGMs2q2XxJsVYJo5RaANojMV1inWYz6ySAiEnNeBhFHBbA8dboWc 0KOg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726571661; x=1727176461; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OJMYlnyS1LZRaHdNncK1wWBqiV76KGsJGAYtBN7J5io=; b=MBAs4dPPSpXIp4rPhWZ2TsBNvZIReCIogm5dSo92UgUDR4G9kTim4l35sOUTIvhKvO gTEduYaqSdHbV1CFtRowU1yyo1CqixSecH0evdzo+6Z177QA7Cy67K+mQWHxlmHJmdmJ VK1T9Apv07zjIe73ntdV9fCV0t3bOL6fCa0+V00aTs4Lj+1e7ZC0ohMpM1c7uFeGV00l TiPwEkM89WdkSy0eLi5ZUd98RkSRc7xwYu+uDBnf5friZ29gtX6oml9+1tzfwNfcah+4 LtQoNP0S1DkloE6Kj9zDF+9zUHq/8sgAo3mTVe2tvd52Ljayz4zvqvlKbNCLWmwDAk+o V8Gg== X-Forwarded-Encrypted: i=1; AJvYcCVfqjrqJf4f9CTYWEf6Po/IDwmFGTamK6wnSOq/F2k5DNxPZkwpe+D6+XpwKjwKoHXscqKg17js4ZgZ4VyE@vger.kernel.org, AJvYcCXkal8VG7Dr++WxIi2uaHn5jhC2l0Wo5WtaNLkxPLNITGifkZP9JoLKAQIHxXYw27pAGOlx7apT+GU=@vger.kernel.org X-Gm-Message-State: AOJu0YzDMMshe9j93hRMeHNJILbUn3buLmM9hDz5XZ8ISzDx5tjBBmz0 okAINqve92DmHLB+OkTuflZYEqqxCXtDUqpLl6PwQWEDecsP/Ryz X-Google-Smtp-Source: AGHT+IE8z5aVwlOc9iGi4Y4TMmapv34hJLB0tZlzJM+QSdbd9q/583IQr+kTvYfVBfS4mqbYuVvrew== X-Received: by 2002:a17:907:6e88:b0:a86:7b71:7b74 with SMTP id a640c23a62f3a-a90296789b0mr2225124366b.55.1726571660336; Tue, 17 Sep 2024 04:14:20 -0700 (PDT) Received: from [192.168.1.17] (host-82-51-105-30.retail.telecomitalia.it. [82.51.105.30]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a90612e1a55sm430745166b.157.2024.09.17.04.14.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Sep 2024 04:14:19 -0700 (PDT) From: Antonino Maniscalco Date: Tue, 17 Sep 2024 13:14:13 +0200 Subject: [PATCH v4 03/11] drm/msm: Add a `preempt_record_size` field Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240917-preemption-a750-t-v4-3-95d48012e0ac@gmail.com> References: <20240917-preemption-a750-t-v4-0-95d48012e0ac@gmail.com> In-Reply-To: <20240917-preemption-a750-t-v4-0-95d48012e0ac@gmail.com> To: Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Jonathan Corbet Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Antonino Maniscalco , Akhil P Oommen , Neil Armstrong X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1726571652; l=2182; i=antomani103@gmail.com; s=20240815; h=from:subject:message-id; bh=xA2R7+V+qAfyd3M9fHuSXLIyku8IvZQlPct7Zfu1oEw=; b=b3QMWPdvUro0RG0S1sUpKNLT+ur6G1ARTv9UYcpbY0iLkKkrGUxFa439U3BXNgLIXwbTC0PSo XWvSHZhlz6pAQOtBHxenEOqRHCjGZnCX54zMrv+ISKm4hFx9UZnrvAs X-Developer-Key: i=antomani103@gmail.com; a=ed25519; pk=0zicFb38tVla+iHRo4kWpOMsmtUrpGBEa7LkFF81lyY= Adds a field to `adreno_info` to store the GPU specific preempt record size. Signed-off-by: Antonino Maniscalco Reviewed-by: Akhil P Oommen Tested-by: Neil Armstrong # on SM8650-QRD Tested-by: Neil Armstrong # on SM8450-HDK Tested-by: Neil Armstrong # on SM8550-QRD --- drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 4 ++++ drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 + 2 files changed, 5 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/ms= m/adreno/a6xx_catalog.c index 68ba9aed5506..316f23ca9167 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c @@ -1190,6 +1190,7 @@ static const struct adreno_info a7xx_gpus[] =3D { .protect =3D &a730_protect, }, .address_space_size =3D SZ_16G, + .preempt_record_size =3D 2860 * SZ_1K, }, { .chip_ids =3D ADRENO_CHIP_IDS(0x43050a01), /* "C510v2" */ .family =3D ADRENO_7XX_GEN2, @@ -1209,6 +1210,7 @@ static const struct adreno_info a7xx_gpus[] =3D { .gmu_chipid =3D 0x7020100, }, .address_space_size =3D SZ_16G, + .preempt_record_size =3D 4192 * SZ_1K, }, { .chip_ids =3D ADRENO_CHIP_IDS(0x43050c01), /* "C512v2" */ .family =3D ADRENO_7XX_GEN2, @@ -1227,6 +1229,7 @@ static const struct adreno_info a7xx_gpus[] =3D { .gmu_chipid =3D 0x7050001, }, .address_space_size =3D SZ_256G, + .preempt_record_size =3D 4192 * SZ_1K, }, { .chip_ids =3D ADRENO_CHIP_IDS(0x43051401), /* "C520v2" */ .family =3D ADRENO_7XX_GEN3, @@ -1245,6 +1248,7 @@ static const struct adreno_info a7xx_gpus[] =3D { .gmu_chipid =3D 0x7090100, }, .address_space_size =3D SZ_16G, + .preempt_record_size =3D 3572 * SZ_1K, } }; DECLARE_ADRENO_GPULIST(a7xx); diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/= adreno/adreno_gpu.h index 1ab523a163a0..6b1888280a83 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -111,6 +111,7 @@ struct adreno_info { * {SHRT_MAX, 0} sentinal. */ struct adreno_speedbin *speedbins; + u64 preempt_record_size; }; =20 #define ADRENO_CHIP_IDS(tbl...) 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[82.51.105.30]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a90612e1a55sm430745166b.157.2024.09.17.04.14.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Sep 2024 04:14:21 -0700 (PDT) From: Antonino Maniscalco Date: Tue, 17 Sep 2024 13:14:14 +0200 Subject: [PATCH v4 04/11] drm/msm: Add CONTEXT_SWITCH_CNTL bitfields Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240917-preemption-a750-t-v4-4-95d48012e0ac@gmail.com> References: <20240917-preemption-a750-t-v4-0-95d48012e0ac@gmail.com> In-Reply-To: <20240917-preemption-a750-t-v4-0-95d48012e0ac@gmail.com> To: Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Jonathan Corbet Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Antonino Maniscalco X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1726571652; l=1210; i=antomani103@gmail.com; s=20240815; h=from:subject:message-id; bh=oUM/CI16gozvDWhTcSfQS9qAoH2wC/uZWKXcoKsNOYo=; b=2VCI1aS4Z608h4Pi8Gj+VwTsW96XSeLQLdg0E8YySWBTbyreJtftTWlxqeZG4DnDHwcxzZkUb LOdjawpPx98DHEwkwqrEnzluBHfkfs8CBILQYtp77Hwt4fB2dM6H8KJ X-Developer-Key: i=antomani103@gmail.com; a=ed25519; pk=0zicFb38tVla+iHRo4kWpOMsmtUrpGBEa7LkFF81lyY= Add missing bitfields to CONTEXT_SWITCH_CNTL in a6xx.xml. Signed-off-by: Antonino Maniscalco Tested-by: Neil Armstrong # on SM8450-HDK Tested-by: Neil Armstrong # on SM8550-QRD --- drivers/gpu/drm/msm/registers/adreno/a6xx.xml | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/registers/adreno/a6xx.xml b/drivers/gpu/dr= m/msm/registers/adreno/a6xx.xml index 2dfe6913ab4f..fd31d1d7a11e 100644 --- a/drivers/gpu/drm/msm/registers/adreno/a6xx.xml +++ b/drivers/gpu/drm/msm/registers/adreno/a6xx.xml @@ -1337,7 +1337,12 @@ to upconvert to 32b float internally? =20 - + + + + + + --=20 2.46.0 From nobody Fri Nov 29 16:28:56 2024 Received: from mail-ej1-f49.google.com (mail-ej1-f49.google.com [209.85.218.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 909DE176227; Tue, 17 Sep 2024 11:14:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726571668; cv=none; b=u3q8aqBG8VO2dCWDtSfU1ZbYyey5J0I9jzMjafB156zdEWTe96WNESE8Op4c5TxBhxF80UZGEM3lR74YZiJTfEeJsNBxqRjfTdFFchWcO0vGwRfeWZsohhrerC+oIOcFATtx/OSO9D42Klbvi+sS6QYG6X2qj4Vu2Z+udpgWxjI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726571668; c=relaxed/simple; bh=ayZZCwGjkw/oMh5/38xPta2YZ0v6YgCV3uduR2qC3M4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ek4/sIs5jttLr6X0WAEooGgZxIoHsOSA4R5hqlRUQt9I8H/rD0oKyQNQs0gieww/MrTQ+saCxrQ1On8Xog49M7ucfbF2pmiLlhxgCm+KXawjxlmaJzjFswCSqo+ILnxrHs860MQFC9NgFxb5U7zbwac4W1/KkiY+UfsIlKa8yaA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=WwpPfUx9; arc=none smtp.client-ip=209.85.218.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="WwpPfUx9" Received: by mail-ej1-f49.google.com with SMTP id a640c23a62f3a-a86e9db75b9so859564266b.1; Tue, 17 Sep 2024 04:14:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1726571664; x=1727176464; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=FGmavIcR/01TPphLqBKzplDUaCSjadp450T/U8xEH80=; b=WwpPfUx9BHMb41VeMmRsHM817LcnozKtyeSkbMa/K1iZYT5S+8qgKNY57P988oJ+AQ kHz6dIqTqnxJnXknNGDdvemTPo2nFNQxQ4/7HLH0sZhONGFCKR/H00YiE7ZTgvLCOwOx 49rDp/DY4FgsZI7/5IXThWWPEzlVSQMFdE32mf+ddlFzlfJ7mDDeM6s7pIaQAbvmzZKO JHdEGRXdc8B1g1WShE86qDH1lJdZxZsas7Q+n3o1ak6w7bePuPS5uPvYlcgkue4rmYF0 p0rzK/IK9zeXs4agF9juXv1vket1PYgJjNK878AeHdKrtrlxU8Pe92ryGkvVWe4iMTkh bsag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726571664; x=1727176464; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FGmavIcR/01TPphLqBKzplDUaCSjadp450T/U8xEH80=; b=tPSjH7SN9e7H0yijhhtTBMVNyfO1UaiRLsAiR2yK4SBndMTRfhdKUDsVrXdZs8SCTe E+ltQU28EHwpmrVN8qBXadMpvG11AvUDjdT0ANnXVm0ZHGXrLaGfmOUSjIlkE3DqOws3 P8B5+CyANP5IYU+Lfq2FlKYzALfCirLNwis0PlxOWjXl8h5ZEJoEXKaRLGNtMDqTZU3h dvLNSK8bkCmcEX1qWTj3pkspw2P8DP5veGFdvF5ARi8JWBaj4xtDc54ugxljy/znxRt2 Eg9O9L2OBSCpcX/iv0pfVRKwFJM+RPlnpTClrAdnmnB4uYYF1xEIgnX44bhuzbSyUpRm +DbA== X-Forwarded-Encrypted: i=1; AJvYcCVdywjLy4b3P1DU2AcBl4afs6AXKeK4YvRBmyqftJgHOhS8cbHrAE+by3dl1Bq2fYLuHOrn+LJhNh41Ic+9@vger.kernel.org, AJvYcCWR4+ALDTHe6yQSHDRx+5yK0bii47PfVdAzLrWvySb+lKjPezt47+WqU+3wZ/nxvPt72B+WfpMvnlQ=@vger.kernel.org X-Gm-Message-State: AOJu0YxNjlVN7jjUieMJvudJoREXTTVY5YDp3ypYkHqAHeuyaj/WRo7L G1IHuOBMwTOixS63aIKwEGFpboLSq6yyqQkkqtmSsslm6G/gGQaF X-Google-Smtp-Source: AGHT+IHR//CDXkW5pX/ElrY5875DerBiwDTtrgw6HSt4va8p++JwqvzxSKKN6cMAC1T3Ba8P5oJo/g== X-Received: by 2002:a17:907:944f:b0:a8d:4db8:9eed with SMTP id a640c23a62f3a-a90296eab80mr2014191466b.51.1726571663630; Tue, 17 Sep 2024 04:14:23 -0700 (PDT) Received: from [192.168.1.17] (host-82-51-105-30.retail.telecomitalia.it. [82.51.105.30]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a90612e1a55sm430745166b.157.2024.09.17.04.14.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Sep 2024 04:14:23 -0700 (PDT) From: Antonino Maniscalco Date: Tue, 17 Sep 2024 13:14:15 +0200 Subject: [PATCH v4 05/11] drm/msm/A6xx: Implement preemption for A7XX targets Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240917-preemption-a750-t-v4-5-95d48012e0ac@gmail.com> References: <20240917-preemption-a750-t-v4-0-95d48012e0ac@gmail.com> In-Reply-To: <20240917-preemption-a750-t-v4-0-95d48012e0ac@gmail.com> To: Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Jonathan Corbet Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Antonino Maniscalco , Sharat Masetty , Neil Armstrong X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1726571652; l=34481; i=antomani103@gmail.com; s=20240815; h=from:subject:message-id; bh=ayZZCwGjkw/oMh5/38xPta2YZ0v6YgCV3uduR2qC3M4=; b=SJNE3etC01pxsVgJYNXNSv7/8ayhOGqCPfscpCerQjD0Vn+j/uNHJqDXptkQN6psd6mINe9rX X+G35QffPhyBv8lAcvkEC5ly+Rfi6+pOjgpbUvMc2uhH39yykbuQy4+ X-Developer-Key: i=antomani103@gmail.com; a=ed25519; pk=0zicFb38tVla+iHRo4kWpOMsmtUrpGBEa7LkFF81lyY= This patch implements preemption feature for A6xx targets, this allows the GPU to switch to a higher priority ringbuffer if one is ready. A6XX hardware as such supports multiple levels of preemption granularities, ranging from coarse grained(ringbuffer level) to a more fine grained such as draw-call level or a bin boundary level preemption. This patch enables the basic preemption level, with more fine grained preemption support to follow. Signed-off-by: Sharat Masetty Signed-off-by: Antonino Maniscalco Tested-by: Neil Armstrong # on SM8650-QRD Reviewed-by: Akhil P Oommen Tested-by: Neil Armstrong # on SM8450-HDK Tested-by: Neil Armstrong # on SM8550-QRD --- drivers/gpu/drm/msm/Makefile | 1 + drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 283 +++++++++++++++++++++- drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 168 +++++++++++++ drivers/gpu/drm/msm/adreno/a6xx_preempt.c | 377 ++++++++++++++++++++++++++= ++++ drivers/gpu/drm/msm/msm_ringbuffer.h | 7 + 5 files changed, 825 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile index f5e2838c6a76..32e915109a59 100644 --- a/drivers/gpu/drm/msm/Makefile +++ b/drivers/gpu/drm/msm/Makefile @@ -23,6 +23,7 @@ adreno-y :=3D \ adreno/a6xx_gpu.o \ adreno/a6xx_gmu.o \ adreno/a6xx_hfi.o \ + adreno/a6xx_preempt.o \ =20 adreno-$(CONFIG_DEBUG_FS) +=3D adreno/a5xx_debugfs.o \ =20 diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index 6e065500b64d..355a3e210335 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -16,6 +16,84 @@ =20 #define GPU_PAS_ID 13 =20 +/* IFPC & Preemption static powerup restore list */ +static const uint32_t a7xx_pwrup_reglist[] =3D { + REG_A6XX_UCHE_TRAP_BASE, + REG_A6XX_UCHE_TRAP_BASE + 1, + REG_A6XX_UCHE_WRITE_THRU_BASE, + REG_A6XX_UCHE_WRITE_THRU_BASE + 1, + REG_A6XX_UCHE_GMEM_RANGE_MIN, + REG_A6XX_UCHE_GMEM_RANGE_MIN + 1, + REG_A6XX_UCHE_GMEM_RANGE_MAX, + REG_A6XX_UCHE_GMEM_RANGE_MAX + 1, + REG_A6XX_UCHE_CACHE_WAYS, + REG_A6XX_UCHE_MODE_CNTL, + REG_A6XX_RB_NC_MODE_CNTL, + REG_A6XX_RB_CMP_DBG_ECO_CNTL, + REG_A7XX_GRAS_NC_MODE_CNTL, + REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE, + REG_A6XX_UCHE_GBIF_GX_CONFIG, + REG_A6XX_UCHE_CLIENT_PF, + REG_A6XX_TPL1_DBG_ECO_CNTL1, +}; + +static const uint32_t a7xx_ifpc_pwrup_reglist[] =3D { + REG_A6XX_TPL1_NC_MODE_CNTL, + REG_A6XX_SP_NC_MODE_CNTL, + REG_A6XX_CP_DBG_ECO_CNTL, + REG_A6XX_CP_PROTECT_CNTL, + REG_A6XX_CP_PROTECT(0), + REG_A6XX_CP_PROTECT(1), + REG_A6XX_CP_PROTECT(2), + REG_A6XX_CP_PROTECT(3), + REG_A6XX_CP_PROTECT(4), + REG_A6XX_CP_PROTECT(5), + REG_A6XX_CP_PROTECT(6), + REG_A6XX_CP_PROTECT(7), + REG_A6XX_CP_PROTECT(8), + REG_A6XX_CP_PROTECT(9), + REG_A6XX_CP_PROTECT(10), + REG_A6XX_CP_PROTECT(11), + REG_A6XX_CP_PROTECT(12), + REG_A6XX_CP_PROTECT(13), + REG_A6XX_CP_PROTECT(14), + REG_A6XX_CP_PROTECT(15), + REG_A6XX_CP_PROTECT(16), + REG_A6XX_CP_PROTECT(17), + REG_A6XX_CP_PROTECT(18), + REG_A6XX_CP_PROTECT(19), + REG_A6XX_CP_PROTECT(20), + REG_A6XX_CP_PROTECT(21), + REG_A6XX_CP_PROTECT(22), + REG_A6XX_CP_PROTECT(23), + REG_A6XX_CP_PROTECT(24), + REG_A6XX_CP_PROTECT(25), + REG_A6XX_CP_PROTECT(26), + REG_A6XX_CP_PROTECT(27), + REG_A6XX_CP_PROTECT(28), + REG_A6XX_CP_PROTECT(29), + REG_A6XX_CP_PROTECT(30), + REG_A6XX_CP_PROTECT(31), + REG_A6XX_CP_PROTECT(32), + REG_A6XX_CP_PROTECT(33), + REG_A6XX_CP_PROTECT(34), + REG_A6XX_CP_PROTECT(35), + REG_A6XX_CP_PROTECT(36), + REG_A6XX_CP_PROTECT(37), + REG_A6XX_CP_PROTECT(38), + REG_A6XX_CP_PROTECT(39), + REG_A6XX_CP_PROTECT(40), + REG_A6XX_CP_PROTECT(41), + REG_A6XX_CP_PROTECT(42), + REG_A6XX_CP_PROTECT(43), + REG_A6XX_CP_PROTECT(44), + REG_A6XX_CP_PROTECT(45), + REG_A6XX_CP_PROTECT(46), + REG_A6XX_CP_PROTECT(47), + REG_A6XX_CP_AHB_CNTL, +}; + + static inline bool _a6xx_check_idle(struct msm_gpu *gpu) { struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); @@ -68,6 +146,8 @@ static void update_shadow_rptr(struct msm_gpu *gpu, stru= ct msm_ringbuffer *ring) =20 static void a6xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring) { + struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); + struct a6xx_gpu *a6xx_gpu =3D to_a6xx_gpu(adreno_gpu); uint32_t wptr; unsigned long flags; =20 @@ -81,12 +161,17 @@ static void a6xx_flush(struct msm_gpu *gpu, struct msm= _ringbuffer *ring) /* Make sure to wrap wptr if we need to */ wptr =3D get_wptr(ring); =20 - spin_unlock_irqrestore(&ring->preempt_lock, flags); - - /* Make sure everything is posted before making a decision */ - mb(); + /* Update HW if this is the current ring and we are not in preempt*/ + if (!a6xx_in_preempt(a6xx_gpu)) { + if (a6xx_gpu->cur_ring =3D=3D ring) + gpu_write(gpu, REG_A6XX_CP_RB_WPTR, wptr); + else + ring->restore_wptr =3D true; + } else { + ring->restore_wptr =3D true; + } =20 - gpu_write(gpu, REG_A6XX_CP_RB_WPTR, wptr); + spin_unlock_irqrestore(&ring->preempt_lock, flags); } =20 static void get_stats_counter(struct msm_ringbuffer *ring, u32 counter, @@ -138,12 +223,14 @@ static void a6xx_set_pagetable(struct a6xx_gpu *a6xx_= gpu, =20 /* * Write the new TTBR0 to the memstore. This is good for debugging. + * Needed for preemption */ - OUT_PKT7(ring, CP_MEM_WRITE, 4); + OUT_PKT7(ring, CP_MEM_WRITE, 5); OUT_RING(ring, CP_MEM_WRITE_0_ADDR_LO(lower_32_bits(memptr))); OUT_RING(ring, CP_MEM_WRITE_1_ADDR_HI(upper_32_bits(memptr))); OUT_RING(ring, lower_32_bits(ttbr)); - OUT_RING(ring, (asid << 16) | upper_32_bits(ttbr)); + OUT_RING(ring, upper_32_bits(ttbr)); + OUT_RING(ring, ctx->seqno); =20 /* * Sync both threads after switching pagetables and enable BR only @@ -268,6 +355,34 @@ static void a6xx_submit(struct msm_gpu *gpu, struct ms= m_gem_submit *submit) a6xx_flush(gpu, ring); } =20 +static void a6xx_emit_set_pseudo_reg(struct msm_ringbuffer *ring, + struct a6xx_gpu *a6xx_gpu, struct msm_gpu_submitqueue *queue) +{ + OUT_PKT7(ring, CP_SET_PSEUDO_REG, 12); + + OUT_RING(ring, SMMU_INFO); + /* don't save SMMU, we write the record from the kernel instead */ + OUT_RING(ring, 0); + OUT_RING(ring, 0); + + /* privileged and non secure buffer save */ + OUT_RING(ring, NON_SECURE_SAVE_ADDR); + OUT_RING(ring, lower_32_bits( + a6xx_gpu->preempt_iova[ring->id] + PREEMPT_OFFSET_PRIV_NON_SECURE)); + OUT_RING(ring, upper_32_bits( + a6xx_gpu->preempt_iova[ring->id] + PREEMPT_OFFSET_PRIV_NON_SECURE)); + + /* user context buffer save, seems to be unnused by fw */ + OUT_RING(ring, NON_PRIV_SAVE_ADDR); + OUT_RING(ring, 0); + OUT_RING(ring, 0); + + OUT_RING(ring, COUNTER); + /* seems OK to set to 0 to disable it */ + OUT_RING(ring, 0); + OUT_RING(ring, 0); +} + static void a7xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) { unsigned int index =3D submit->seqno % MSM_GPU_SUBMIT_STATS_COUNT; @@ -285,6 +400,13 @@ static void a7xx_submit(struct msm_gpu *gpu, struct ms= m_gem_submit *submit) =20 a6xx_set_pagetable(a6xx_gpu, ring, submit->queue->ctx); =20 + /* + * If preemption is enabled, then set the pseudo register for the save + * sequence + */ + if (gpu->nr_rings > 1) + a6xx_emit_set_pseudo_reg(ring, a6xx_gpu, submit->queue); + get_stats_counter(ring, REG_A7XX_RBBM_PERFCTR_CP(0), rbmemptr_stats(ring, index, cpcycles_start)); get_stats_counter(ring, REG_A6XX_CP_ALWAYS_ON_COUNTER, @@ -376,6 +498,8 @@ static void a7xx_submit(struct msm_gpu *gpu, struct msm= _gem_submit *submit) OUT_RING(ring, upper_32_bits(rbmemptr(ring, bv_fence))); OUT_RING(ring, submit->seqno); =20 + a6xx_gpu->last_seqno[ring->id] =3D submit->seqno; + /* write the ringbuffer timestamp */ OUT_PKT7(ring, CP_EVENT_WRITE, 4); OUT_RING(ring, CACHE_CLEAN | CP_EVENT_WRITE_0_IRQ | BIT(27)); @@ -389,10 +513,32 @@ static void a7xx_submit(struct msm_gpu *gpu, struct m= sm_gem_submit *submit) OUT_PKT7(ring, CP_SET_MARKER, 1); OUT_RING(ring, 0x100); /* IFPC enable */ =20 + /* If preemption is enabled */ + if (gpu->nr_rings > 1) { + /* Yield the floor on command completion */ + OUT_PKT7(ring, CP_CONTEXT_SWITCH_YIELD, 4); + + /* + * If dword[2:1] are non zero, they specify an address for + * the CP to write the value of dword[3] to on preemption + * complete. Write 0 to skip the write + */ + OUT_RING(ring, 0x00); + OUT_RING(ring, 0x00); + /* Data value - not used if the address above is 0 */ + OUT_RING(ring, 0x01); + /* generate interrupt on preemption completion */ + OUT_RING(ring, 0x00); + } + + trace_msm_gpu_submit_flush(submit, gpu_read64(gpu, REG_A6XX_CP_ALWAYS_ON_COUNTER)); =20 a6xx_flush(gpu, ring); + + /* Check to see if we need to start preemption */ + a6xx_preempt_trigger(gpu); } =20 static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state) @@ -588,6 +734,89 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) adreno_gpu->ubwc_config.min_acc_len << 23 | hbb_lo << 21); } =20 +static void a7xx_patch_pwrup_reglist(struct msm_gpu *gpu) +{ + struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); + struct a6xx_gpu *a6xx_gpu =3D to_a6xx_gpu(adreno_gpu); + struct adreno_reglist_list reglist[2]; + void *ptr =3D a6xx_gpu->pwrup_reglist_ptr; + struct cpu_gpu_lock *lock =3D ptr; + u32 *dest =3D (u32 *)&lock->regs[0]; + int i, j; + + lock->gpu_req =3D lock->cpu_req =3D lock->turn =3D 0; + lock->ifpc_list_len =3D ARRAY_SIZE(a7xx_ifpc_pwrup_reglist); + lock->preemption_list_len =3D ARRAY_SIZE(a7xx_pwrup_reglist); + + /* Static IFPC-only registers */ + reglist[0].regs =3D a7xx_ifpc_pwrup_reglist; + reglist[0].count =3D ARRAY_SIZE(a7xx_ifpc_pwrup_reglist); + lock->ifpc_list_len =3D reglist[0].count; + + /* Static IFPC + preemption registers */ + reglist[1].regs =3D a7xx_pwrup_reglist; + reglist[1].count =3D ARRAY_SIZE(a7xx_pwrup_reglist); + lock->preemption_list_len =3D reglist[1].count; + + /* + * For each entry in each of the lists, write the offset and the current + * register value into the GPU buffer + */ + for (i =3D 0; i < 2; i++) { + const u32 *r =3D reglist[i].regs; + + for (j =3D 0; j < reglist[i].count; j++) { + *dest++ =3D r[j]; + *dest++ =3D gpu_read(gpu, r[j]); + } + } + + /* + * The overall register list is composed of + * 1. Static IFPC-only registers + * 2. Static IFPC + preemption registers + * 3. Dynamic IFPC + preemption registers (ex: perfcounter selects) + * + * The first two lists are static. Size of these lists are stored as + * number of pairs in ifpc_list_len and preemption_list_len + * respectively. With concurrent binning, Some of the perfcounter + * registers being virtualized, CP needs to know the pipe id to program + * the aperture inorder to restore the same. Thus, third list is a + * dynamic list with triplets as + * (
), and the length is + * stored as number for triplets in dynamic_list_len. + */ + lock->dynamic_list_len =3D 0; +} + +static int a7xx_preempt_start(struct msm_gpu *gpu) +{ + struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); + struct a6xx_gpu *a6xx_gpu =3D to_a6xx_gpu(adreno_gpu); + struct msm_ringbuffer *ring =3D gpu->rb[0]; + + if (gpu->nr_rings <=3D 1) + return 0; + + /* Turn CP protection off */ + OUT_PKT7(ring, CP_SET_PROTECTED_MODE, 1); + OUT_RING(ring, 0); + + a6xx_emit_set_pseudo_reg(ring, a6xx_gpu, NULL); + + /* Yield the floor on command completion */ + OUT_PKT7(ring, CP_CONTEXT_SWITCH_YIELD, 4); + OUT_RING(ring, 0x00); + OUT_RING(ring, 0x00); + OUT_RING(ring, 0x00); + /* Generate interrupt on preemption completion */ + OUT_RING(ring, 0x00); + + a6xx_flush(gpu, ring); + + return a6xx_idle(gpu, ring) ? 0 : -EINVAL; +} + static int a6xx_cp_init(struct msm_gpu *gpu) { struct msm_ringbuffer *ring =3D gpu->rb[0]; @@ -619,6 +848,8 @@ static int a6xx_cp_init(struct msm_gpu *gpu) =20 static int a7xx_cp_init(struct msm_gpu *gpu) { + struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); + struct a6xx_gpu *a6xx_gpu =3D to_a6xx_gpu(adreno_gpu); struct msm_ringbuffer *ring =3D gpu->rb[0]; u32 mask; =20 @@ -656,11 +887,11 @@ static int a7xx_cp_init(struct msm_gpu *gpu) =20 /* *Don't* send a power up reg list for concurrent binning (TODO) */ /* Lo address */ - OUT_RING(ring, 0x00000000); + OUT_RING(ring, lower_32_bits(a6xx_gpu->pwrup_reglist_iova)); /* Hi address */ - OUT_RING(ring, 0x00000000); + OUT_RING(ring, upper_32_bits(a6xx_gpu->pwrup_reglist_iova)); /* BIT(31) set =3D> read the regs from the list */ - OUT_RING(ring, 0x00000000); + OUT_RING(ring, BIT(31)); =20 a6xx_flush(gpu, ring); return a6xx_idle(gpu, ring) ? 0 : -EINVAL; @@ -784,6 +1015,16 @@ static int a6xx_ucode_load(struct msm_gpu *gpu) msm_gem_object_set_name(a6xx_gpu->shadow_bo, "shadow"); } =20 + a6xx_gpu->pwrup_reglist_ptr =3D msm_gem_kernel_new(gpu->dev, PAGE_SIZE, + MSM_BO_WC | MSM_BO_MAP_PRIV, + gpu->aspace, &a6xx_gpu->pwrup_reglist_bo, + &a6xx_gpu->pwrup_reglist_iova); + + if (IS_ERR(a6xx_gpu->pwrup_reglist_ptr)) + return PTR_ERR(a6xx_gpu->pwrup_reglist_ptr); + + msm_gem_object_set_name(a6xx_gpu->pwrup_reglist_bo, "pwrup_reglist"); + return 0; } =20 @@ -1128,6 +1369,8 @@ static int hw_init(struct msm_gpu *gpu) if (a6xx_gpu->shadow_bo) { gpu_write64(gpu, REG_A6XX_CP_RB_RPTR_ADDR, shadowptr(a6xx_gpu, gpu->rb[0])); + for (unsigned int i =3D 0; i < gpu->nr_rings; i++) + a6xx_gpu->shadow[i] =3D 0; } =20 /* ..which means "always" on A7xx, also for BV shadow */ @@ -1136,6 +1379,8 @@ static int hw_init(struct msm_gpu *gpu) rbmemptr(gpu->rb[0], bv_rptr)); } =20 + a6xx_preempt_hw_init(gpu); + /* Always come up on rb 0 */ a6xx_gpu->cur_ring =3D gpu->rb[0]; =20 @@ -1145,6 +1390,11 @@ static int hw_init(struct msm_gpu *gpu) /* Enable the SQE_to start the CP engine */ gpu_write(gpu, REG_A6XX_CP_SQE_CNTL, 1); =20 + if (adreno_is_a7xx(adreno_gpu) && !a6xx_gpu->pwrup_reglist_emitted) { + a7xx_patch_pwrup_reglist(gpu); + a6xx_gpu->pwrup_reglist_emitted =3D true; + } + ret =3D adreno_is_a7xx(adreno_gpu) ? a7xx_cp_init(gpu) : a6xx_cp_init(gpu= ); if (ret) goto out; @@ -1182,6 +1432,10 @@ static int hw_init(struct msm_gpu *gpu) out: if (adreno_has_gmu_wrapper(adreno_gpu)) return ret; + + /* Last step - yield the ringbuffer */ + a7xx_preempt_start(gpu); + /* * Tell the GMU that we are done touching the GPU and it can start power * management @@ -1559,8 +1813,13 @@ static irqreturn_t a6xx_irq(struct msm_gpu *gpu) if (status & A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION) a7xx_sw_fuse_violation_irq(gpu); =20 - if (status & A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS) + if (status & A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS) { msm_gpu_retire(gpu); + a6xx_preempt_trigger(gpu); + } + + if (status & A6XX_RBBM_INT_0_MASK_CP_SW) + a6xx_preempt_irq(gpu); =20 return IRQ_HANDLED; } @@ -2333,6 +2592,8 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) a6xx_fault_handler); =20 a6xx_calc_ubwc_config(adreno_gpu); + /* Set up the preemption specific bits and pieces for each ringbuffer */ + a6xx_preempt_init(gpu); =20 return gpu; } diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.h index e3e5c53ae8af..7fc994121676 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h @@ -12,6 +12,31 @@ =20 extern bool hang_debug; =20 +struct cpu_gpu_lock { + uint32_t gpu_req; + uint32_t cpu_req; + uint32_t turn; + union { + struct { + uint16_t list_length; + uint16_t list_offset; + }; + struct { + uint8_t ifpc_list_len; + uint8_t preemption_list_len; + uint16_t dynamic_list_len; + }; + }; + uint64_t regs[62]; +}; + +struct adreno_reglist_list { + /** @reg: List of register **/ + const u32 *regs; + /** @count: Number of registers in the list **/ + u32 count; +}; + /** * struct a6xx_info - a6xx specific information from device table * @@ -31,6 +56,20 @@ struct a6xx_gpu { uint64_t sqe_iova; =20 struct msm_ringbuffer *cur_ring; + struct msm_ringbuffer *next_ring; + + struct drm_gem_object *preempt_bo[MSM_GPU_MAX_RINGS]; + void *preempt[MSM_GPU_MAX_RINGS]; + uint64_t preempt_iova[MSM_GPU_MAX_RINGS]; + uint32_t last_seqno[MSM_GPU_MAX_RINGS]; + + atomic_t preempt_state; + spinlock_t eval_lock; + struct timer_list preempt_timer; + + unsigned int preempt_level; + bool uses_gmem; + bool skip_save_restore; =20 struct a6xx_gmu gmu; =20 @@ -38,6 +77,11 @@ struct a6xx_gpu { uint64_t shadow_iova; uint32_t *shadow; =20 + struct drm_gem_object *pwrup_reglist_bo; + void *pwrup_reglist_ptr; + uint64_t pwrup_reglist_iova; + bool pwrup_reglist_emitted; + bool has_whereami; =20 void __iomem *llc_mmio; @@ -49,6 +93,102 @@ struct a6xx_gpu { =20 #define to_a6xx_gpu(x) container_of(x, struct a6xx_gpu, base) =20 +/* + * In order to do lockless preemption we use a simple state machine to pro= gress + * through the process. + * + * PREEMPT_NONE - no preemption in progress. Next state START. + * PREEMPT_START - The trigger is evaluating if preemption is possible. Ne= xt + * states: TRIGGERED, NONE + * PREEMPT_FINISH - An intermediate state before moving back to NONE. Next + * state: NONE. + * PREEMPT_TRIGGERED: A preemption has been executed on the hardware. Next + * states: FAULTED, PENDING + * PREEMPT_FAULTED: A preemption timed out (never completed). This will tr= igger + * recovery. Next state: N/A + * PREEMPT_PENDING: Preemption complete interrupt fired - the callback is + * checking the success of the operation. Next state: FAULTED, NONE. + */ + +enum a6xx_preempt_state { + PREEMPT_NONE =3D 0, + PREEMPT_START, + PREEMPT_FINISH, + PREEMPT_TRIGGERED, + PREEMPT_FAULTED, + PREEMPT_PENDING, +}; + +/* + * struct a6xx_preempt_record is a shared buffer between the microcode and= the + * CPU to store the state for preemption. The record itself is much larger + * (2112k) but most of that is used by the CP for storage. + * + * There is a preemption record assigned per ringbuffer. When the CPU trig= gers a + * preemption, it fills out the record with the useful information (wptr, = ring + * base, etc) and the microcode uses that information to set up the CP fol= lowing + * the preemption. When a ring is switched out, the CP will save the ring= buffer + * state back to the record. In this way, once the records are properly se= t up + * the CPU can quickly switch back and forth between ringbuffers by only + * updating a few registers (often only the wptr). + * + * These are the CPU aware registers in the record: + * @magic: Must always be 0xAE399D6EUL + * @info: Type of the record - written 0 by the CPU, updated by the CP + * @errno: preemption error record + * @data: Data field in YIELD and SET_MARKER packets, Written and used by = CP + * @cntl: Value of RB_CNTL written by CPU, save/restored by CP + * @rptr: Value of RB_RPTR written by CPU, save/restored by CP + * @wptr: Value of RB_WPTR written by CPU, save/restored by CP + * @_pad: Reserved/padding + * @rptr_addr: Value of RB_RPTR_ADDR_LO|HI written by CPU, save/restored b= y CP + * @rbase: Value of RB_BASE written by CPU, save/restored by CP + * @counter: GPU address of the storage area for the preemption counters + * @bv_rptr_addr: Value of BV_RB_RPTR_ADDR_LO|HI written by CPU, save/rest= ored by CP + */ +struct a6xx_preempt_record { + u32 magic; + u32 info; + u32 errno; + u32 data; + u32 cntl; + u32 rptr; + u32 wptr; + u32 _pad; + u64 rptr_addr; + u64 rbase; + u64 counter; + u64 bv_rptr_addr; +}; + +#define A6XX_PREEMPT_RECORD_MAGIC 0xAE399D6EUL + +#define PREEMPT_RECORD_SIZE_FALLBACK(size) \ + ((size) =3D=3D 0 ? 4192 * SZ_1K : (size)) + +#define PREEMPT_OFFSET_SMMU_INFO 0 +#define PREEMPT_OFFSET_PRIV_NON_SECURE (PREEMPT_OFFSET_SMMU_INFO + 4096) +#define PREEMPT_SIZE(size) \ + (PREEMPT_OFFSET_PRIV_NON_SECURE + PREEMPT_RECORD_SIZE_FALLBACK(size)) + +/* + * The preemption counter block is a storage area for the value of the + * preemption counters that are saved immediately before context switch. We + * append it on to the end of the allocation for the preemption record. + */ +#define A6XX_PREEMPT_COUNTER_SIZE (16 * 4) + +struct a7xx_cp_smmu_info { + u32 magic; + u32 _pad4; + u64 ttbr0; + u32 asid; + u32 context_idr; + u32 context_bank; +}; + +#define GEN7_CP_SMMU_INFO_MAGIC 0x241350d5UL + /* * Given a register and a count, return a value to program into * REG_CP_PROTECT_REG(n) - this will block both reads and writes for @@ -106,6 +246,34 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct de= vice_node *node); int a6xx_gmu_wrapper_init(struct a6xx_gpu *a6xx_gpu, struct device_node *n= ode); void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu); =20 +void a6xx_preempt_init(struct msm_gpu *gpu); +void a6xx_preempt_hw_init(struct msm_gpu *gpu); +void a6xx_preempt_trigger(struct msm_gpu *gpu); +void a6xx_preempt_irq(struct msm_gpu *gpu); +void a6xx_preempt_fini(struct msm_gpu *gpu); +int a6xx_preempt_submitqueue_setup(struct msm_gpu *gpu, + struct msm_gpu_submitqueue *queue); +void a6xx_preempt_submitqueue_close(struct msm_gpu *gpu, + struct msm_gpu_submitqueue *queue); + +/* Return true if we are in a preempt state */ +static inline bool a6xx_in_preempt(struct a6xx_gpu *a6xx_gpu) +{ + /* + * Make sure the read to preempt_state is ordered with respect to reads + * of other variables before ... + */ + smp_rmb(); + + int preempt_state =3D atomic_read(&a6xx_gpu->preempt_state); + + /* ... and after. */ + smp_rmb(); + + return !(preempt_state =3D=3D PREEMPT_NONE || + preempt_state =3D=3D PREEMPT_FINISH); +} + void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp, bool suspended); unsigned long a6xx_gmu_get_freq(struct msm_gpu *gpu); diff --git a/drivers/gpu/drm/msm/adreno/a6xx_preempt.c b/drivers/gpu/drm/ms= m/adreno/a6xx_preempt.c new file mode 100644 index 000000000000..aa4bad394f9e --- /dev/null +++ b/drivers/gpu/drm/msm/adreno/a6xx_preempt.c @@ -0,0 +1,377 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. */ +/* Copyright (c) 2023 Collabora, Ltd. */ +/* Copyright (c) 2024 Valve Corporation */ + +#include "msm_gem.h" +#include "a6xx_gpu.h" +#include "a6xx_gmu.xml.h" +#include "msm_mmu.h" + +/* + * Try to transition the preemption state from old to new. Return + * true on success or false if the original state wasn't 'old' + */ +static inline bool try_preempt_state(struct a6xx_gpu *a6xx_gpu, + enum a6xx_preempt_state old, enum a6xx_preempt_state new) +{ + enum a6xx_preempt_state cur =3D atomic_cmpxchg(&a6xx_gpu->preempt_state, + old, new); + + return (cur =3D=3D old); +} + +/* + * Force the preemption state to the specified state. This is used in cas= es + * where the current state is known and won't change + */ +static inline void set_preempt_state(struct a6xx_gpu *gpu, + enum a6xx_preempt_state new) +{ + /* + * preempt_state may be read by other cores trying to trigger a + * preemption or in the interrupt handler so barriers are needed + * before... + */ + smp_mb__before_atomic(); + atomic_set(&gpu->preempt_state, new); + /* ... and after*/ + smp_mb__after_atomic(); +} + +/* Write the most recent wptr for the given ring into the hardware */ +static inline void update_wptr(struct msm_gpu *gpu, struct msm_ringbuffer = *ring) +{ + unsigned long flags; + uint32_t wptr; + + spin_lock_irqsave(&ring->preempt_lock, flags); + + if (ring->restore_wptr) { + wptr =3D get_wptr(ring); + + gpu_write(gpu, REG_A6XX_CP_RB_WPTR, wptr); + + ring->restore_wptr =3D false; + } + + spin_unlock_irqrestore(&ring->preempt_lock, flags); +} + +/* Return the highest priority ringbuffer with something in it */ +static struct msm_ringbuffer *get_next_ring(struct msm_gpu *gpu) +{ + struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); + struct a6xx_gpu *a6xx_gpu =3D to_a6xx_gpu(adreno_gpu); + + unsigned long flags; + int i; + + for (i =3D 0; i < gpu->nr_rings; i++) { + bool empty; + struct msm_ringbuffer *ring =3D gpu->rb[i]; + + spin_lock_irqsave(&ring->preempt_lock, flags); + empty =3D (get_wptr(ring) =3D=3D gpu->funcs->get_rptr(gpu, ring)); + if (!empty && ring =3D=3D a6xx_gpu->cur_ring) + empty =3D ring->memptrs->fence =3D=3D a6xx_gpu->last_seqno[i]; + spin_unlock_irqrestore(&ring->preempt_lock, flags); + + if (!empty) + return ring; + } + + return NULL; +} + +static void a6xx_preempt_timer(struct timer_list *t) +{ + struct a6xx_gpu *a6xx_gpu =3D from_timer(a6xx_gpu, t, preempt_timer); + struct msm_gpu *gpu =3D &a6xx_gpu->base.base; + struct drm_device *dev =3D gpu->dev; + + if (!try_preempt_state(a6xx_gpu, PREEMPT_TRIGGERED, PREEMPT_FAULTED)) + return; + + dev_err(dev->dev, "%s: preemption timed out\n", gpu->name); + kthread_queue_work(gpu->worker, &gpu->recover_work); +} + +void a6xx_preempt_irq(struct msm_gpu *gpu) +{ + uint32_t status; + struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); + struct a6xx_gpu *a6xx_gpu =3D to_a6xx_gpu(adreno_gpu); + struct drm_device *dev =3D gpu->dev; + + if (!try_preempt_state(a6xx_gpu, PREEMPT_TRIGGERED, PREEMPT_PENDING)) + return; + + /* Delete the preemption watchdog timer */ + del_timer(&a6xx_gpu->preempt_timer); + + /* + * The hardware should be setting the stop bit of CP_CONTEXT_SWITCH_CNTL + * to zero before firing the interrupt, but there is a non zero chance + * of a hardware condition or a software race that could set it again + * before we have a chance to finish. If that happens, log and go for + * recovery + */ + status =3D gpu_read(gpu, REG_A6XX_CP_CONTEXT_SWITCH_CNTL); + if (unlikely(status & A6XX_CP_CONTEXT_SWITCH_CNTL_STOP)) { + DRM_DEV_ERROR(&gpu->pdev->dev, + "!!!!!!!!!!!!!!!! preemption faulted !!!!!!!!!!!!!! irq\n"); + set_preempt_state(a6xx_gpu, PREEMPT_FAULTED); + dev_err(dev->dev, "%s: Preemption failed to complete\n", + gpu->name); + kthread_queue_work(gpu->worker, &gpu->recover_work); + return; + } + + a6xx_gpu->cur_ring =3D a6xx_gpu->next_ring; + a6xx_gpu->next_ring =3D NULL; + + set_preempt_state(a6xx_gpu, PREEMPT_FINISH); + + update_wptr(gpu, a6xx_gpu->cur_ring); + + set_preempt_state(a6xx_gpu, PREEMPT_NONE); + + /* + * Retrigger preemption to avoid a deadlock that might occur when preempt= ion + * is skipped due to it being already in flight when requested. + */ + a6xx_preempt_trigger(gpu); +} + +void a6xx_preempt_hw_init(struct msm_gpu *gpu) +{ + struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); + struct a6xx_gpu *a6xx_gpu =3D to_a6xx_gpu(adreno_gpu); + int i; + + /* No preemption if we only have one ring */ + if (gpu->nr_rings =3D=3D 1) + return; + + for (i =3D 0; i < gpu->nr_rings; i++) { + struct a6xx_preempt_record *record_ptr =3D + a6xx_gpu->preempt[i] + PREEMPT_OFFSET_PRIV_NON_SECURE; + record_ptr->wptr =3D 0; + record_ptr->rptr =3D 0; + record_ptr->rptr_addr =3D shadowptr(a6xx_gpu, gpu->rb[i]); + record_ptr->info =3D 0; + record_ptr->data =3D 0; + record_ptr->rbase =3D gpu->rb[i]->iova; + } + + /* Write a 0 to signal that we aren't switching pagetables */ + gpu_write64(gpu, REG_A6XX_CP_CONTEXT_SWITCH_SMMU_INFO, 0); + + /* Enable the GMEM save/restore feature for preemption */ + gpu_write(gpu, REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE, 0x1); + + /* Reset the preemption state */ + set_preempt_state(a6xx_gpu, PREEMPT_NONE); + + spin_lock_init(&a6xx_gpu->eval_lock); + + /* Always come up on rb 0 */ + a6xx_gpu->cur_ring =3D gpu->rb[0]; +} + +void a6xx_preempt_trigger(struct msm_gpu *gpu) +{ + struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); + struct a6xx_gpu *a6xx_gpu =3D to_a6xx_gpu(adreno_gpu); + unsigned long flags; + struct msm_ringbuffer *ring; + unsigned int cntl; + + if (gpu->nr_rings =3D=3D 1) + return; + + /* + * Lock to make sure another thread attempting preemption doesn't skip it + * while we are still evaluating the next ring. This makes sure the other + * thread does start preemption if we abort it and avoids a soft lock. + */ + spin_lock_irqsave(&a6xx_gpu->eval_lock, flags); + + /* + * Try to start preemption by moving from NONE to START. If + * unsuccessful, a preemption is already in flight + */ + if (!try_preempt_state(a6xx_gpu, PREEMPT_NONE, PREEMPT_START)) { + spin_unlock_irqrestore(&a6xx_gpu->eval_lock, flags); + return; + } + + cntl =3D A6XX_CP_CONTEXT_SWITCH_CNTL_LEVEL(a6xx_gpu->preempt_level); + + if (a6xx_gpu->skip_save_restore) + cntl |=3D A6XX_CP_CONTEXT_SWITCH_CNTL_SKIP_SAVE_RESTORE; + + if (a6xx_gpu->uses_gmem) + cntl |=3D A6XX_CP_CONTEXT_SWITCH_CNTL_USES_GMEM; + + cntl |=3D A6XX_CP_CONTEXT_SWITCH_CNTL_STOP; + + /* Get the next ring to preempt to */ + ring =3D get_next_ring(gpu); + + /* + * If no ring is populated or the highest priority ring is the current + * one do nothing except to update the wptr to the latest and greatest + */ + if (!ring || (a6xx_gpu->cur_ring =3D=3D ring)) { + set_preempt_state(a6xx_gpu, PREEMPT_FINISH); + update_wptr(gpu, a6xx_gpu->cur_ring); + set_preempt_state(a6xx_gpu, PREEMPT_NONE); + spin_unlock_irqrestore(&a6xx_gpu->eval_lock, flags); + return; + } + + spin_unlock_irqrestore(&a6xx_gpu->eval_lock, flags); + + spin_lock_irqsave(&ring->preempt_lock, flags); + + struct a7xx_cp_smmu_info *smmu_info_ptr =3D + a6xx_gpu->preempt[ring->id] + PREEMPT_OFFSET_SMMU_INFO; + struct a6xx_preempt_record *record_ptr =3D + a6xx_gpu->preempt[ring->id] + PREEMPT_OFFSET_PRIV_NON_SECURE; + u64 ttbr0 =3D ring->memptrs->ttbr0; + u32 context_idr =3D ring->memptrs->context_idr; + + smmu_info_ptr->ttbr0 =3D ttbr0; + smmu_info_ptr->context_idr =3D context_idr; + record_ptr->wptr =3D get_wptr(ring); + + /* + * The GPU will write the wptr we set above when we preempt. Reset + * restore_wptr to make sure that we don't write WPTR to the same + * thing twice. It's still possible subsequent submissions will update + * wptr again, in which case they will set the flag to true. This has + * to be protected by the lock for setting the flag and updating wptr + * to be atomic. + */ + ring->restore_wptr =3D false; + + spin_unlock_irqrestore(&ring->preempt_lock, flags); + + gpu_write64(gpu, + REG_A6XX_CP_CONTEXT_SWITCH_SMMU_INFO, + a6xx_gpu->preempt_iova[ring->id] + PREEMPT_OFFSET_SMMU_INFO); + + gpu_write64(gpu, + REG_A6XX_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR, + a6xx_gpu->preempt_iova[ring->id] + PREEMPT_OFFSET_PRIV_NON_SECURE); + + a6xx_gpu->next_ring =3D ring; + + /* Start a timer to catch a stuck preemption */ + mod_timer(&a6xx_gpu->preempt_timer, jiffies + msecs_to_jiffies(10000)); + + /* Set the preemption state to triggered */ + set_preempt_state(a6xx_gpu, PREEMPT_TRIGGERED); + + /* Trigger the preemption */ + gpu_write(gpu, REG_A6XX_CP_CONTEXT_SWITCH_CNTL, cntl); +} + +static int preempt_init_ring(struct a6xx_gpu *a6xx_gpu, + struct msm_ringbuffer *ring) +{ + struct adreno_gpu *adreno_gpu =3D &a6xx_gpu->base; + struct msm_gpu *gpu =3D &adreno_gpu->base; + struct drm_gem_object *bo =3D NULL; + phys_addr_t ttbr; + u64 iova =3D 0; + void *ptr; + int asid; + + ptr =3D msm_gem_kernel_new(gpu->dev, + PREEMPT_SIZE(adreno_gpu->info->preempt_record_size), + MSM_BO_WC | MSM_BO_MAP_PRIV, gpu->aspace, &bo, &iova); + + if (IS_ERR(ptr)) + return PTR_ERR(ptr); + + memset(ptr, 0, PREEMPT_SIZE(adreno_gpu->info->preempt_record_size)); + + msm_gem_object_set_name(bo, "preempt_record"); + + a6xx_gpu->preempt_bo[ring->id] =3D bo; + a6xx_gpu->preempt_iova[ring->id] =3D iova; + a6xx_gpu->preempt[ring->id] =3D ptr; + + struct a7xx_cp_smmu_info *smmu_info_ptr =3D ptr + PREEMPT_OFFSET_SMMU_INF= O; + struct a6xx_preempt_record *record_ptr =3D ptr + PREEMPT_OFFSET_PRIV_NON_= SECURE; + + msm_iommu_pagetable_params(gpu->aspace->mmu, &ttbr, &asid); + + smmu_info_ptr->magic =3D GEN7_CP_SMMU_INFO_MAGIC; + smmu_info_ptr->ttbr0 =3D ttbr; + smmu_info_ptr->asid =3D 0xdecafbad; + smmu_info_ptr->context_idr =3D 0; + + /* Set up the defaults on the preemption record */ + record_ptr->magic =3D A6XX_PREEMPT_RECORD_MAGIC; + record_ptr->info =3D 0; + record_ptr->data =3D 0; + record_ptr->rptr =3D 0; + record_ptr->wptr =3D 0; + record_ptr->cntl =3D MSM_GPU_RB_CNTL_DEFAULT; + record_ptr->rbase =3D ring->iova; + record_ptr->counter =3D 0; + record_ptr->bv_rptr_addr =3D rbmemptr(ring, bv_rptr); + + return 0; +} + +void a6xx_preempt_fini(struct msm_gpu *gpu) +{ + struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); + struct a6xx_gpu *a6xx_gpu =3D to_a6xx_gpu(adreno_gpu); + int i; + + for (i =3D 0; i < gpu->nr_rings; i++) + msm_gem_kernel_put(a6xx_gpu->preempt_bo[i], gpu->aspace); +} + +void a6xx_preempt_init(struct msm_gpu *gpu) +{ + struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); + struct a6xx_gpu *a6xx_gpu =3D to_a6xx_gpu(adreno_gpu); + int i; + + /* No preemption if we only have one ring */ + if (gpu->nr_rings <=3D 1) + return; + + for (i =3D 0; i < gpu->nr_rings; i++) { + if (preempt_init_ring(a6xx_gpu, gpu->rb[i])) + goto fail; + } + + /* TODO: make this configurable? */ + a6xx_gpu->preempt_level =3D 1; + a6xx_gpu->uses_gmem =3D 1; + a6xx_gpu->skip_save_restore =3D 1; + + timer_setup(&a6xx_gpu->preempt_timer, a6xx_preempt_timer, 0); + + return; +fail: + /* + * On any failure our adventure is over. Clean up and + * set nr_rings to 1 to force preemption off + */ + a6xx_preempt_fini(gpu); + gpu->nr_rings =3D 1; + + DRM_DEV_ERROR(&gpu->pdev->dev, + "preemption init failed, disabling preemption\n"); + + return; +} diff --git a/drivers/gpu/drm/msm/msm_ringbuffer.h b/drivers/gpu/drm/msm/msm= _ringbuffer.h index 174f83137a49..d1e49f701c81 100644 --- a/drivers/gpu/drm/msm/msm_ringbuffer.h +++ b/drivers/gpu/drm/msm/msm_ringbuffer.h @@ -36,6 +36,7 @@ struct msm_rbmemptrs { =20 volatile struct msm_gpu_submit_stats stats[MSM_GPU_SUBMIT_STATS_COUNT]; volatile u64 ttbr0; + volatile u32 context_idr; }; =20 struct msm_cp_state { @@ -101,6 +102,12 @@ struct msm_ringbuffer { */ spinlock_t preempt_lock; =20 + /* + * Whether we skipped writing wptr and it needs to be updated in the + * future when the ring becomes current. + */ + bool restore_wptr; + /** * cur_ctx_seqno: * --=20 2.46.0 From nobody Fri Nov 29 16:28:56 2024 Received: from mail-lf1-f53.google.com (mail-lf1-f53.google.com [209.85.167.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 541D217A591; Tue, 17 Sep 2024 11:14:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726571670; cv=none; b=lCWuanHZ91pmE3XIbpRuLd7F7/k676icUYAuRLNKqcb7JiNTGyGN7OWDEE+0did6qxPBdzMR4zdoKM3dv0RW3EKR9PFEgoioUGU+1HhF5fqUggx0iQ61NEhgHb0snM1FcbpemWUTwg1Iwl8L0MPFpMwTg1zS11c+Fv6cmzNrVBc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726571670; c=relaxed/simple; bh=uXlziadan9hJzafa2UxEKSmDxQDugnNERdYxm6GapoY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=fqqL1F2wYfVaNTTsykNR07+bd+K9VGK31Ts9N/ZcOyZSM5JDeDkp0h8rCy0xo2lBiq1FI198IrnTqaINoM0L+0lXiw6pP850/3ITts9k1N1T7pa7yoIzQ0fyuePAxVsrUPT+HWvaiaAz6lytynMlmnox/PE0o2yJua+tzzkTS+4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=D5jXNGTH; arc=none smtp.client-ip=209.85.167.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="D5jXNGTH" Received: by mail-lf1-f53.google.com with SMTP id 2adb3069b0e04-53654e2ed93so5939206e87.0; Tue, 17 Sep 2024 04:14:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1726571665; x=1727176465; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=f0kNTx+9AsOZWf/8yH7sCZ+xqB2wOOoaQ6wZ/cu7hDA=; b=D5jXNGTHHQA7c03gHdQ6xcz2irXg8YprH+tebbmiXbhZ9eQ0qc9eXQHlbzcSEL32Zb cXOTvauQoi/EBaHcEC3CGjESAT3R/JktRngvvAjMAQfifIBYJSCrK2yYN/Hz86ff1o44 nxyr73LJ34+iGGq3lQO/s4iF7pM3gx5Al9UBKyaVZneCtgqoLh8EvI/Ew/Gw0dIuRWPG 4z8IpWDccNVPtKTW4D6LnFsZCgpq7RffC7ZxOKAgL2kcVNPEHoNqEni2ickfEKQqJMCK A6QzHFaMud+PIiss+b55JGavBaBQGjRJz4PewNF/KO053fgCDiLTKMq/RqXnJHmPopUN hacA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726571665; x=1727176465; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=f0kNTx+9AsOZWf/8yH7sCZ+xqB2wOOoaQ6wZ/cu7hDA=; b=inWsEZ+oYF37X85XZbwPOE3ol2q8YJlFljhNc48wJZnOnvME3iM6/dHiBjrb6HyD3i XZZyJ1wQQAUVVkijEb8JpoWs8dXTdjxmdPJS3GAcVt/jtcnV2+bnMWH/YV0xNperzjlw cB/szWwyAktadno0YZxwT5VFnPeapURJIBE1GsowmYR+akUF8J20XSXuQMyc5tE0jRsJ mMSUQa88m/qZPwFX9S17Zw3oY/JiqYx4A0ZN6YiR43IS5zlJfnvxSpdkPY7PAWa7lXnG VpdJttzSsePm0iinFpS/W1atop571PL9GX/D2TurPr4T2ZwWnRLZps+gHxyJOVBwqeio am/Q== X-Forwarded-Encrypted: i=1; AJvYcCWrM288MnoNEReSBagIsyqqBvTfABKuZcqYpCypyzQAEA9x1IWlUwQRFnUPyINUybKSmW4xM1ix3Fk=@vger.kernel.org, AJvYcCXpRoOfLu4Z6u02jt+51H0Jee9WLOMCfemtrPOHe2qVRwFw9HHsXswYpTs0J7AZu6AkxPBpMpZis19iQ9d3@vger.kernel.org X-Gm-Message-State: AOJu0Yy7ltspIxe6no/LfDYr8VeYqXUX8ngm+PlqRn6XvYaNSF/Z1okZ YjYZTfvqam9b4/2q9zv1XlHler55E1CyAmAOfriGisOB5IHIiVmQ X-Google-Smtp-Source: AGHT+IE43HUTMcvg5JPGXBf28PLzvI1fH4Km7StHBX+xWMhU+QpuFfK2hgWczU0D69DxDYdSxCzUFA== X-Received: by 2002:a05:6512:110d:b0:536:5816:82ad with SMTP id 2adb3069b0e04-53678ff4b27mr9354969e87.57.1726571665303; Tue, 17 Sep 2024 04:14:25 -0700 (PDT) Received: from [192.168.1.17] (host-82-51-105-30.retail.telecomitalia.it. [82.51.105.30]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a90612e1a55sm430745166b.157.2024.09.17.04.14.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Sep 2024 04:14:24 -0700 (PDT) From: Antonino Maniscalco Date: Tue, 17 Sep 2024 13:14:16 +0200 Subject: [PATCH v4 06/11] drm/msm/A6xx: Sync relevant adreno_pm4.xml changes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240917-preemption-a750-t-v4-6-95d48012e0ac@gmail.com> References: <20240917-preemption-a750-t-v4-0-95d48012e0ac@gmail.com> In-Reply-To: <20240917-preemption-a750-t-v4-0-95d48012e0ac@gmail.com> To: Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Jonathan Corbet Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Antonino Maniscalco X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1726571652; l=3764; i=antomani103@gmail.com; s=20240815; h=from:subject:message-id; bh=uXlziadan9hJzafa2UxEKSmDxQDugnNERdYxm6GapoY=; b=LavGzjE0gZg8Jbw1qTXAm9ohHGbmvmV5uqhK5TpSFaHXALTVqMsf4VS3aKzyRdChm90JHepAR NG5HoyAZn+hDbXNjPE9jVC9gu77SGobCE8Gzod4x/omBen6tlwG+nG4 X-Developer-Key: i=antomani103@gmail.com; a=ed25519; pk=0zicFb38tVla+iHRo4kWpOMsmtUrpGBEa7LkFF81lyY= In mesa CP_SET_CTXSWITCH_IB is renamed to CP_SET_AMBLE and some other names are changed to match KGSL. Import those changes. The changes have not been merged yet in mesa but are necessary for this series. Signed-off-by: Antonino Maniscalco Tested-by: Neil Armstrong # on SM8450-HDK Tested-by: Neil Armstrong # on SM8550-QRD --- .../gpu/drm/msm/registers/adreno/adreno_pm4.xml | 39 ++++++++++--------= ---- 1 file changed, 17 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/msm/registers/adreno/adreno_pm4.xml b/drivers/= gpu/drm/msm/registers/adreno/adreno_pm4.xml index cab01af55d22..55a35182858c 100644 --- a/drivers/gpu/drm/msm/registers/adreno/adreno_pm4.xml +++ b/drivers/gpu/drm/msm/registers/adreno/adreno_pm4.xml @@ -581,8 +581,7 @@ xsi:schemaLocation=3D"https://gitlab.freedesktop.org/fr= eedreno/ rules-fd.xsd"> and forcibly switch to the indicated context. - - + =20