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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BL02EPF00021F68.mail.protection.outlook.com (10.167.249.4) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7918.13 via Frontend Transport; Mon, 16 Sep 2024 20:52:20 +0000 Received: from weiserver.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 16 Sep 2024 15:52:18 -0500 From: Wei Huang To: , , , CC: , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH V5 5/5] bnxt_en: Pass NQ ID to the FW when allocating RX/RX AGG rings Date: Mon, 16 Sep 2024 15:51:03 -0500 Message-ID: <20240916205103.3882081-6-wei.huang2@amd.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240916205103.3882081-1-wei.huang2@amd.com> References: <20240916205103.3882081-1-wei.huang2@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF00021F68:EE_|MW3PR12MB4473:EE_ X-MS-Office365-Filtering-Correlation-Id: 92bc06b9-004d-47a9-84c5-08dcd6917524 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|82310400026|1800799024|36860700013; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Sep 2024 20:52:20.1197 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 92bc06b9-004d-47a9-84c5-08dcd6917524 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF00021F68.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW3PR12MB4473 Content-Type: text/plain; charset="utf-8" From: Michael Chan Newer firmware can use the NQ ring ID associated with each RX/RX AGG ring to enable PCIe steering tag. Older firmware will just ignore the information. Signed-off-by: Michael Chan Signed-off-by: Andy Gospodarek Reviewed-by: Hongguang Gao Reviewed-by: Ajit Khaparde --- drivers/net/ethernet/broadcom/bnxt/bnxt.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/broadcom/bnxt/bnxt.c b/drivers/net/ethern= et/broadcom/bnxt/bnxt.c index ea0bd25d1efb..48ca3095ef2e 100644 --- a/drivers/net/ethernet/broadcom/bnxt/bnxt.c +++ b/drivers/net/ethernet/broadcom/bnxt/bnxt.c @@ -6811,10 +6811,12 @@ static int hwrm_ring_alloc_send_msg(struct bnxt *bp, =20 /* Association of rx ring with stats context */ grp_info =3D &bp->grp_info[ring->grp_idx]; + req->nq_ring_id =3D cpu_to_le16(grp_info->cp_fw_ring_id); req->rx_buf_size =3D cpu_to_le16(bp->rx_buf_use_size); req->stat_ctx_id =3D cpu_to_le32(grp_info->fw_stats_ctx); req->enables |=3D cpu_to_le32( - RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID); + RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID | + RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID); if (NET_IP_ALIGN =3D=3D 2) flags =3D RING_ALLOC_REQ_FLAGS_RX_SOP_PAD; req->flags =3D cpu_to_le16(flags); @@ -6826,11 +6828,13 @@ static int hwrm_ring_alloc_send_msg(struct bnxt *bp, /* Association of agg ring with rx ring */ grp_info =3D &bp->grp_info[ring->grp_idx]; req->rx_ring_id =3D cpu_to_le16(grp_info->rx_fw_ring_id); + req->nq_ring_id =3D cpu_to_le16(grp_info->cp_fw_ring_id); req->rx_buf_size =3D cpu_to_le16(BNXT_RX_PAGE_SIZE); req->stat_ctx_id =3D cpu_to_le32(grp_info->fw_stats_ctx); req->enables |=3D cpu_to_le32( RING_ALLOC_REQ_ENABLES_RX_RING_ID_VALID | - RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID); + RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID | + RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID); } else { req->ring_type =3D RING_ALLOC_REQ_RING_TYPE_RX; } --=20 2.45.1