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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CH2PEPF00000142.mail.protection.outlook.com (10.167.244.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7918.13 via Frontend Transport; Mon, 16 Sep 2024 17:18:50 +0000 Received: from purico-ed03host.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 16 Sep 2024 12:18:36 -0500 From: Suravee Suthikulpanit To: , CC: , , , , , , , , , Suravee Suthikulpanit Subject: [PATCH v4 2/6] iommu/amd: Introduce helper function to update 256-bit DTE Date: Mon, 16 Sep 2024 17:18:01 +0000 Message-ID: <20240916171805.324292-3-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240916171805.324292-1-suravee.suthikulpanit@amd.com> References: <20240916171805.324292-1-suravee.suthikulpanit@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF00000142:EE_|SJ2PR12MB7823:EE_ X-MS-Office365-Filtering-Correlation-Id: 078c0cab-7ef3-471c-a6b3-08dcd673a1b8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|376014|82310400026; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Sep 2024 17:18:50.1802 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 078c0cab-7ef3-471c-a6b3-08dcd673a1b8 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF00000142.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB7823 Content-Type: text/plain; charset="utf-8" The current implementation does not follow 128-bit write requirement to update DTE as specified in the AMD I/O Virtualization Techonology (IOMMU) Specification. Therefore, modify the struct dev_table_entry to contain union of u128 data array, and introduce a helper functions update_dte256() to update DTE using two 128-bit cmpxchg operations to update 256-bit DTE with the modified structure, and take into account the DTE[V, GV] bits when programming the DTE to ensure proper order of DTE programming and flushing. In addition, introduce a per-DTE spin_lock struct dev_data.dte_lock to provide synchronization when updating the DTE to prevent cmpxchg128 failure. Suggested-by: Jason Gunthorpe Signed-off-by: Suravee Suthikulpanit Reviewed-by: Jason Gunthorpe --- drivers/iommu/amd/amd_iommu.h | 2 + drivers/iommu/amd/amd_iommu_types.h | 8 ++- drivers/iommu/amd/iommu.c | 96 +++++++++++++++++++++++++++++ 3 files changed, 105 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h index 52e18b5f99fd..14a153c7bc12 100644 --- a/drivers/iommu/amd/amd_iommu.h +++ b/drivers/iommu/amd/amd_iommu.h @@ -28,6 +28,8 @@ void iommu_feature_enable(struct amd_iommu *iommu, u8 bit= ); void *__init iommu_alloc_4k_pages(struct amd_iommu *iommu, gfp_t gfp, size_t size); =20 +int iommu_flush_sync_dte(struct amd_iommu *iommu, u16 devid); + #ifdef CONFIG_AMD_IOMMU_DEBUGFS void amd_iommu_debugfs_setup(struct amd_iommu *iommu); #else diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_io= mmu_types.h index c9f9a598eb82..fea7544f8c55 100644 --- a/drivers/iommu/amd/amd_iommu_types.h +++ b/drivers/iommu/amd/amd_iommu_types.h @@ -427,6 +427,8 @@ =20 #define GCR3_VALID 0x01ULL =20 +#define DTE_INTR_MASK (~GENMASK_ULL(55, 52)) + #define IOMMU_PAGE_MASK (((1ULL << 52) - 1) & ~0xfffULL) #define IOMMU_PTE_PRESENT(pte) ((pte) & IOMMU_PTE_PR) #define IOMMU_PTE_DIRTY(pte) ((pte) & IOMMU_PTE_HD) @@ -833,6 +835,7 @@ struct devid_map { struct iommu_dev_data { /*Protect against attach/detach races */ spinlock_t lock; + spinlock_t dte_lock; /* DTE lock for 256-bit access */ =20 struct list_head list; /* For domain->dev_list */ struct llist_node dev_data_list; /* For global dev_data_list */ @@ -883,7 +886,10 @@ extern struct amd_iommu *amd_iommus[MAX_IOMMUS]; * Structure defining one entry in the device table */ struct dev_table_entry { - u64 data[4]; + union { + u64 data[4]; + u128 data128[2]; + }; }; =20 /* diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 87c5385ce3f2..48a721d10f06 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -85,6 +85,91 @@ static void set_dte_entry(struct amd_iommu *iommu, * *************************************************************************= ***/ =20 +static void write_upper(struct dev_table_entry *ptr, struct dev_table_entr= y *new) +{ + struct dev_table_entry old =3D {}; + + do { + old.data128[1] =3D ptr->data128[1]; + new->data[2] &=3D ~DTE_INTR_MASK; + new->data[2] |=3D (old.data[2] & DTE_INTR_MASK); + } while (!try_cmpxchg128(&ptr->data128[1], &old.data128[1], new->data128[= 1])); +} + +static void write_lower(struct dev_table_entry *ptr, struct dev_table_entr= y *new) +{ + struct dev_table_entry old =3D {}; + + do { + old.data128[0] =3D ptr->data128[0]; + } while (!try_cmpxchg128(&ptr->data128[0], &old.data128[0], new->data128[= 0])); +} + +/* + * Note: + * IOMMU reads the entire Device Table entry in a single 256-bit transacti= on + * but the driver is programming DTE using 2 128-bit cmpxchg. So, the driv= er + * need to ensure the following: + * - DTE[V|GV] bit is being written last when setting. + * - DTE[V|GV] bit is being written first when clearing. + * + * This function is used only by code, which updates DMA translation part = of the DTE. + * So, only consider control bits related to DMA when updating the entry. + */ +static void update_dte256(struct amd_iommu *iommu, struct iommu_dev_data *= dev_data, + struct dev_table_entry *new) +{ + struct dev_table_entry *dev_table =3D get_dev_table(iommu); + struct dev_table_entry *ptr =3D &dev_table[dev_data->devid]; + + spin_lock(&dev_data->dte_lock); + + if (!(ptr->data[0] & DTE_FLAG_V)) { + /* Existing DTE is not valid. */ + write_upper(ptr, new); + write_lower(ptr, new); + iommu_flush_sync_dte(iommu, dev_data->devid); + } else if (!(new->data[0] & DTE_FLAG_V)) { + /* Existing DTE is valid. New DTE is not valid. */ + write_lower(ptr, new); + write_upper(ptr, new); + iommu_flush_sync_dte(iommu, dev_data->devid); + } else { + /* Existing & new DTEs are valid. */ + if (!FIELD_GET(DTE_FLAG_GV, ptr->data[0])) { + /* Existing DTE has no guest page table. */ + write_upper(ptr, new); + write_lower(ptr, new); + iommu_flush_sync_dte(iommu, dev_data->devid); + } else if (!FIELD_GET(DTE_FLAG_GV, new->data[0])) { + /* + * Existing DTE has guest page table, + * new DTE has no guest page table, + */ + write_lower(ptr, new); + write_upper(ptr, new); + iommu_flush_sync_dte(iommu, dev_data->devid); + } else { + /* + * Existing DTE has guest page table, + * new DTE has guest page table. + */ + struct dev_table_entry clear =3D {}; + + /* First disable DTE */ + write_lower(ptr, &clear); + iommu_flush_sync_dte(iommu, dev_data->devid); + + /* Then update DTE */ + write_upper(ptr, new); + write_lower(ptr, new); + iommu_flush_sync_dte(iommu, dev_data->devid); + } + } + + spin_unlock(&dev_data->dte_lock); +} + static inline bool pdom_is_v2_pgtbl_mode(struct protection_domain *pdom) { return (pdom && (pdom->pd_mode =3D=3D PD_MODE_V2)); @@ -205,6 +290,7 @@ static struct iommu_dev_data *alloc_dev_data(struct amd= _iommu *iommu, u16 devid) return NULL; =20 spin_lock_init(&dev_data->lock); + spin_lock_init(&dev_data->dte_lock); dev_data->devid =3D devid; ratelimit_default_init(&dev_data->rs); =20 @@ -1256,6 +1342,16 @@ static int iommu_flush_dte(struct amd_iommu *iommu, = u16 devid) return iommu_queue_command(iommu, &cmd); } =20 +int iommu_flush_sync_dte(struct amd_iommu *iommu, u16 devid) +{ + int ret; + + ret =3D iommu_flush_dte(iommu, devid); + if (!ret) + iommu_completion_wait(iommu); + return ret; +} + static void amd_iommu_flush_dte_all(struct amd_iommu *iommu) { u32 devid; --=20 2.34.1