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(unknown [10.28.34.196]) by maili.marvell.com (Postfix) with ESMTP id CCD7D3F704A; Mon, 16 Sep 2024 03:34:49 -0700 (PDT) From: Linu Cherian To: , , CC: , , , , , , , , , , , Linu Cherian Subject: [PATCH v10 1/8] dt-bindings: arm: coresight-tmc: Add "memory-region" property Date: Mon, 16 Sep 2024 16:04:30 +0530 Message-ID: <20240916103437.226816-2-lcherian@marvell.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240916103437.226816-1-lcherian@marvell.com> References: <20240916103437.226816-1-lcherian@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: EQP2SgR-2Gfe5zyRrAMMPrd0tcP9_6-3 X-Proofpoint-GUID: EQP2SgR-2Gfe5zyRrAMMPrd0tcP9_6-3 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 Content-Type: text/plain; charset="utf-8" memory-region 0: Reserved trace buffer memory TMC ETR: When available, use this reserved memory region for trace data capture. Same region is used for trace data retention after a panic or watchdog reset. TMC ETF: When available, use this reserved memory region for trace data retention synced from internal SRAM after a panic or watchdog reset. memory-region 1: Reserved meta data memory TMC ETR, ETF: When available, use this memory for register snapshot retention synced from hardware registers after a panic or watchdog reset. Reviewed-by: Rob Herring Signed-off-by: Linu Cherian --- Changelog from v9: No changes. .../bindings/arm/arm,coresight-tmc.yaml | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml b= /Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml index cb8dceaca70e..4787d7c6bac2 100644 --- a/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml +++ b/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml @@ -101,6 +101,29 @@ properties: and ETF configurations. $ref: /schemas/graph.yaml#/properties/port =20 + memory-region: + items: + - description: Reserved trace buffer memory for ETR and ETF sinks. + For ETR, this reserved memory region is used for trace data capt= ure. + Same region is used for trace data retention as well after a pan= ic + or watchdog reset. + This reserved memory region is used as trace buffer or used for = trace + data retention only if specifically selected by the user in sysfs + interface. + The default memory usage models for ETR in sysfs/perf modes are + otherwise unaltered. + + For ETF, this reserved memory region is used by default for + retention of trace data synced from internal SRAM after a panic + or watchdog reset. + - description: Reserved meta data memory. Used for ETR and ETF sinks + for storing metadata. + + memory-region-names: + items: + - const: tracedata + - const: metadata + required: - compatible - reg @@ -115,6 +138,9 @@ examples: etr@20070000 { compatible =3D "arm,coresight-tmc", "arm,primecell"; reg =3D <0x20070000 0x1000>; + memory-region =3D <&etr_trace_mem_reserved>, + <&etr_mdata_mem_reserved>; + memory-region-names =3D "tracedata", "metadata"; =20 clocks =3D <&oscclk6a>; clock-names =3D "apb_pclk"; --=20 2.34.1 From nobody Fri Nov 29 18:35:20 2024 Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6712514A4E9; Mon, 16 Sep 2024 10:35:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=67.231.156.173 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726482913; cv=none; b=gIF/pzlWJ+ZvnWOVWs1juZbBYYudsX539IeNovmV11gpSgZh24SBu+FxEsHNs6xlkbmGQI/ObreSkpp+AdSM0+JVA+sVPbySBLAeSxYz1vKLnOStdkKkEuZ29MArxOx5dVN/XrHv3rl1qEm49CRbq6alHKei4K68gd9LdPrRzD4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726482913; c=relaxed/simple; bh=qZIeWi2Bq0BxOHEktpo0Mju0MaEGIbFictGdvY11hBg=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=STfBcpayFqXHI5dgR7FkM8uf8wkp3BAi7xTh+G7S/UQdvJGq8QFND71/iYnCt3Dt4yh2JcpAdPn/YbgoGncsu/t9KqD7C+ytxkKETIm7iRxIzeGCRUyOecPe81alHUXG4sypLg/iRI+Fe8jyiJDRBQuJ4EEZKgGOIPOvN20RqUc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com; spf=pass smtp.mailfrom=marvell.com; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b=QCUYcVUV; arc=none smtp.client-ip=67.231.156.173 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=marvell.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b="QCUYcVUV" Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 48FMdrZG016228; Mon, 16 Sep 2024 03:35:00 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=pfpt0220; bh=G ZQVZf0KpSwQTm3tF79PQmmN6aCyAlPI1T22k1lWMgM=; b=QCUYcVUV7bSo3FmVx nIiQgvBycK/94yoS4zntnK6lm+VuBTnIUWFCzMrEELCRtlAAsRxGb4hsTCvc9iM8 lxdppbjEf8vjUIUlEhK7XFCK8ItuDwv4/jyEqsQDB6p3yzueu4ZKdAazb6aGr4Rt jOB1xmq6uJWw4dSDYe3PJ6bmlbc6HvYtG+ksBBLvB8gLDsqcl+kr0SJX3qOYBi5u n1oht46USp12Nn+PxCIOc28Awpw6sApLnjPCRo+z0KJyzu67sT+UiDUrLM7JwgfV Z/T4xT0Fl2jm7A3B1FVpUx/gEggMHujjXAMJMEIT6OkTEsUtR79J8pktxnlUZFDe rBYjA== Received: from dc5-exch05.marvell.com ([199.233.59.128]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 41na0fw3q7-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 16 Sep 2024 03:35:00 -0700 (PDT) Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Mon, 16 Sep 2024 03:34:58 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Mon, 16 Sep 2024 03:34:58 -0700 Received: from virtx40.. (unknown [10.28.34.196]) by maili.marvell.com (Postfix) with ESMTP id 631093F704A; Mon, 16 Sep 2024 03:34:54 -0700 (PDT) From: Linu Cherian To: , , CC: , , , , , , , , , , , Linu Cherian , Anil Kumar Reddy Subject: [PATCH v10 2/8] coresight: tmc-etr: Add support to use reserved trace memory Date: Mon, 16 Sep 2024 16:04:31 +0530 Message-ID: <20240916103437.226816-3-lcherian@marvell.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240916103437.226816-1-lcherian@marvell.com> References: <20240916103437.226816-1-lcherian@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: FXlOLyEBV4SoOsK-O7-7Wg7F9i-2Yvvb X-Proofpoint-GUID: FXlOLyEBV4SoOsK-O7-7Wg7F9i-2Yvvb X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 Content-Type: text/plain; charset="utf-8" Add support to use reserved memory for coresight ETR trace buffer. Introduce a new ETR buffer mode called ETR_MODE_RESRV, which becomes available when ETR device tree node is supplied with a valid reserved memory region. ETR_MODE_RESRV can be selected only by explicit user request. $ echo resrv >/sys/bus/coresight/devices/tmc_etr/buf_mode_preferred Signed-off-by: Anil Kumar Reddy Signed-off-by: Linu Cherian --- Changelog from v9: - Added common helper function of_tmc_get_reserved_resource_by_name for better code reuse - drvdata->crash_tbuf renamed to drvdata->resrv_buf - In order to seperate validity of crash metadata with the availability of reserved buffer, is_tmc_reserved_region_valid was renamed to=20 tmc_has_reserved_buffer=20 - Removed "Reviewed-by: James Clark " due to the above changes .../hwtracing/coresight/coresight-tmc-core.c | 50 ++++++++++++ .../hwtracing/coresight/coresight-tmc-etr.c | 79 +++++++++++++++++++ drivers/hwtracing/coresight/coresight-tmc.h | 25 ++++++ 3 files changed, 154 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwt= racing/coresight/coresight-tmc-core.c index b54562f392f3..0764c21aba0f 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-core.c +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include #include @@ -399,6 +400,53 @@ static inline bool tmc_etr_has_non_secure_access(struc= t tmc_drvdata *drvdata) =20 static const struct amba_id tmc_ids[]; =20 +static int of_tmc_get_reserved_resource_by_name(struct device *dev, + const char *name, + struct resource *res) +{ + int index, rc =3D -ENODEV; + struct device_node *node; + + if (!is_of_node(dev->fwnode)) + return -ENODEV; + + index =3D of_property_match_string(dev->of_node, "memory-region-names", + name); + if (index < 0) + return rc; + + node =3D of_parse_phandle(dev->of_node, "memory-region", index); + if (!node) + return rc; + + if (!of_address_to_resource(node, 0, res) && + res->start !=3D 0 && resource_size(res) !=3D 0) + rc =3D 0; + of_node_put(node); + + return rc; +} + +static void tmc_get_reserved_region(struct device *parent) +{ + struct tmc_drvdata *drvdata =3D dev_get_drvdata(parent); + struct resource res; + + if (of_tmc_get_reserved_resource_by_name(parent, "tracedata", &res)) + return; + + drvdata->resrv_buf.vaddr =3D memremap(res.start, + resource_size(&res), + MEMREMAP_WC); + if (IS_ERR_OR_NULL(drvdata->resrv_buf.vaddr)) { + dev_err(parent, "Reserved trace buffer mapping failed\n"); + return; + } + + drvdata->resrv_buf.paddr =3D res.start; + drvdata->resrv_buf.size =3D resource_size(&res); +} + /* Detect and initialise the capabilities of a TMC ETR */ static int tmc_etr_setup_caps(struct device *parent, u32 devid, struct csdev_access *access) @@ -509,6 +557,8 @@ static int __tmc_probe(struct device *dev, struct resou= rce *res) drvdata->size =3D readl_relaxed(drvdata->base + TMC_RSZ) * 4; } =20 + tmc_get_reserved_region(dev); + desc.dev =3D dev; =20 switch (drvdata->config_type) { diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtr= acing/coresight/coresight-tmc-etr.c index a48bb85d0e7f..8bca5b36334a 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -30,6 +30,7 @@ struct etr_buf_hw { bool has_iommu; bool has_etr_sg; bool has_catu; + bool has_resrv; }; =20 /* @@ -695,6 +696,75 @@ static const struct etr_buf_operations etr_flat_buf_op= s =3D { .get_data =3D tmc_etr_get_data_flat_buf, }; =20 +/* + * tmc_etr_alloc_resrv_buf: Allocate a contiguous DMA buffer from reserved= region. + */ +static int tmc_etr_alloc_resrv_buf(struct tmc_drvdata *drvdata, + struct etr_buf *etr_buf, int node, + void **pages) +{ + struct etr_flat_buf *resrv_buf; + struct device *real_dev =3D drvdata->csdev->dev.parent; + + /* We cannot reuse existing pages for resrv buf */ + if (pages) + return -EINVAL; + + resrv_buf =3D kzalloc(sizeof(*resrv_buf), GFP_KERNEL); + if (!resrv_buf) + return -ENOMEM; + + resrv_buf->daddr =3D dma_map_resource(real_dev, drvdata->resrv_buf.paddr, + drvdata->resrv_buf.size, + DMA_FROM_DEVICE, 0); + if (dma_mapping_error(real_dev, resrv_buf->daddr)) { + dev_err(real_dev, "failed to map source buffer address\n"); + kfree(resrv_buf); + return -ENOMEM; + } + + resrv_buf->vaddr =3D drvdata->resrv_buf.vaddr; + resrv_buf->size =3D etr_buf->size =3D drvdata->resrv_buf.size; + resrv_buf->dev =3D &drvdata->csdev->dev; + etr_buf->hwaddr =3D resrv_buf->daddr; + etr_buf->mode =3D ETR_MODE_RESRV; + etr_buf->private =3D resrv_buf; + return 0; +} + +static void tmc_etr_free_resrv_buf(struct etr_buf *etr_buf) +{ + struct etr_flat_buf *resrv_buf =3D etr_buf->private; + + if (resrv_buf && resrv_buf->daddr) { + struct device *real_dev =3D resrv_buf->dev->parent; + + dma_unmap_resource(real_dev, resrv_buf->daddr, + resrv_buf->size, DMA_FROM_DEVICE, 0); + } + kfree(resrv_buf); +} + +static void tmc_etr_sync_resrv_buf(struct etr_buf *etr_buf, u64 rrp, u64 r= wp) +{ + /* + * Adjust the buffer to point to the beginning of the trace data + * and update the available trace data. + */ + etr_buf->offset =3D rrp - etr_buf->hwaddr; + if (etr_buf->full) + etr_buf->len =3D etr_buf->size; + else + etr_buf->len =3D rwp - rrp; +} + +static const struct etr_buf_operations etr_resrv_buf_ops =3D { + .alloc =3D tmc_etr_alloc_resrv_buf, + .free =3D tmc_etr_free_resrv_buf, + .sync =3D tmc_etr_sync_resrv_buf, + .get_data =3D tmc_etr_get_data_flat_buf, +}; + /* * tmc_etr_alloc_sg_buf: Allocate an SG buf @etr_buf. Setup the parameters * appropriately. @@ -801,6 +871,7 @@ static const struct etr_buf_operations *etr_buf_ops[] = =3D { [ETR_MODE_FLAT] =3D &etr_flat_buf_ops, [ETR_MODE_ETR_SG] =3D &etr_sg_buf_ops, [ETR_MODE_CATU] =3D NULL, + [ETR_MODE_RESRV] =3D &etr_resrv_buf_ops }; =20 void tmc_etr_set_catu_ops(const struct etr_buf_operations *catu) @@ -826,6 +897,7 @@ static inline int tmc_etr_mode_alloc_buf(int mode, case ETR_MODE_FLAT: case ETR_MODE_ETR_SG: case ETR_MODE_CATU: + case ETR_MODE_RESRV: if (etr_buf_ops[mode] && etr_buf_ops[mode]->alloc) rc =3D etr_buf_ops[mode]->alloc(drvdata, etr_buf, node, pages); @@ -844,6 +916,7 @@ static void get_etr_buf_hw(struct device *dev, struct e= tr_buf_hw *buf_hw) buf_hw->has_iommu =3D iommu_get_domain_for_dev(dev->parent); buf_hw->has_etr_sg =3D tmc_etr_has_cap(drvdata, TMC_ETR_SG); buf_hw->has_catu =3D !!tmc_etr_get_catu_device(drvdata); + buf_hw->has_resrv =3D tmc_has_reserved_buffer(drvdata); } =20 static bool etr_can_use_flat_mode(struct etr_buf_hw *buf_hw, ssize_t etr_b= uf_size) @@ -1831,6 +1904,7 @@ static const char *const buf_modes_str[] =3D { [ETR_MODE_FLAT] =3D "flat", [ETR_MODE_ETR_SG] =3D "tmc-sg", [ETR_MODE_CATU] =3D "catu", + [ETR_MODE_RESRV] =3D "resrv", [ETR_MODE_AUTO] =3D "auto", }; =20 @@ -1849,6 +1923,9 @@ static ssize_t buf_modes_available_show(struct device= *dev, if (buf_hw.has_catu) size +=3D sysfs_emit_at(buf, size, "%s ", buf_modes_str[ETR_MODE_CATU]); =20 + if (buf_hw.has_resrv) + size +=3D sysfs_emit_at(buf, size, "%s ", buf_modes_str[ETR_MODE_RESRV]); + size +=3D sysfs_emit_at(buf, size, "\n"); return size; } @@ -1876,6 +1953,8 @@ static ssize_t buf_mode_preferred_store(struct device= *dev, drvdata->etr_mode =3D ETR_MODE_ETR_SG; else if (sysfs_streq(buf, buf_modes_str[ETR_MODE_CATU]) && buf_hw.has_cat= u) drvdata->etr_mode =3D ETR_MODE_CATU; + else if (sysfs_streq(buf, buf_modes_str[ETR_MODE_RESRV]) && buf_hw.has_re= srv) + drvdata->etr_mode =3D ETR_MODE_RESRV; else if (sysfs_streq(buf, buf_modes_str[ETR_MODE_AUTO])) drvdata->etr_mode =3D ETR_MODE_AUTO; else diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracin= g/coresight/coresight-tmc.h index 2671926be62a..d2261eddab71 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.h +++ b/drivers/hwtracing/coresight/coresight-tmc.h @@ -135,6 +135,7 @@ enum etr_mode { ETR_MODE_FLAT, /* Uses contiguous flat buffer */ ETR_MODE_ETR_SG, /* Uses in-built TMC ETR SG mechanism */ ETR_MODE_CATU, /* Use SG mechanism in CATU */ + ETR_MODE_RESRV, /* Use reserved region contiguous buffer */ ETR_MODE_AUTO, /* Use the default mechanism */ }; =20 @@ -164,6 +165,17 @@ struct etr_buf { void *private; }; =20 +/** + * @paddr : Start address of reserved memory region. + * @vaddr : Corresponding CPU virtual address. + * @size : Size of reserved memory region. + */ +struct tmc_resrv_buf { + phys_addr_t paddr; + void *vaddr; + size_t size; +}; + /** * struct tmc_drvdata - specifics associated to an TMC component * @pclk: APB clock if present, otherwise NULL @@ -189,6 +201,10 @@ struct etr_buf { * @idr_mutex: Access serialisation for idr. * @sysfs_buf: SYSFS buffer for ETR. * @perf_buf: PERF buffer for ETR. + * @resrv_buf: Used by ETR as hardware trace buffer and for trace data + * retention (after crash) only when ETR_MODE_RESRV buffer + * mode is enabled. Used by ETF for trace data retention + * (after crash) by default. */ struct tmc_drvdata { struct clk *pclk; @@ -214,6 +230,7 @@ struct tmc_drvdata { struct mutex idr_mutex; struct etr_buf *sysfs_buf; struct etr_buf *perf_buf; + struct tmc_resrv_buf resrv_buf; }; =20 struct etr_buf_operations { @@ -331,6 +348,14 @@ tmc_sg_table_buf_size(struct tmc_sg_table *sg_table) return (unsigned long)sg_table->data_pages.nr_pages << PAGE_SHIFT; } =20 +static inline bool tmc_has_reserved_buffer(struct tmc_drvdata *drvdata) +{ + if (drvdata->resrv_buf.vaddr && + drvdata->resrv_buf.size) + return true; + return false; +} + struct coresight_device *tmc_etr_get_catu_device(struct tmc_drvdata *drvda= ta); =20 void tmc_etr_set_catu_ops(const struct etr_buf_operations *catu); --=20 2.34.1 From nobody Fri Nov 29 18:35:20 2024 Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C4558154C19; Mon, 16 Sep 2024 10:35:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=67.231.148.174 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726482918; cv=none; b=dZjhKZqxgDqzaoER3/2c9gEm5la1z1fuXYQOcyWXCnxaqlDtvu6P744JMeaft1KZ8ZOjCvROzV3T8pumFFD7PYrsLxyCY/TWhP/wM8E6t/2u+VYTrpLHlDy+zyBIV9rx8jLB/czN+sn+goIMdC5wFKFJwR0XChaA8m0Ii67HWXc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726482918; c=relaxed/simple; bh=NxKKtKJ/uLY0tGbkd9ReoyC9hHLsinm0enE7v5/D7QI=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=hvczWc7dhkFTshXFbKJsVVBU/ddL4jZIBpUV5eHScAcrPN420qjA8Gk4jhf7yCU/2z1c6hms6CUklFEy4+CaGLbr/bvDSPxJ/nhm5RbGd2TmZ2Hff4M8GXMgAZZOPJfvG3ZxuZFuGpcxjQS62t7wrTbGEoNR49pgWu6eTd3c9L8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com; spf=pass smtp.mailfrom=marvell.com; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b=NITbfeAE; arc=none smtp.client-ip=67.231.148.174 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=marvell.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b="NITbfeAE" Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 48GA0QaF024628; Mon, 16 Sep 2024 03:35:04 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=pfpt0220; bh=M XVL17DCIvBohMJtRPyN7CqL3YFzs6RfI/8MqlmHLxM=; b=NITbfeAETZRq8lSg9 iPS8dRK3kBGFfl6SR4Bds6ADmNkg7+cb27T2QG0AM33THJ/IvcUeE4cMNYJbveu2 naUIh5oeKJYcNP32sRku+MovLsSnhurmLiTqn+SC3ubPMVyxKjkuMMhliAbsLUHo NBu239/FMpybs2Jc4Q/+/pmQCV4BsnStGfakwiGDUMtnO1zsyadHsz8gZMu3Iw2D +XBoCtWe2wKNZwX6sV6urn+1wwbW8Jsquv1f8WZkw5C8IKhcVHgGtx3iqk14m7yU A/SixqOZJQbrqlOgL4N7rj1c0MqI1Dc5KCCT35EYRJNxkW802O1WIjRlcW24+m44 bnZ/A== Received: from dc5-exch05.marvell.com ([199.233.59.128]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 41n7ujndae-2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 16 Sep 2024 03:35:03 -0700 (PDT) Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Mon, 16 Sep 2024 03:35:03 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Mon, 16 Sep 2024 03:35:03 -0700 Received: from virtx40.. (unknown [10.28.34.196]) by maili.marvell.com (Postfix) with ESMTP id 34E8C3F704A; Mon, 16 Sep 2024 03:34:58 -0700 (PDT) From: Linu Cherian To: , , CC: , , , , , , , , , , , Linu Cherian Subject: [PATCH v10 3/8] coresight: core: Add provision for panic callbacks Date: Mon, 16 Sep 2024 16:04:32 +0530 Message-ID: <20240916103437.226816-4-lcherian@marvell.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240916103437.226816-1-lcherian@marvell.com> References: <20240916103437.226816-1-lcherian@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: gp4lbiOlu3kkIT3zAe_AQOrjANyMrq2B X-Proofpoint-ORIG-GUID: gp4lbiOlu3kkIT3zAe_AQOrjANyMrq2B X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 Content-Type: text/plain; charset="utf-8" Panic callback handlers allows coresight device drivers to sync relevant trace data and trace metadata to reserved memory regions so that they can be retrieved later in the subsequent boot or in the crashdump kernel. Signed-off-by: Linu Cherian Reviewed-by: James Clark --- Changelog from v9: - Added return checks atomic_notifier_chain_register drivers/hwtracing/coresight/coresight-core.c | 42 ++++++++++++++++++++ include/linux/coresight.h | 12 ++++++ 2 files changed, 54 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtraci= ng/coresight/coresight-core.c index ea38ecf26fcb..8c5fb66911a5 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -19,6 +19,7 @@ #include #include #include +#include =20 #include "coresight-etm-perf.h" #include "coresight-priv.h" @@ -1378,6 +1379,36 @@ const struct bus_type coresight_bustype =3D { .name =3D "coresight", }; =20 +static int coresight_panic_sync(struct device *dev, void *data) +{ + int mode; + struct coresight_device *csdev; + + /* Run through panic sync handlers for all enabled devices */ + csdev =3D container_of(dev, struct coresight_device, dev); + mode =3D coresight_get_mode(csdev); + + if ((mode =3D=3D CS_MODE_SYSFS) || (mode =3D=3D CS_MODE_PERF)) { + if (panic_ops(csdev)) + panic_ops(csdev)->sync(csdev); + } + + return 0; +} + +static int coresight_panic_cb(struct notifier_block *self, + unsigned long v, void *p) +{ + bus_for_each_dev(&coresight_bustype, NULL, NULL, + coresight_panic_sync); + + return 0; +} + +static struct notifier_block coresight_notifier =3D { + .notifier_call =3D coresight_panic_cb, +}; + static int __init coresight_init(void) { int ret; @@ -1390,11 +1421,20 @@ static int __init coresight_init(void) if (ret) goto exit_bus_unregister; =20 + /* Register function to be called for panic */ + ret =3D atomic_notifier_chain_register(&panic_notifier_list, + &coresight_notifier); + if (ret) + goto exit_perf; + /* initialise the coresight syscfg API */ ret =3D cscfg_init(); if (!ret) return 0; =20 + atomic_notifier_chain_unregister(&panic_notifier_list, + &coresight_notifier); +exit_perf: etm_perf_exit(); exit_bus_unregister: bus_unregister(&coresight_bustype); @@ -1404,6 +1444,8 @@ static int __init coresight_init(void) static void __exit coresight_exit(void) { cscfg_exit(); + atomic_notifier_chain_unregister(&panic_notifier_list, + &coresight_notifier); etm_perf_exit(); bus_unregister(&coresight_bustype); } diff --git a/include/linux/coresight.h b/include/linux/coresight.h index c13342594278..2e63f7614551 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -335,6 +335,7 @@ enum cs_mode { #define link_ops(csdev) csdev->ops->link_ops #define helper_ops(csdev) csdev->ops->helper_ops #define ect_ops(csdev) csdev->ops->ect_ops +#define panic_ops(csdev) csdev->ops->panic_ops =20 /** * struct coresight_ops_sink - basic operations for a sink @@ -404,11 +405,22 @@ struct coresight_ops_helper { int (*disable)(struct coresight_device *csdev, void *data); }; =20 + +/** + * struct coresight_ops_panic - Generic device ops for panic handing + * + * @sync : Sync the device register state/trace data + */ +struct coresight_ops_panic { + int (*sync)(struct coresight_device *csdev); +}; + struct coresight_ops { const struct coresight_ops_sink *sink_ops; const struct coresight_ops_link *link_ops; const struct coresight_ops_source *source_ops; const struct coresight_ops_helper *helper_ops; + const struct coresight_ops_panic *panic_ops; }; =20 static inline u32 csdev_access_relaxed_read32(struct csdev_access *csa, --=20 2.34.1 From nobody Fri Nov 29 18:35:20 2024 Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 74242155756; Mon, 16 Sep 2024 10:35:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=67.231.156.173 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726482921; cv=none; b=Agm/I7yne6ruEZGRT/LzJn8V94OUMkSk5TJDIgzsoOVOPCleMirlRxzKqh0IOUk4hXjE0W1mMRjkqzlf7cHi4Z1KW/BxMo0nBQCr6yU/xClyYbxh+dOrm8btvcoKCDAsaEXyZVK8/4WHJeMhYsC8d0PrggXoej4BO6o5dzxWRLM= ARC-Message-Signature: i=1; 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(unknown [10.28.34.196]) by maili.marvell.com (Postfix) with ESMTP id BEC2A3F7054; Mon, 16 Sep 2024 03:35:03 -0700 (PDT) From: Linu Cherian To: , , CC: , , , , , , , , , , , Linu Cherian Subject: [PATCH v10 4/8] coresight: tmc: Enable panic sync handling Date: Mon, 16 Sep 2024 16:04:33 +0530 Message-ID: <20240916103437.226816-5-lcherian@marvell.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240916103437.226816-1-lcherian@marvell.com> References: <20240916103437.226816-1-lcherian@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: hXcD1kT1iDAdEUZfhM5CTDx14Okvfi8U X-Proofpoint-GUID: hXcD1kT1iDAdEUZfhM5CTDx14Okvfi8U X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 Content-Type: text/plain; charset="utf-8" - Get reserved region from device tree node for metadata - Define metadata format for TMC - Add TMC ETR panic sync handler that syncs register snapshot to metadata region - Add TMC ETF panic sync handler that syncs register snapshot to metadata region and internal SRAM to reserved trace buffer region. Signed-off-by: Linu Cherian --- Changelog from v9: - Add common helper function of_tmc_get_reserved_resource_by_name for better code reuse - Inorder to keep the reserved buffer validity and crashdata validity independent, is_tmc_reserved_region_valid renamed to tmc_has_reserved_buf= fer - drvdata->crash_tbuf renamed to drvdata->resrv_buf - New fields added to crash metadata: version, ffcr, ffsr, mode - Defined crashdata version with Major version 1, Minor version 0 - Set version while creating crashdata record - Removed Reviewed-by tag due to the above changes =20 .../hwtracing/coresight/coresight-tmc-core.c | 14 ++++ .../hwtracing/coresight/coresight-tmc-etf.c | 77 ++++++++++++++++++ .../hwtracing/coresight/coresight-tmc-etr.c | 78 +++++++++++++++++++ drivers/hwtracing/coresight/coresight-tmc.h | 66 ++++++++++++++++ 4 files changed, 235 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwt= racing/coresight/coresight-tmc-core.c index 0764c21aba0f..54bf8ae2bff8 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-core.c +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c @@ -445,6 +445,20 @@ static void tmc_get_reserved_region(struct device *par= ent) =20 drvdata->resrv_buf.paddr =3D res.start; drvdata->resrv_buf.size =3D resource_size(&res); + + if (of_tmc_get_reserved_resource_by_name(parent, "metadata", &res)) + return; + + drvdata->crash_mdata.vaddr =3D memremap(res.start, + resource_size(&res), + MEMREMAP_WC); + if (IS_ERR_OR_NULL(drvdata->crash_mdata.vaddr)) { + dev_err(parent, "Metadata memory mapping failed\n"); + return; + } + + drvdata->crash_mdata.paddr =3D res.start; + drvdata->crash_mdata.size =3D resource_size(&res); } =20 /* Detect and initialise the capabilities of a TMC ETR */ diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtr= acing/coresight/coresight-tmc-etf.c index d4f641cd9de6..d77ec9307e98 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c @@ -590,6 +590,78 @@ static unsigned long tmc_update_etf_buffer(struct core= sight_device *csdev, return to_read; } =20 +static int tmc_panic_sync_etf(struct coresight_device *csdev) +{ + u32 val; + struct csdev_access *csa; + struct tmc_crash_metadata *mdata; + struct tmc_drvdata *drvdata =3D dev_get_drvdata(csdev->dev.parent); + + csa =3D &drvdata->csdev->access; + mdata =3D (struct tmc_crash_metadata *)drvdata->crash_mdata.vaddr; + + /* Make sure we have valid reserved memory */ + if (!tmc_has_reserved_buffer(drvdata) || + !tmc_has_crash_mdata_buffer(drvdata)) + return 0; + + tmc_crashdata_set_invalid(drvdata); + + CS_UNLOCK(drvdata->base); + + /* Proceed only if ETF is enabled or configured as sink */ + val =3D readl(drvdata->base + TMC_CTL); + if (!(val & TMC_CTL_CAPT_EN)) + goto out; + + val =3D readl(drvdata->base + TMC_MODE); + if (val !=3D TMC_MODE_CIRCULAR_BUFFER) + goto out; + + val =3D readl(drvdata->base + TMC_FFSR); + /* Do manual flush and stop only if its not auto-stopped */ + if (!(val & TMC_FFSR_FT_STOPPED)) { + dev_info(&csdev->dev, + "%s: Triggering manual flush\n", __func__); + tmc_flush_and_stop(drvdata); + } else + tmc_wait_for_tmcready(drvdata); + + /* Sync registers from hardware to metadata region */ + mdata->sts =3D csdev_access_relaxed_read32(csa, TMC_STS); + mdata->mode =3D csdev_access_relaxed_read32(csa, TMC_MODE); + mdata->ffcr =3D csdev_access_relaxed_read32(csa, TMC_FFCR); + mdata->ffsr =3D csdev_access_relaxed_read32(csa, TMC_FFSR); + mdata->trace_paddr =3D drvdata->resrv_buf.paddr; + + /* Sync Internal SRAM to reserved trace buffer region */ + drvdata->buf =3D drvdata->resrv_buf.vaddr; + tmc_etb_dump_hw(drvdata); + /* Store as per RSZ register convention */ + mdata->size =3D drvdata->len >> 2; + mdata->version =3D CS_CRASHDATA_VERSION; + + /* + * Make sure all previous writes are completed, + * before we mark valid + */ + dsb(sy); + mdata->valid =3D true; + /* + * Below order need to maintained, since crc of metadata + * is dependent on first + */ + mdata->crc32_tdata =3D find_crash_tracedata_crc(drvdata, mdata); + mdata->crc32_mdata =3D find_crash_metadata_crc(mdata); + + tmc_disable_hw(drvdata); + + dev_info(&csdev->dev, "%s: success\n", __func__); +out: + CS_UNLOCK(drvdata->base); + return 0; +} + static const struct coresight_ops_sink tmc_etf_sink_ops =3D { .enable =3D tmc_enable_etf_sink, .disable =3D tmc_disable_etf_sink, @@ -603,6 +675,10 @@ static const struct coresight_ops_link tmc_etf_link_op= s =3D { .disable =3D tmc_disable_etf_link, }; =20 +static const struct coresight_ops_panic tmc_etf_sync_ops =3D { + .sync =3D tmc_panic_sync_etf, +}; + const struct coresight_ops tmc_etb_cs_ops =3D { .sink_ops =3D &tmc_etf_sink_ops, }; @@ -610,6 +686,7 @@ const struct coresight_ops tmc_etb_cs_ops =3D { const struct coresight_ops tmc_etf_cs_ops =3D { .sink_ops =3D &tmc_etf_sink_ops, .link_ops =3D &tmc_etf_link_ops, + .panic_ops =3D &tmc_etf_sync_ops, }; =20 int tmc_read_prepare_etb(struct tmc_drvdata *drvdata) diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtr= acing/coresight/coresight-tmc-etr.c index 8bca5b36334a..8228d7aaa361 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -1814,6 +1814,79 @@ static int tmc_disable_etr_sink(struct coresight_dev= ice *csdev) return 0; } =20 +static int tmc_panic_sync_etr(struct coresight_device *csdev) +{ + u32 val; + struct csdev_access *csa; + struct tmc_crash_metadata *mdata; + struct tmc_drvdata *drvdata =3D dev_get_drvdata(csdev->dev.parent); + + csa =3D &drvdata->csdev->access; + mdata =3D (struct tmc_crash_metadata *)drvdata->crash_mdata.vaddr; + + if (!drvdata->etr_buf) + return 0; + + /* Being in RESRV mode implies valid reserved memory as well */ + if (drvdata->etr_buf->mode !=3D ETR_MODE_RESRV) + return 0; + + if (!tmc_has_reserved_buffer(drvdata) || + !tmc_has_crash_mdata_buffer(drvdata)) + return 0; + + tmc_crashdata_set_invalid(drvdata); + + CS_UNLOCK(drvdata->base); + + /* Proceed only if ETR is enabled */ + val =3D readl(drvdata->base + TMC_CTL); + if (!(val & TMC_CTL_CAPT_EN)) + goto out; + + val =3D readl(drvdata->base + TMC_FFSR); + /* Do manual flush and stop only if its not auto-stopped */ + if (!(val & TMC_FFSR_FT_STOPPED)) { + dev_info(&csdev->dev, + "%s: Triggering manual flush\n", __func__); + tmc_flush_and_stop(drvdata); + } else + tmc_wait_for_tmcready(drvdata); + + /* Sync registers from hardware to metadata region */ + mdata->size =3D csdev_access_relaxed_read32(csa, TMC_RSZ); + mdata->sts =3D csdev_access_relaxed_read32(csa, TMC_STS); + mdata->mode =3D csdev_access_relaxed_read32(csa, TMC_MODE); + mdata->ffcr =3D csdev_access_relaxed_read32(csa, TMC_FFCR); + mdata->ffsr =3D csdev_access_relaxed_read32(csa, TMC_FFSR); + mdata->rrp =3D tmc_read_rrp(drvdata); + mdata->rwp =3D tmc_read_rwp(drvdata); + mdata->dba =3D tmc_read_dba(drvdata); + mdata->trace_paddr =3D drvdata->resrv_buf.paddr; + mdata->version =3D CS_CRASHDATA_VERSION; + + /* + * Make sure all previous writes are completed, + * before we mark valid + */ + dsb(sy); + mdata->valid =3D true; + /* + * Below order need to maintained, since crc of metadata + * is dependent on first + */ + mdata->crc32_tdata =3D find_crash_tracedata_crc(drvdata, mdata); + mdata->crc32_mdata =3D find_crash_metadata_crc(mdata); + + tmc_disable_hw(drvdata); + + dev_info(&csdev->dev, "%s: success\n", __func__); +out: + CS_UNLOCK(drvdata->base); + + return 0; +} + static const struct coresight_ops_sink tmc_etr_sink_ops =3D { .enable =3D tmc_enable_etr_sink, .disable =3D tmc_disable_etr_sink, @@ -1822,8 +1895,13 @@ static const struct coresight_ops_sink tmc_etr_sink_= ops =3D { .free_buffer =3D tmc_free_etr_buffer, }; =20 +static const struct coresight_ops_panic tmc_etr_sync_ops =3D { + .sync =3D tmc_panic_sync_etr, +}; + const struct coresight_ops tmc_etr_cs_ops =3D { .sink_ops =3D &tmc_etr_sink_ops, + .panic_ops =3D &tmc_etr_sync_ops, }; =20 int tmc_read_prepare_etr(struct tmc_drvdata *drvdata) diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracin= g/coresight/coresight-tmc.h index d2261eddab71..75e504e51956 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.h +++ b/drivers/hwtracing/coresight/coresight-tmc.h @@ -12,6 +12,7 @@ #include #include #include +#include =20 #define TMC_RSZ 0x004 #define TMC_STS 0x00c @@ -76,6 +77,9 @@ #define TMC_AXICTL_AXCACHE_OS (0xf << 2) #define TMC_AXICTL_ARCACHE_OS (0xf << 16) =20 +/* TMC_FFSR - 0x300 */ +#define TMC_FFSR_FT_STOPPED BIT(1) + /* TMC_FFCR - 0x304 */ #define TMC_FFCR_FLUSHMAN_BIT 6 #define TMC_FFCR_EN_FMT BIT(0) @@ -94,6 +98,9 @@ =20 #define TMC_AUTH_NSID_MASK GENMASK(1, 0) =20 +/* Major version 1 Minor version 0 */ +#define CS_CRASHDATA_VERSION (1 << 16) + enum tmc_config_type { TMC_CONFIG_TYPE_ETB, TMC_CONFIG_TYPE_ETR, @@ -131,6 +138,25 @@ enum tmc_mem_intf_width { #define CORESIGHT_SOC_600_ETR_CAPS \ (TMC_ETR_SAVE_RESTORE | TMC_ETR_AXI_ARCACHE) =20 +/* TMC metadata region for ETR and ETF configurations */ +struct tmc_crash_metadata { + uint32_t crc32_mdata; /* crc of metadata */ + uint32_t crc32_tdata; /* crc of tracedata */ + uint32_t version; /* 31:16 Major version, 15:0 Minor version */ + uint32_t valid; /* Indicate if this ETF/ETR was enabled */ + uint32_t size; /* Ram Size register */ + uint32_t sts; /* Status register */ + uint32_t mode; /* Mode register */ + uint64_t ffcr; /* Formatter and flush control register */ + uint64_t ffsr; /* Formatter and flush status register */ + uint32_t reserved32[3]; + uint64_t rrp; /* Ram Read pointer register */ + uint64_t rwp; /* Ram Write pointer register */ + uint64_t dba; /* Data buffer address register */ + uint64_t trace_paddr; /* Phys address of trace buffer */ + uint64_t reserved64[3]; +}; + enum etr_mode { ETR_MODE_FLAT, /* Uses contiguous flat buffer */ ETR_MODE_ETR_SG, /* Uses in-built TMC ETR SG mechanism */ @@ -205,6 +231,8 @@ struct tmc_resrv_buf { * retention (after crash) only when ETR_MODE_RESRV buffer * mode is enabled. Used by ETF for trace data retention * (after crash) by default. + * @crash_mdata: Reserved memory for storing tmc crash metadata. + * Used by ETR/ETF. */ struct tmc_drvdata { struct clk *pclk; @@ -231,6 +259,7 @@ struct tmc_drvdata { struct etr_buf *sysfs_buf; struct etr_buf *perf_buf; struct tmc_resrv_buf resrv_buf; + struct tmc_resrv_buf crash_mdata; }; =20 struct etr_buf_operations { @@ -356,6 +385,43 @@ static inline bool tmc_has_reserved_buffer(struct tmc_= drvdata *drvdata) return false; } =20 +static inline bool tmc_has_crash_mdata_buffer(struct tmc_drvdata *drvdata) +{ + if (drvdata->crash_mdata.vaddr && + drvdata->crash_mdata.size) + return true; + return false; +} + +static inline void tmc_crashdata_set_invalid(struct tmc_drvdata *drvdata) +{ + struct tmc_crash_metadata *mdata; + + mdata =3D (struct tmc_crash_metadata *)drvdata->crash_mdata.vaddr; + + if (tmc_has_crash_mdata_buffer(drvdata)) + mdata->valid =3D false; +} + +static inline uint32_t find_crash_metadata_crc(struct tmc_crash_metadata *= md) +{ + unsigned long crc_size; + + crc_size =3D sizeof(struct tmc_crash_metadata) - + offsetof(struct tmc_crash_metadata, crc32_tdata); + return crc32_le(0, (void *)&md->crc32_tdata, crc_size); +} + +static inline uint32_t find_crash_tracedata_crc(struct tmc_drvdata *drvdat= a, + struct tmc_crash_metadata *md) +{ + unsigned long crc_size; + + /* Take CRC of configured buffer size to keep it simple */ + crc_size =3D md->size << 2; + return crc32_le(0, (void *)drvdata->resrv_buf.vaddr, crc_size); +} + struct coresight_device *tmc_etr_get_catu_device(struct tmc_drvdata *drvda= ta); =20 void tmc_etr_set_catu_ops(const struct etr_buf_operations *catu); --=20 2.34.1 From nobody Fri Nov 29 18:35:20 2024 Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 409C115350B; Mon, 16 Sep 2024 10:35:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=67.231.156.173 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726482926; cv=none; b=hHYIZlU1EAL9XPNFbUS4y1LqMSwwqKn+lKAsGPu3SCKCZ4wUIeYiQG7LN+w3N2Q0FPp0ohdMoUDwGVuYB8Oxm9MSXVjVr3sIve+UB3vnmdyqGqymlk4QTkYNvIiipiI/dxQZxApJ0+41B+coXt62baLmOl19S2F9pYHNDtRd+/0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726482926; c=relaxed/simple; bh=UFXpNi7YIJTrOsswuSPqIW/4d7Bfn64PO9mkgI1/oPs=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Dzc3pmoPhJA2/aXSbHeqAsFvR/TZnUZCTiitJ53k95lq0cfKNKrRyeSKJFIV4exXzM/OosulL4eu2tUP8LEg/Fbw7i/VbAxeyygzpBWwWQpww3ERK+L7Ny6fzxkPXnGwrD2n+or0c3Aw0carrEfybPNttm8RxFosB94Z9vjhVE4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com; spf=pass smtp.mailfrom=marvell.com; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b=HBtugHWW; arc=none smtp.client-ip=67.231.156.173 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=marvell.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b="HBtugHWW" Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 48FMeVfQ017329; Mon, 16 Sep 2024 03:35:14 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=pfpt0220; bh=W XFEvKIP4/DCJfUZn9tIpiBgTOC39jiSetSrP4L3QbQ=; b=HBtugHWWIQzW5lCc6 2vMpGUtPDbNrHtLzGigEuCj66CThrZzeng2yjQ4ZoRfxNUbbiNkzFCYHdB6vEDr0 8n2N3UsT7lF6dqZNujUnG9kwrrK5+k9Kv+zzy4KOVaMITbgyYT2I46tcG1Uu6JLe N/xZ25fG0Nc46M0PGt/dzPfvypuwWo1h0B/8uRxK1PN9hCfZDhu/U6B61PCaE8jx Eeps5n45rZ70a+HMsKFxPespuEhrnEXKWpBWZP60dwCWE0se554hiDAJQjnpKQLf cfnkAfXm8zh5ZC882jAFCLTyLIaSHEnm0EfOFKzcJWFL7sdHQtzkf+LvYjIz4Zl0 Sp8wQ== Received: from dc6wp-exch02.marvell.com ([4.21.29.225]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 41na0fw3qm-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 16 Sep 2024 03:35:13 -0700 (PDT) Received: from DC6WP-EXCH02.marvell.com (10.76.176.209) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Mon, 16 Sep 2024 03:35:13 -0700 Received: from maili.marvell.com (10.69.176.80) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Mon, 16 Sep 2024 03:35:13 -0700 Received: from virtx40.. (unknown [10.28.34.196]) by maili.marvell.com (Postfix) with ESMTP id 589E33F704A; Mon, 16 Sep 2024 03:35:08 -0700 (PDT) From: Linu Cherian To: , , CC: , , , , , , , , , , , Linu Cherian , Anil Kumar Reddy , Tanmay Jagdale Subject: [PATCH v10 5/8] coresight: tmc: Add support for reading crash data Date: Mon, 16 Sep 2024 16:04:34 +0530 Message-ID: <20240916103437.226816-6-lcherian@marvell.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240916103437.226816-1-lcherian@marvell.com> References: <20240916103437.226816-1-lcherian@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: 1s_R8uBHdiLkJC6cqcVnpOFf-ZM_z0IP X-Proofpoint-GUID: 1s_R8uBHdiLkJC6cqcVnpOFf-ZM_z0IP X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 Content-Type: text/plain; charset="utf-8" * Add support for reading crashdata using special device files. The special device files /dev/crash_tmc_xxx would be available for read file operation only when the crash data is valid. * User can read the crash data as below For example, for reading crash data from tmc_etf sink #dd if=3D/dev/crash_tmc_etfXX of=3D~/cstrace.bin Signed-off-by: Anil Kumar Reddy Signed-off-by: Tanmay Jagdale Signed-off-by: Linu Cherian --- Changelog from v9: - Removed READ_CRASHDATA mode meant for special casing crashdata read - Added new fields full, len, offset to struct tmc_resrv_buf =20 so as to have a common read function for ETR and ETF - Introduced read file operation, tmc_crashdata_read specific to crashdata reads common for both ETR and ETF=20 - Introduced is_tmc_crashdata_valid function Special device file /dev/crash_tmc_xxx will be available only when crashdata is valid. - Version checks added to crashdata validity checks - Mark crashdata as invalid when user starts tracing with ETR sink in "resrv" buffer mode .../hwtracing/coresight/coresight-tmc-core.c | 206 +++++++++++++++++- .../hwtracing/coresight/coresight-tmc-etf.c | 36 +++ .../hwtracing/coresight/coresight-tmc-etr.c | 63 ++++++ drivers/hwtracing/coresight/coresight-tmc.h | 18 +- include/linux/coresight.h | 12 + 5 files changed, 333 insertions(+), 2 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwt= racing/coresight/coresight-tmc-core.c index 54bf8ae2bff8..47b6b3f88750 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-core.c +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c @@ -105,6 +105,125 @@ u32 tmc_get_memwidth_mask(struct tmc_drvdata *drvdata) return mask; } =20 +bool is_tmc_crashdata_valid(struct tmc_drvdata *drvdata) +{ + struct tmc_crash_metadata *mdata; + + if (!tmc_has_reserved_buffer(drvdata) || + !tmc_has_crash_mdata_buffer(drvdata)) + return false; + + mdata =3D drvdata->crash_mdata.vaddr; + + /* Check version match */ + if (mdata->version !=3D CS_CRASHDATA_VERSION) + return false; + + /* Check data integrity of metadata */ + if (mdata->crc32_mdata !=3D find_crash_metadata_crc(mdata)) { + dev_dbg(&drvdata->csdev->dev, + "CRC mismatch in tmc crash metadata\n"); + return false; + } + /* Check data integrity of tracedata */ + if (mdata->crc32_tdata !=3D find_crash_tracedata_crc(drvdata, mdata)) { + dev_dbg(&drvdata->csdev->dev, + "CRC mismatch in tmc crash tracedata\n"); + return false; + } + /* Check for valid metadata */ + if (!mdata->valid) { + dev_dbg(&drvdata->csdev->dev, + "Data invalid in tmc crash metadata\n"); + return false; + } + + return true; +} + +int tmc_read_prepare_crashdata(struct tmc_drvdata *drvdata) +{ + int ret =3D 0; + unsigned long flags; + struct tmc_crash_metadata *mdata; + struct coresight_device *csdev =3D drvdata->csdev; + + spin_lock_irqsave(&drvdata->spinlock, flags); + + if (!is_tmc_crashdata_valid(drvdata)) { + ret =3D -ENXIO; + goto out; + } + + mdata =3D drvdata->crash_mdata.vaddr; + /* + * Buffer address given by metadata for retrieval of trace data + * from previous boot is expected to be same as the reserved + * trace buffer memory region provided through DTS + */ + if (drvdata->resrv_buf.paddr !=3D mdata->trace_paddr) { + dev_dbg(&csdev->dev, "Trace buffer address of previous boot invalid\n"); + ret =3D -EINVAL; + goto out; + } + + /* Sink specific crashdata mode preparation */ + ret =3D crashdata_ops(csdev)->prepare(csdev); + if (ret) + goto out; + + if (mdata->sts & 0x1) + coresight_insert_barrier_packet(drvdata->buf); + + drvdata->reading =3D true; +out: + spin_unlock_irqrestore(&drvdata->spinlock, flags); + return ret; +} + +int tmc_read_unprepare_crashdata(struct tmc_drvdata *drvdata) +{ + int ret; + unsigned long flags; + struct coresight_device *csdev =3D drvdata->csdev; + + spin_lock_irqsave(&drvdata->spinlock, flags); + + /* Sink specific crashdata mode preparation */ + ret =3D crashdata_ops(csdev)->unprepare(csdev); + + drvdata->reading =3D false; + spin_unlock_irqrestore(&drvdata->spinlock, flags); + + return ret; +} + +static inline ssize_t tmc_get_resvbuf_trace(struct tmc_drvdata *drvdata, + loff_t pos, size_t len, char **bufpp) +{ + s64 offset; + ssize_t actual =3D len; + struct tmc_resrv_buf *rbuf =3D &drvdata->resrv_buf; + + if (pos + actual > rbuf->len) + actual =3D rbuf->len - pos; + if (actual <=3D 0) + return actual; + + /* Compute the offset from which we read the data */ + offset =3D rbuf->offset + pos; + if (offset >=3D rbuf->size) + offset -=3D rbuf->size; + + /* Adjust the length to limit this transaction to end of buffer */ + actual =3D (actual < (rbuf->size - offset)) ? + actual : rbuf->size - offset; + + *bufpp =3D (char *)rbuf->vaddr + offset; + + return actual; +} + static int tmc_read_prepare(struct tmc_drvdata *drvdata) { int ret =3D 0; @@ -224,6 +343,70 @@ static const struct file_operations tmc_fops =3D { .llseek =3D no_llseek, }; =20 +static int tmc_crashdata_open(struct inode *inode, struct file *file) +{ + int ret; + struct tmc_drvdata *drvdata =3D container_of(file->private_data, + struct tmc_drvdata, + crashdev); + + ret =3D tmc_read_prepare_crashdata(drvdata); + if (ret) + return ret; + + nonseekable_open(inode, file); + + dev_dbg(&drvdata->csdev->dev, "%s: successfully opened\n", __func__); + return 0; +} + +static ssize_t tmc_crashdata_read(struct file *file, char __user *data, + size_t len, loff_t *ppos) +{ + char *bufp; + ssize_t actual; + struct tmc_drvdata *drvdata =3D container_of(file->private_data, + struct tmc_drvdata, + crashdev); + + actual =3D tmc_get_resvbuf_trace(drvdata, *ppos, len, &bufp); + if (actual <=3D 0) + return 0; + + if (copy_to_user(data, bufp, actual)) { + dev_dbg(&drvdata->csdev->dev, + "%s: copy_to_user failed\n", __func__); + return -EFAULT; + } + + *ppos +=3D actual; + dev_dbg(&drvdata->csdev->dev, "%zu bytes copied\n", actual); + + return actual; + +} + +static int tmc_crashdata_release(struct inode *inode, struct file *file) +{ + int ret =3D 0; + struct tmc_drvdata *drvdata =3D container_of(file->private_data, + struct tmc_drvdata, + crashdev); + + ret =3D tmc_read_unprepare_crashdata(drvdata); + + dev_dbg(&drvdata->csdev->dev, "%s: released\n", __func__); + return ret; +} + +static const struct file_operations tmc_crashdata_fops =3D { + .owner =3D THIS_MODULE, + .open =3D tmc_crashdata_open, + .read =3D tmc_crashdata_read, + .release =3D tmc_crashdata_release, + .llseek =3D no_llseek, +}; + static enum tmc_mem_intf_width tmc_get_memwidth(u32 devid) { enum tmc_mem_intf_width memwidth; @@ -533,6 +716,20 @@ static u32 tmc_etr_get_max_burst_size(struct device *d= ev) return burst_size; } =20 +static void register_crash_dev_interface(struct tmc_drvdata *drvdata, + const char *name) +{ + drvdata->crashdev.name =3D + devm_kasprintf(&drvdata->csdev->dev, GFP_KERNEL, "%s_%s", "crash", name); + drvdata->crashdev.minor =3D MISC_DYNAMIC_MINOR; + drvdata->crashdev.fops =3D &tmc_crashdata_fops; + if (misc_register(&drvdata->crashdev)) { + dev_dbg(&drvdata->csdev->dev, + "Failed to setup user interface for crashdata\n"); + drvdata->crashdev.fops =3D NULL; + } +} + static int __tmc_probe(struct device *dev, struct resource *res) { int ret =3D 0; @@ -633,8 +830,13 @@ static int __tmc_probe(struct device *dev, struct reso= urce *res) drvdata->miscdev.minor =3D MISC_DYNAMIC_MINOR; drvdata->miscdev.fops =3D &tmc_fops; ret =3D misc_register(&drvdata->miscdev); - if (ret) + if (ret) { coresight_unregister(drvdata->csdev); + goto out; + } + + if (is_tmc_crashdata_valid(drvdata)) + register_crash_dev_interface(drvdata, desc.name); out: return ret; } @@ -688,6 +890,8 @@ static void __tmc_remove(struct device *dev) * handler to this device is closed. */ misc_deregister(&drvdata->miscdev); + if (drvdata->crashdev.fops) + misc_deregister(&drvdata->crashdev); coresight_unregister(drvdata->csdev); } =20 diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtr= acing/coresight/coresight-tmc-etf.c index d77ec9307e98..2b4639a1def2 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c @@ -662,6 +662,36 @@ static int tmc_panic_sync_etf(struct coresight_device = *csdev) return 0; } =20 +static int tmc_etb_prepare_crashdata(struct coresight_device *csdev) +{ + unsigned long size; + struct tmc_resrv_buf *rbuf; + struct tmc_crash_metadata *mdata; + struct tmc_drvdata *drvdata =3D dev_get_drvdata(csdev->dev.parent); + + rbuf =3D &drvdata->resrv_buf; + mdata =3D drvdata->crash_mdata.vaddr; + size =3D mdata->size << 2; + + rbuf->len =3D size; + rbuf->offset =3D 0; + rbuf->full =3D 0; + + return 0; +} + +static int tmc_etb_unprepare_crashdata(struct coresight_device *csdev) +{ + struct tmc_resrv_buf *rbuf; + struct tmc_drvdata *drvdata =3D dev_get_drvdata(csdev->dev.parent); + + rbuf =3D &drvdata->resrv_buf; + /* Reset valid length */ + rbuf->len =3D 0; + + return 0; +} + static const struct coresight_ops_sink tmc_etf_sink_ops =3D { .enable =3D tmc_enable_etf_sink, .disable =3D tmc_disable_etf_sink, @@ -679,6 +709,11 @@ static const struct coresight_ops_panic tmc_etf_sync_o= ps =3D { .sync =3D tmc_panic_sync_etf, }; =20 +static const struct coresight_ops_crashdata tmc_etf_crashdata_ops =3D { + .prepare =3D tmc_etb_prepare_crashdata, + .unprepare =3D tmc_etb_unprepare_crashdata, +}; + const struct coresight_ops tmc_etb_cs_ops =3D { .sink_ops =3D &tmc_etf_sink_ops, }; @@ -687,6 +722,7 @@ const struct coresight_ops tmc_etf_cs_ops =3D { .sink_ops =3D &tmc_etf_sink_ops, .link_ops =3D &tmc_etf_link_ops, .panic_ops =3D &tmc_etf_sync_ops, + .crashdata_ops =3D &tmc_etf_crashdata_ops, }; =20 int tmc_read_prepare_etb(struct tmc_drvdata *drvdata) diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtr= acing/coresight/coresight-tmc-etr.c index 8228d7aaa361..7688b8d70ced 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -1887,6 +1887,55 @@ static int tmc_panic_sync_etr(struct coresight_devic= e *csdev) return 0; } =20 +static int tmc_etr_prepare_crashdata(struct coresight_device *csdev) +{ + u32 status; + u64 rrp, rwp, dba; + struct tmc_resrv_buf *rbuf; + struct tmc_crash_metadata *mdata; + struct tmc_drvdata *drvdata =3D dev_get_drvdata(csdev->dev.parent); + + rbuf =3D &drvdata->resrv_buf; + mdata =3D drvdata->crash_mdata.vaddr; + + rrp =3D mdata->rrp; + rwp =3D mdata->rwp; + dba =3D mdata->dba; + status =3D mdata->sts; + + rbuf->full =3D !!(status & TMC_STS_FULL); + + /* Sync the buffer pointers */ + rbuf->offset =3D rrp - dba; + if (rbuf->full) + rbuf->len =3D rbuf->size; + else + rbuf->len =3D rwp - rrp; + + /* Additional sanity checks for validating metadata */ + if ((rbuf->offset > rbuf->size) || + (rbuf->len > rbuf->size)) { + dev_dbg(&drvdata->csdev->dev, + "Offset and length invalid in tmc crash metadata\n"); + return -EINVAL; + } + + return 0; +} + +static int tmc_etr_unprepare_crashdata(struct coresight_device *csdev) +{ + struct tmc_resrv_buf *rbuf; + struct tmc_drvdata *drvdata =3D dev_get_drvdata(csdev->dev.parent); + + rbuf =3D &drvdata->resrv_buf; + + /* Reset valid length */ + rbuf->len =3D 0; + + return 0; +} + static const struct coresight_ops_sink tmc_etr_sink_ops =3D { .enable =3D tmc_enable_etr_sink, .disable =3D tmc_disable_etr_sink, @@ -1899,9 +1948,15 @@ static const struct coresight_ops_panic tmc_etr_sync= _ops =3D { .sync =3D tmc_panic_sync_etr, }; =20 +static const struct coresight_ops_crashdata tmc_etr_crashdata_ops =3D { + .prepare =3D tmc_etr_prepare_crashdata, + .unprepare =3D tmc_etr_unprepare_crashdata, +}; + const struct coresight_ops tmc_etr_cs_ops =3D { .sink_ops =3D &tmc_etr_sink_ops, .panic_ops =3D &tmc_etr_sync_ops, + .crashdata_ops =3D &tmc_etr_crashdata_ops, }; =20 int tmc_read_prepare_etr(struct tmc_drvdata *drvdata) @@ -1934,6 +1989,14 @@ int tmc_read_prepare_etr(struct tmc_drvdata *drvdata) __tmc_etr_disable_hw(drvdata); =20 drvdata->reading =3D true; + + /* + * The only other place we mark the metadata invalid is during + * panic handler. Normally this won't race with panic handler, + * as all cpus would be stopped before running panic handler. + */ + if (drvdata->etr_mode =3D=3D ETR_MODE_RESRV) + tmc_crashdata_set_invalid(drvdata); out: spin_unlock_irqrestore(&drvdata->spinlock, flags); =20 diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracin= g/coresight/coresight-tmc.h index 75e504e51956..a6daa35c7cc1 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.h +++ b/drivers/hwtracing/coresight/coresight-tmc.h @@ -195,11 +195,17 @@ struct etr_buf { * @paddr : Start address of reserved memory region. * @vaddr : Corresponding CPU virtual address. * @size : Size of reserved memory region. + * @full : Trace data overflow + * @offset : Offset of the trace data in the buffer for consumption. + * @len : Available trace data @buf (may round up to the beginning). */ struct tmc_resrv_buf { phys_addr_t paddr; void *vaddr; size_t size; + bool full; + unsigned long offset; + s64 len; }; =20 /** @@ -208,6 +214,8 @@ struct tmc_resrv_buf { * @base: memory mapped base address for this component. * @csdev: component vitals needed by the framework. * @miscdev: specifics to handle "/dev/xyz.tmc" entry. + * @crashdev: specifics to handle "/dev/crash_tmc_xyz" entry for reading + * crash tracedata. * @spinlock: only one at a time pls. * @pid: Process ID of the process that owns the session that is using * this component. For example this would be the pid of the Perf @@ -227,7 +235,10 @@ struct tmc_resrv_buf { * @idr_mutex: Access serialisation for idr. * @sysfs_buf: SYSFS buffer for ETR. * @perf_buf: PERF buffer for ETR. - * @resrv_buf: Used by ETR as hardware trace buffer and for trace data + * @sysfs_crash_buf: Sysfs crashdata buffer for ETR. This is a special pur= pose + * buffer that is used only for mapping the trace buffer from + * previous crash and not for capturing trace. + * @resrv_buf: Used by ETR as hardware trace buffer and for trace data * retention (after crash) only when ETR_MODE_RESRV buffer * mode is enabled. Used by ETF for trace data retention * (after crash) by default. @@ -239,6 +250,7 @@ struct tmc_drvdata { void __iomem *base; struct coresight_device *csdev; struct miscdevice miscdev; + struct miscdevice crashdev; spinlock_t spinlock; pid_t pid; bool reading; @@ -309,6 +321,8 @@ void tmc_flush_and_stop(struct tmc_drvdata *drvdata); void tmc_enable_hw(struct tmc_drvdata *drvdata); void tmc_disable_hw(struct tmc_drvdata *drvdata); u32 tmc_get_memwidth_mask(struct tmc_drvdata *drvdata); +int tmc_read_prepare_crashdata(struct tmc_drvdata *drvdata); +int tmc_read_unprepare_crashdata(struct tmc_drvdata *drvdata); =20 /* ETB/ETF functions */ int tmc_read_prepare_etb(struct tmc_drvdata *drvdata); @@ -371,6 +385,8 @@ void tmc_sg_table_sync_data_range(struct tmc_sg_table *= table, u64 offset, u64 size); ssize_t tmc_sg_table_get_data(struct tmc_sg_table *sg_table, u64 offset, size_t len, char **bufpp); + +bool is_tmc_crashdata_valid(struct tmc_drvdata *drvdata); static inline unsigned long tmc_sg_table_buf_size(struct tmc_sg_table *sg_table) { diff --git a/include/linux/coresight.h b/include/linux/coresight.h index 2e63f7614551..f04e40828885 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -336,6 +336,7 @@ enum cs_mode { #define helper_ops(csdev) csdev->ops->helper_ops #define ect_ops(csdev) csdev->ops->ect_ops #define panic_ops(csdev) csdev->ops->panic_ops +#define crashdata_ops(csdev) csdev->ops->crashdata_ops =20 /** * struct coresight_ops_sink - basic operations for a sink @@ -415,12 +416,23 @@ struct coresight_ops_panic { int (*sync)(struct coresight_device *csdev); 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(unknown [10.28.34.196]) by maili.marvell.com (Postfix) with ESMTP id 64ADD3F704A; Mon, 16 Sep 2024 03:35:13 -0700 (PDT) From: Linu Cherian To: , , CC: , , , , , , , , , , , Linu Cherian Subject: [PATCH v10 6/8] coresight: tmc: Stop trace capture on FlIn Date: Mon, 16 Sep 2024 16:04:35 +0530 Message-ID: <20240916103437.226816-7-lcherian@marvell.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240916103437.226816-1-lcherian@marvell.com> References: <20240916103437.226816-1-lcherian@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: Jz7YMrCXcEwxChBgO3TgDyR8-o7AEi-c X-Proofpoint-GUID: Jz7YMrCXcEwxChBgO3TgDyR8-o7AEi-c X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 Content-Type: text/plain; charset="utf-8" Configure TMC ETR and ETF to flush and stop trace capture on FlIn event based on sysfs attribute, /sys/bus/coresight/devices/tmc_etXn/stop_on_flush. Signed-off-by: Linu Cherian --- Changelog from v9: No changes .../hwtracing/coresight/coresight-tmc-core.c | 31 +++++++++++++++++++ .../hwtracing/coresight/coresight-tmc-etf.c | 12 ++++--- .../hwtracing/coresight/coresight-tmc-etr.c | 12 ++++--- drivers/hwtracing/coresight/coresight-tmc.h | 2 ++ 4 files changed, 47 insertions(+), 10 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwt= racing/coresight/coresight-tmc-core.c index 47b6b3f88750..73888cd9b832 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-core.c +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c @@ -516,9 +516,40 @@ static ssize_t buffer_size_store(struct device *dev, =20 static DEVICE_ATTR_RW(buffer_size); =20 +static ssize_t stop_on_flush_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct tmc_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + + return sprintf(buf, "%#x\n", drvdata->stop_on_flush); +} + +static ssize_t stop_on_flush_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + int ret; + u8 val; + struct tmc_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + + ret =3D kstrtou8(buf, 0, &val); + if (ret) + return ret; + if (val) + drvdata->stop_on_flush =3D true; + else + drvdata->stop_on_flush =3D false; + + return size; +} + +static DEVICE_ATTR_RW(stop_on_flush); + + static struct attribute *coresight_tmc_attrs[] =3D { &dev_attr_trigger_cntr.attr, &dev_attr_buffer_size.attr, + &dev_attr_stop_on_flush.attr, NULL, }; =20 diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtr= acing/coresight/coresight-tmc-etf.c index 2b4639a1def2..ef7dd1f79cff 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c @@ -19,6 +19,7 @@ static int tmc_set_etf_buffer(struct coresight_device *cs= dev, static int __tmc_etb_enable_hw(struct tmc_drvdata *drvdata) { int rc =3D 0; + u32 ffcr; =20 CS_UNLOCK(drvdata->base); =20 @@ -32,10 +33,12 @@ static int __tmc_etb_enable_hw(struct tmc_drvdata *drvd= ata) } =20 writel_relaxed(TMC_MODE_CIRCULAR_BUFFER, drvdata->base + TMC_MODE); - writel_relaxed(TMC_FFCR_EN_FMT | TMC_FFCR_EN_TI | - TMC_FFCR_FON_FLIN | TMC_FFCR_FON_TRIG_EVT | - TMC_FFCR_TRIGON_TRIGIN, - drvdata->base + TMC_FFCR); + + ffcr =3D TMC_FFCR_EN_FMT | TMC_FFCR_EN_TI | TMC_FFCR_FON_FLIN | + TMC_FFCR_FON_TRIG_EVT | TMC_FFCR_TRIGON_TRIGIN; + if (drvdata->stop_on_flush) + ffcr |=3D TMC_FFCR_STOP_ON_FLUSH; + writel_relaxed(ffcr, drvdata->base + TMC_FFCR); =20 writel_relaxed(drvdata->trigger_cntr, drvdata->base + TMC_TRG); tmc_enable_hw(drvdata); @@ -225,7 +228,6 @@ static int tmc_enable_etf_sink_sysfs(struct coresight_d= evice *csdev) used =3D true; drvdata->buf =3D buf; } - ret =3D tmc_etb_enable_hw(drvdata); if (!ret) { coresight_set_mode(csdev, CS_MODE_SYSFS); diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtr= acing/coresight/coresight-tmc-etr.c index 7688b8d70ced..0069ae65a03a 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -1060,7 +1060,7 @@ static void tmc_sync_etr_buf(struct tmc_drvdata *drvd= ata) =20 static int __tmc_etr_enable_hw(struct tmc_drvdata *drvdata) { - u32 axictl, sts; + u32 axictl, sts, ffcr; struct etr_buf *etr_buf =3D drvdata->etr_buf; int rc =3D 0; =20 @@ -1106,10 +1106,12 @@ static int __tmc_etr_enable_hw(struct tmc_drvdata *= drvdata) writel_relaxed(sts, drvdata->base + TMC_STS); } =20 - writel_relaxed(TMC_FFCR_EN_FMT | TMC_FFCR_EN_TI | - TMC_FFCR_FON_FLIN | TMC_FFCR_FON_TRIG_EVT | - TMC_FFCR_TRIGON_TRIGIN, - drvdata->base + TMC_FFCR); + ffcr =3D TMC_FFCR_EN_FMT | TMC_FFCR_EN_TI | TMC_FFCR_FON_FLIN | + TMC_FFCR_FON_TRIG_EVT | TMC_FFCR_TRIGON_TRIGIN; + if (drvdata->stop_on_flush) + ffcr |=3D TMC_FFCR_STOP_ON_FLUSH; + writel_relaxed(ffcr, drvdata->base + TMC_FFCR); + writel_relaxed(drvdata->trigger_cntr, drvdata->base + TMC_TRG); tmc_enable_hw(drvdata); =20 diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracin= g/coresight/coresight-tmc.h index a6daa35c7cc1..c33b32542d9d 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.h +++ b/drivers/hwtracing/coresight/coresight-tmc.h @@ -220,6 +220,7 @@ struct tmc_resrv_buf { * @pid: Process ID of the process that owns the session that is using * this component. For example this would be the pid of the Perf * process. + * @stop_on_flush: Stop on flush trigger user configuration. * @buf: Snapshot of the trace data for ETF/ETB. * @etr_buf: details of buffer used in TMC-ETR * @len: size of the available trace for ETF/ETB. @@ -254,6 +255,7 @@ struct tmc_drvdata { spinlock_t spinlock; pid_t pid; bool reading; + bool stop_on_flush; union { char *buf; /* TMC ETB */ struct etr_buf *etr_buf; /* TMC ETR */ --=20 2.34.1 From nobody Fri Nov 29 18:35:20 2024 Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 683E4156F39; Mon, 16 Sep 2024 10:35:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=67.231.156.173 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726482934; cv=none; b=dRL6X5/nMCmAJiQuFvljhzaCvSeKNA89Ybrnn4GzT8qqQanf9IYY8s0V+4tlf5xtR9bBsgiYOVa9iln7/c0yX8o8ePGcq5SBypqKDV13SLXcobU03XvIBjzr6f8Vg6/Zgd0FFiviPqD1JNG+TSGE5soyW0pkp8K/f2EbGXnbpQk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726482934; c=relaxed/simple; bh=dh2KZ3MU3peeJ1EWFD1K78A1DTC5gBRwSR307nYcDQ8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=K07aYnNHWFAkHET+6AfVtFiOJKL/pdLw8x9a+pQjT+pQmktEnglVKn5zU7omww1adxKMRvqvC5dQsJDin71ahbyJXxSHUUZFe1P9zU5oXzYO0zvDsdGV/6S31I0gme6XyTt8ikKAKnph1g7KxJZp41h3waBgEGIlQPx/UcNzCKw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com; spf=pass smtp.mailfrom=marvell.com; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b=QfJwdIUa; arc=none smtp.client-ip=67.231.156.173 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=marvell.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b="QfJwdIUa" Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 48FLdfA4017267; Mon, 16 Sep 2024 03:35:23 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=pfpt0220; bh=v AJpyUxQJLXyqdEeA0uvNidm1mJvFhpbhsg8Y9G0atQ=; b=QfJwdIUa+o/8rC4XV YKKrHtGdYLqVpJqoRFsqz5JDro0uDCT7G/GEn+vqv5DZASlEGnLG69yeB4rxj4ok Ga3WvHYk4sMlwDKztXpHRsN1OxCN4rUsFKwjx0CDQcpWnetxO37G+zjBCX+7qWZZ TuwnqfQRCxKXUPlsX2Xdpvqh5897M2ZeQ5bwLFp3pe3GWwFkJ7By8hMdyQGC6hUR zGxI22qBA65y+Yk4KooE6l2wmyOHTAqjpJP/TDVIZusTc7zW+iTMac/4HG2f6fKg fYdcwbTQskwYnA9cOZ9iTRPjzljZb09UsixgmwCIwnZQsUKRhygMGniRDdcCooDO dKH0w== Received: from dc6wp-exch02.marvell.com ([4.21.29.225]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 41na0fw3r6-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 16 Sep 2024 03:35:22 -0700 (PDT) Received: from DC6WP-EXCH02.marvell.com (10.76.176.209) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Mon, 16 Sep 2024 03:35:22 -0700 Received: from maili.marvell.com (10.69.176.80) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Mon, 16 Sep 2024 03:35:22 -0700 Received: from virtx40.. (unknown [10.28.34.196]) by maili.marvell.com (Postfix) with ESMTP id 000963F704A; Mon, 16 Sep 2024 03:35:17 -0700 (PDT) From: Linu Cherian To: , , CC: , , , , , , , , , , , Linu Cherian Subject: [PATCH v10 7/8] coresight: config: Add preloaded configuration Date: Mon, 16 Sep 2024 16:04:36 +0530 Message-ID: <20240916103437.226816-8-lcherian@marvell.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240916103437.226816-1-lcherian@marvell.com> References: <20240916103437.226816-1-lcherian@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: r10xwRqmuVAZ-Rcho89EqxYvKV5eKJtE X-Proofpoint-GUID: r10xwRqmuVAZ-Rcho89EqxYvKV5eKJtE X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 Content-Type: text/plain; charset="utf-8" Add a preloaded configuration for generating external trigger on address match. This can be used by CTI and ETR blocks to stop trace capture on kernel panic. Kernel address for "panic" function is used as the default trigger address. This new configuration is available as, /sys/kernel/config/cs-syscfg/configurations/panicstop Signed-off-by: Linu Cherian Reviewed-by: James Clark --- Changelog from v9: No changes drivers/hwtracing/coresight/Makefile | 2 +- .../coresight/coresight-cfg-preload.c | 2 + .../coresight/coresight-cfg-preload.h | 2 + .../hwtracing/coresight/coresight-cfg-pstop.c | 83 +++++++++++++++++++ 4 files changed, 88 insertions(+), 1 deletion(-) create mode 100644 drivers/hwtracing/coresight/coresight-cfg-pstop.c diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/cores= ight/Makefile index 4ba478211b31..46ce7f39d05f 100644 --- a/drivers/hwtracing/coresight/Makefile +++ b/drivers/hwtracing/coresight/Makefile @@ -25,7 +25,7 @@ subdir-ccflags-y +=3D $(condflags) obj-$(CONFIG_CORESIGHT) +=3D coresight.o coresight-y :=3D coresight-core.o coresight-etm-perf.o coresight-platform= .o \ coresight-sysfs.o coresight-syscfg.o coresight-config.o \ - coresight-cfg-preload.o coresight-cfg-afdo.o \ + coresight-cfg-preload.o coresight-cfg-afdo.o coresight-cfg-pstop.o \ coresight-syscfg-configfs.o coresight-trace-id.o obj-$(CONFIG_CORESIGHT_LINK_AND_SINK_TMC) +=3D coresight-tmc.o coresight-tmc-y :=3D coresight-tmc-core.o coresight-tmc-etf.o \ diff --git a/drivers/hwtracing/coresight/coresight-cfg-preload.c b/drivers/= hwtracing/coresight/coresight-cfg-preload.c index e237a4edfa09..4980e68483c5 100644 --- a/drivers/hwtracing/coresight/coresight-cfg-preload.c +++ b/drivers/hwtracing/coresight/coresight-cfg-preload.c @@ -13,6 +13,7 @@ static struct cscfg_feature_desc *preload_feats[] =3D { #if IS_ENABLED(CONFIG_CORESIGHT_SOURCE_ETM4X) &strobe_etm4x, + &gen_etrig_etm4x, #endif NULL }; @@ -20,6 +21,7 @@ static struct cscfg_feature_desc *preload_feats[] =3D { static struct cscfg_config_desc *preload_cfgs[] =3D { #if IS_ENABLED(CONFIG_CORESIGHT_SOURCE_ETM4X) &afdo_etm4x, + &pstop_etm4x, #endif NULL }; diff --git a/drivers/hwtracing/coresight/coresight-cfg-preload.h b/drivers/= hwtracing/coresight/coresight-cfg-preload.h index 21299e175477..291ba530a6a5 100644 --- a/drivers/hwtracing/coresight/coresight-cfg-preload.h +++ b/drivers/hwtracing/coresight/coresight-cfg-preload.h @@ -10,4 +10,6 @@ #if IS_ENABLED(CONFIG_CORESIGHT_SOURCE_ETM4X) extern struct cscfg_feature_desc strobe_etm4x; extern struct cscfg_config_desc afdo_etm4x; +extern struct cscfg_feature_desc gen_etrig_etm4x; +extern struct cscfg_config_desc pstop_etm4x; #endif diff --git a/drivers/hwtracing/coresight/coresight-cfg-pstop.c b/drivers/hw= tracing/coresight/coresight-cfg-pstop.c new file mode 100644 index 000000000000..c2bfbd07bfaf --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-cfg-pstop.c @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright(C) 2023 Marvell. + * Based on coresight-cfg-afdo.c + */ + +#include "coresight-config.h" + +/* ETMv4 includes and features */ +#if IS_ENABLED(CONFIG_CORESIGHT_SOURCE_ETM4X) +#include "coresight-etm4x-cfg.h" + +/* preload configurations and features */ + +/* preload in features for ETMv4 */ + +/* panic_stop feature */ +static struct cscfg_parameter_desc gen_etrig_params[] =3D { + { + .name =3D "address", + .value =3D (u64)panic, + }, +}; + +static struct cscfg_regval_desc gen_etrig_regs[] =3D { + /* resource selector */ + { + .type =3D CS_CFG_REG_TYPE_RESOURCE, + .offset =3D TRCRSCTLRn(2), + .hw_info =3D ETM4_CFG_RES_SEL, + .val32 =3D 0x40001, + }, + /* single address comparator */ + { + .type =3D CS_CFG_REG_TYPE_RESOURCE | CS_CFG_REG_TYPE_VAL_64BIT | + CS_CFG_REG_TYPE_VAL_PARAM, + .offset =3D TRCACVRn(0), + .val32 =3D 0x0, + }, + { + .type =3D CS_CFG_REG_TYPE_RESOURCE, + .offset =3D TRCACATRn(0), + .val64 =3D 0xf00, + }, + /* Driver external output[0] with comparator out */ + { + .type =3D CS_CFG_REG_TYPE_RESOURCE, + .offset =3D TRCEVENTCTL0R, + .val32 =3D 0x2, + }, + /* end of regs */ +}; + +struct cscfg_feature_desc gen_etrig_etm4x =3D { + .name =3D "gen_etrig", + .description =3D "Generate external trigger on address match\n" + "parameter \'address\': address of kernel address\n", + .match_flags =3D CS_CFG_MATCH_CLASS_SRC_ETM4, + .nr_params =3D ARRAY_SIZE(gen_etrig_params), + .params_desc =3D gen_etrig_params, + .nr_regs =3D ARRAY_SIZE(gen_etrig_regs), + .regs_desc =3D gen_etrig_regs, +}; + +/* create a panic stop configuration */ + +/* the total number of parameters in used features */ +#define PSTOP_NR_PARAMS ARRAY_SIZE(gen_etrig_params) + +static const char *pstop_ref_names[] =3D { + "gen_etrig", +}; + +struct cscfg_config_desc pstop_etm4x =3D { + .name =3D "panicstop", + .description =3D "Stop ETM on kernel panic\n", + .nr_feat_refs =3D ARRAY_SIZE(pstop_ref_names), + .feat_ref_names =3D pstop_ref_names, + .nr_total_params =3D PSTOP_NR_PARAMS, +}; + +/* end of ETM4x configurations */ +#endif /* IS_ENABLED(CONFIG_CORESIGHT_SOURCE_ETM4X) */ --=20 2.34.1 From nobody Fri Nov 29 18:35:20 2024 Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E799A156F57; Mon, 16 Sep 2024 10:35:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=67.231.148.174 ARC-Seal: i=1; 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(unknown [10.28.34.196]) by maili.marvell.com (Postfix) with ESMTP id 8DEF83F704A; Mon, 16 Sep 2024 03:35:22 -0700 (PDT) From: Linu Cherian To: , , CC: , , , , , , , , , , , Linu Cherian Subject: [PATCH v10 8/8] Documentation: coresight: Panic support Date: Mon, 16 Sep 2024 16:04:37 +0530 Message-ID: <20240916103437.226816-9-lcherian@marvell.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240916103437.226816-1-lcherian@marvell.com> References: <20240916103437.226816-1-lcherian@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: Wcog7m0PQL297n61BwDdtnx5tw49u0wy X-Proofpoint-ORIG-GUID: Wcog7m0PQL297n61BwDdtnx5tw49u0wy X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 Content-Type: text/plain; charset="utf-8" Add documentation on using coresight during panic and watchdog. Signed-off-by: Linu Cherian --- Changelog from v9: This patch has been newly introduced. Documentation/trace/coresight/panic.rst | 356 ++++++++++++++++++++++++ 1 file changed, 356 insertions(+) create mode 100644 Documentation/trace/coresight/panic.rst diff --git a/Documentation/trace/coresight/panic.rst b/Documentation/trace/= coresight/panic.rst new file mode 100644 index 000000000000..3b53d91cace8 --- /dev/null +++ b/Documentation/trace/coresight/panic.rst @@ -0,0 +1,356 @@ +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D +Using Coresight for Kernel panic and Watchdog reset +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D + +Introduction +------------ +This documentation is about using Linux coresight trace support to +debug kernel panic and watchdog reset scenarios. + +Coresight trace during Kernel panic +----------------------------------- +From the coresight driver point of view, addressing the kernel panic +situation has four main requirements. + +a. Support for allocation of trace buffer pages from reserved memory area. + Platform can advertise this using a new device tree property added to + relevant coresight nodes. + +b. Support for stopping coresight blocks at the time of panic + +c. Saving required metadata in the specified format + +d. Support for reading trace data captured at the time of panic + +Allocation of trace buffer pages from reserved RAM +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +A new optional device tree property "memory-region" is added to the +ETR/ETF device nodes, that would give the base address and size of trace +buffer. + +Static allocation of trace buffers would ensure that both IOMMU enabled +and disabled cases are handled. Also, platforms that support persistent +RAM will allow users to read trace data in the subsequent boot without +booting the crashdump kernel. + +Note: +For ETR sink devices, this reserved region will be used for both trace +capture and trace data retrieval. +For ETF sink devices, internal SRAM would be used for trace capture, +and they would be synced to reserved region for retrieval. + + +Disabling coresight blocks at the time of panic +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +In order to avoid the situation of losing relevant trace data after a +kernel panic, it would be desirable to stop the coresight blocks at the +time of panic. + +This can be achieved by configuring the comparator, CTI and sink +devices as below:: + + Trigger on panic + Comparator --->External out --->CTI -->External In---->ETR/ETF stop + +Saving metadata at the time of kernel panic +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +Coresight metadata involves all additional data that are required for a +successful trace decode in addition to the trace data. This involves +ETR/ETF, ETE register snapshot etc. + +A new optional device property "memory-region" is added to +the ETR/ETF/ETE device nodes for this. + +Reading trace data captured at the time of panic +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +Trace data captured at the time of panic, can be read from rebooted kernel +or from crashdump kernel using a special device file /dev/crash_tmc_xxx. +This device file is created only when there is a valid crashdata available. + +General flow of trace capture and decode incase of kernel panic +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +1. Enable source and sink on all the cores using the sysfs interface. + ETR sinks should have trace buffers allocated from reserved memory, + by selecting "resrv" buffer mode from sysfs. + +2. Run relevant tests. + +3. On a kernel panic, all coresight blocks are disabled, necessary + metadata is synced by kernel panic handler. + + System would eventually reboot or boot a crashdump kernel. + +4. For platforms that supports crashdump kernel, raw trace data can be + dumped using the coresight sysfs interface from the crashdump kernel + itself. Persistent RAM is not a requirement in this case. + +5. For platforms that supports persistent RAM, trace data can be dumped + using the coresight sysfs interface in the subsequent Linux boot. + Crashdump kernel is not a requirement in this case. Persistent RAM + ensures that trace data is intact across reboot. + +Coresight trace during Watchdog reset +------------------------------------- +The main difference between addressing the watchdog reset and kernel panic +case are below, + +a. Saving coresight metadata need to be taken care by the + SCP(system control processor) firmware in the specified format, + instead of kernel. + +b. Reserved memory region given by firmware for trace buffer and metadata + has to be in persistent RAM. + Note: This is a requirement for watchdog reset case but optional + in kernel panic case. + +Watchdog reset can be supported only on platforms that meet the above +two requirements. + +Sample commands for testing a Kernel panic case with ETR sink +------------------------------------------------------------- + +1. Boot Linux kernel with "crash_kexec_post_notifiers" added to the kernel + bootargs. This is mandatory if the user would like to read the tracedata + from the crashdump kernel. + +2. Enable the preloaded ETM configuration + + #echo 1 > /sys/kernel/config/cs-syscfg/configurations/panicstop/enable + +3. Configure CTI using sysfs interface:: + + #./cti_setup.sh + + #cat cti_setup.sh + + + cd /sys/bus/coresight/devices/ + + ap_cti_config () { + #ETM trig out[0] trigger to Channel 0 + echo 0 4 > channels/trigin_attach + } + + etf_cti_config () { + #ETF Flush in trigger from Channel 0 + echo 0 1 > channels/trigout_attach + echo 1 > channels/trig_filter_enable + } + + etr_cti_config () { + #ETR Flush in from Channel 0 + echo 0 1 > channels/trigout_attach + echo 1 > channels/trig_filter_enable + } + + ctidevs=3D`find . -name "cti*"` + + for i in $ctidevs + do + cd $i + + connection=3D`find . -name "ete*"` + if [ ! -z "$connection" ] + then + echo "AP CTI config for $i" + ap_cti_config + fi + + connection=3D`find . -name "tmc_etf*"` + if [ ! -z "$connection" ] + then + echo "ETF CTI config for $i" + etf_cti_config + fi + + connection=3D`find . -name "tmc_etr*"` + if [ ! -z "$connection" ] + then + echo "ETR CTI config for $i" + etr_cti_config + fi + + cd .. + done + +Note: CTI connections are SOC specific and hence the above script is +added just for reference. + +4. Choose reserved buffer mode for ETR buffer + #echo "resrv" > /sys/bus/coresight/devices/tmc_etr0/buf_mode_preferred + +5. Enable stop on flush trigger configuration + #echo 1 > /sys/bus/coresight/devices/tmc_etr0/stop_on_flush + +6. Start Coresight tracing on cores 1 and 2 using sysfs interface + +7. Run some application on core 1 + #taskset -c 1 dd if=3D/dev/urandom of=3D/dev/null & + +8. Invoke kernel panic on core 2 + #echo 1 > /proc/sys/kernel/panic + #taskset -c 2 echo c > /proc/sysrq-trigger + +9. From rebooted kernel or crashdump kernel, read crashdata + + #dd if=3D/dev/crash_tmc_etr0 of=3D/trace/cstrace.bin + +10. Run opencsd decoder tools/scripts to generate the instruction trace. + +Sample instruction trace dump +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Core1 dump:: + + A etm4_enable_hw: ffff800008ae1dd4 + CONTEXT EL2 etm4_enable_hw: ffff800008ae1dd4 + I etm4_enable_hw: ffff800008ae1dd4: + d503201f nop + I etm4_enable_hw: ffff800008ae1dd8: + d503201f nop + I etm4_enable_hw: ffff800008ae1ddc: + d503201f nop + I etm4_enable_hw: ffff800008ae1de0: + d503201f nop + I etm4_enable_hw: ffff800008ae1de4: + d503201f nop + I etm4_enable_hw: ffff800008ae1de8: + d503233f paciasp + I etm4_enable_hw: ffff800008ae1dec: + a9be7bfd stp x29, x30, [sp, #-32]! + I etm4_enable_hw: ffff800008ae1df0: + 910003fd mov x29, sp + I etm4_enable_hw: ffff800008ae1df4: + a90153f3 stp x19, x20, [sp, #16] + I etm4_enable_hw: ffff800008ae1df8: + 2a0003f4 mov w20, w0 + I etm4_enable_hw: ffff800008ae1dfc: + 900085b3 adrp x19, ffff800009b95000 + I etm4_enable_hw: ffff800008ae1e00: + 910f4273 add x19, x19, #0x3d0 + I etm4_enable_hw: ffff800008ae1e04: + f8747a60 ldr x0, [x19, x20, lsl #3] + E etm4_enable_hw: ffff800008ae1e08: + b4000140 cbz x0, ffff800008ae1e30 + I 149.039572921 etm4_enable_hw: ffff800008ae1e30: + a94153f3 ldp x19, x20, [sp, #16] + I 149.039572921 etm4_enable_hw: ffff800008ae1e34: + 52800000 mov w0, #0x0 // #0 + I 149.039572921 etm4_enable_hw: ffff800008ae1e38: + a8c27bfd ldp x29, x30, [sp], #32 + + ..snip + + 149.052324811 chacha_block_generic: ffff800008642d80: + 9100a3e0 add x0, + I 149.052324811 chacha_block_generic: ffff800008642d84: + b86178a2 ldr w2, [x5, x1, lsl #2] + I 149.052324811 chacha_block_generic: ffff800008642d88: + 8b010803 add x3, x0, x1, lsl #2 + I 149.052324811 chacha_block_generic: ffff800008642d8c: + b85fc063 ldur w3, [x3, #-4] + I 149.052324811 chacha_block_generic: ffff800008642d90: + 0b030042 add w2, w2, w3 + I 149.052324811 chacha_block_generic: ffff800008642d94: + b8217882 str w2, [x4, x1, lsl #2] + I 149.052324811 chacha_block_generic: ffff800008642d98: + 91000421 add x1, x1, #0x1 + I 149.052324811 chacha_block_generic: ffff800008642d9c: + f100443f cmp x1, #0x11 + + +Core 2 dump:: + + A etm4_enable_hw: ffff800008ae1dd4 + CONTEXT EL2 etm4_enable_hw: ffff800008ae1dd4 + I etm4_enable_hw: ffff800008ae1dd4: + d503201f nop + I etm4_enable_hw: ffff800008ae1dd8: + d503201f nop + I etm4_enable_hw: ffff800008ae1ddc: + d503201f nop + I etm4_enable_hw: ffff800008ae1de0: + d503201f nop + I etm4_enable_hw: ffff800008ae1de4: + d503201f nop + I etm4_enable_hw: ffff800008ae1de8: + d503233f paciasp + I etm4_enable_hw: ffff800008ae1dec: + a9be7bfd stp x29, x30, [sp, #-32]! + I etm4_enable_hw: ffff800008ae1df0: + 910003fd mov x29, sp + I etm4_enable_hw: ffff800008ae1df4: + a90153f3 stp x19, x20, [sp, #16] + I etm4_enable_hw: ffff800008ae1df8: + 2a0003f4 mov w20, w0 + I etm4_enable_hw: ffff800008ae1dfc: + 900085b3 adrp x19, ffff800009b95000 + I etm4_enable_hw: ffff800008ae1e00: + 910f4273 add x19, x19, #0x3d0 + I etm4_enable_hw: ffff800008ae1e04: + f8747a60 ldr x0, [x19, x20, lsl #3] + E etm4_enable_hw: ffff800008ae1e08: + b4000140 cbz x0, ffff800008ae1e30 + I 149.046243445 etm4_enable_hw: ffff800008ae1e30: + a94153f3 ldp x19, x20, [sp, #16] + I 149.046243445 etm4_enable_hw: ffff800008ae1e34: + 52800000 mov w0, #0x0 // #0 + I 149.046243445 etm4_enable_hw: ffff800008ae1e38: + a8c27bfd ldp x29, x30, [sp], #32 + I 149.046243445 etm4_enable_hw: ffff800008ae1e3c: + d50323bf autiasp + E 149.046243445 etm4_enable_hw: ffff800008ae1e40: + d65f03c0 ret + A ete_sysreg_write: ffff800008adfa18 + + ..snip + + I 149.05422547 panic: ffff800008096300: + a90363f7 stp x23, x24, [sp, #48] + I 149.05422547 panic: ffff800008096304: + 6b00003f cmp w1, w0 + I 149.05422547 panic: ffff800008096308: + 3a411804 ccmn w0, #0x1, #0x4, ne // ne =3D any + N 149.05422547 panic: ffff80000809630c: + 540001e0 b.eq ffff800008096348 // b.none + I 149.05422547 panic: ffff800008096310: + f90023f9 str x25, [sp, #64] + E 149.05422547 panic: ffff800008096314: + 97fe44ef bl ffff8000080276d0 + A panic: ffff80000809634c + I 149.05422547 panic: ffff80000809634c: + 910102d5 add x21, x22, #0x40 + I 149.05422547 panic: ffff800008096350: + 52800020 mov w0, #0x1 // #1 + E 149.05422547 panic: ffff800008096354: + 94166b8b bl ffff800008631180 + N 149.054225518 bust_spinlocks: ffff800008631180: + 340000c0 cbz w0, ffff800008631198 + I 149.054225518 bust_spinlocks: ffff800008631184: + f000a321 adrp x1, ffff800009a98000 + I 149.054225518 bust_spinlocks: ffff800008631188: + b9405c20 ldr w0, [x1, #92] + I 149.054225518 bust_spinlocks: ffff80000863118c: + 11000400 add w0, w0, #0x1 + I 149.054225518 bust_spinlocks: ffff800008631190: + b9005c20 str w0, [x1, #92] + E 149.054225518 bust_spinlocks: ffff800008631194: + d65f03c0 ret + A panic: ffff800008096358 + +Perf based testing +------------------ + +Starting perf session +~~~~~~~~~~~~~~~~~~~~~ +ETF: +perf record -e cs_etm/panicstop,@tmc_etf1/ -C 1 +perf record -e cs_etm/panicstop,@tmc_etf2/ -C 2 + +ETR: +perf record -e cs_etm/panicstop,@tmc_etr0/ -C 1,2 + +Reading trace data after panic +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +Same sysfs based method explained above can be used to retrieve and +decode the trace data after the reboot on kernel panic. --=20 2.34.1