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charset="utf-8" Add device tree node for the DisplayPort controller and eDP PHY found on the Qualcomm SA8775P SoC. Signed-off-by: Soutrik Mukhopadhyay --- This patch depends on following series: https://lore.kernel.org/all/20240816-sa8775p-mm-v3-v1-0-77d53c3c0cef@quicin= c.com/ https://lore.kernel.org/all/20240912071437.1708969-1-quic_mahap@quicinc.com/ https://lore.kernel.org/all/20240913103755.7290-1-quic_mukhopad@quicinc.com/ =20 --- arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi | 23 +++++ arch/arm64/boot/dts/qcom/sa8775p.dtsi | 114 ++++++++++++++++++++- 2 files changed, 136 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi b/arch/arm64/boot/d= ts/qcom/sa8775p-ride.dtsi index 0c1b21def4b6..728b4cda8353 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi @@ -421,6 +421,23 @@ status =3D "okay"; }; =20 +&mdss0 { + status =3D "okay"; +}; + +&mdss0_dp0 { + status =3D "okay"; +}; + +&mdss0_dp0_out { + data-lanes =3D <0 1 2 3>; + link-frequencies =3D /bits/ 64 <1620000000 2700000000 5400000000 81000000= 00>; +}; + +&mdss0_edp_phy0 { + status =3D "okay"; +}; + &pmm8654au_0_gpios { gpio-line-names =3D "DS_EN", "POFF_COMPLETE", @@ -527,6 +544,12 @@ }; =20 &tlmm { + dp_hot_plug_det: dp-hot-plug-det-state { + pins =3D "gpio101"; + function =3D "edp0_hot"; + bias-disable; + }; + ethernet0_default: ethernet0-default-state { ethernet0_mdc: ethernet0-mdc-pins { pins =3D "gpio8"; diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qc= om/sa8775p.dtsi index 7747965e7e46..a04150c29565 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -3339,6 +3339,18 @@ interrupt-parent =3D <&mdss0>; interrupts =3D <0>; =20 + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + dpu_intf0_out: endpoint { + remote-endpoint =3D <&mdss0_dp0_in>; + }; + }; + }; + mdss0_mdp_opp_table: opp-table { compatible =3D "operating-points-v2"; =20 @@ -3363,6 +3375,106 @@ }; }; }; + + mdss0_edp_phy0: phy@aec2a00 { + compatible =3D "qcom,sa8775p-edp-phy"; + + reg =3D <0x0 0xaec2a00 0x0 0x200>, + <0x0 0xaec2200 0x0 0xd0>, + <0x0 0xaec2600 0x0 0xd0>, + <0x0 0xaec2000 0x0 0x1c8>; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_EDP_REF_CLKREF_EN>; + clock-names =3D "aux", + "cfg_ahb"; + + vdda-phy-supply =3D <&vreg_l1c>; + vdda-pll-supply =3D <&vreg_l4a>; + #clock-cells =3D <1>; + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + + mdss0_dp0: displayport-controller@af54000 { + compatible =3D "qcom,sa8775p-dp"; + + pinctrl-0 =3D <&dp_hot_plug_det>; + pinctrl-names =3D "default"; + + reg =3D <0x0 0xaf54000 0x0 0x104>, + <0x0 0xaf54200 0x0 0x0c0>, + <0x0 0xaf55000 0x0 0x770>, + <0x0 0xaf56000 0x0 0x09c>; + + interrupt-parent =3D <&mdss0>; + interrupts =3D <12>; + + clocks =3D <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; + clock-names =3D "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + assigned-clocks =3D <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; + assigned-clock-parents =3D <&mdss0_edp_phy0 0>, <&mdss0_edp_phy0 1>; + phys =3D <&mdss0_edp_phy0>; + phy-names =3D "dp"; + + operating-points-v2 =3D <&dp_opp_table>; + power-domains =3D <&rpmhpd SA8775P_MMCX>; + + #sound-dai-cells =3D <0>; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + mdss0_dp0_in: endpoint { + remote-endpoint =3D <&dpu_intf0_out>; + }; + }; + + port@1 { + reg =3D <1>; + mdss0_dp0_out: endpoint { }; + }; + }; + + dp_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-160000000 { + opp-hz =3D /bits/ 64 <160000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz =3D /bits/ 64 <270000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz =3D /bits/ 64 <540000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz =3D /bits/ 64 <810000000>; + required-opps =3D <&rpmhpd_opp_nom>; + }; + }; + }; }; =20 dispcc0: clock-controller@af00000 { @@ -3372,7 +3484,7 @@ <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, - <0>, <0>, <0>, <0>, + <&mdss0_edp_phy0 0>, <&mdss0_edp_phy0 1>, <0>, <0>, <0>, <0>, <0>, <0>; power-domains =3D <&rpmhpd SA8775P_MMCX>; #clock-cells =3D <1>; --=20 2.17.1