From nobody Fri Nov 29 18:24:45 2024 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.3]) by smtp.subspace.kernel.org (Postfix) with ESMTP id D32CB4120B; Mon, 16 Sep 2024 06:45:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.3 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726469145; cv=none; b=gOztd+T559jPv6UkNacN1mdLsvl3dd4bUNSaJIX6gytSj7gMwJn4zUhUyXOFQpOmP5OnOLlmt25+zMmg7pfLgsqhSP/YZbQhRtWMfuXVzCPE79cYj8dJYM1arSu0FIBnF0f+1zQMMnTbIhuOzSAy7ZrJ73r8fS5jsrvYEg1pvb8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726469145; c=relaxed/simple; bh=jAwSw4LEIfXT39XmNvQkkX3/1clNMqBMeMdEHqSLLuc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=XwLrVYJQO9ckb7UN33sI/4EAf9kCDL2BvWHsQmSYAMhqoo3C5e+OHO+1QMkhzkSaZD+av2OprpNsCOMtRu51rRiRYN9gkdg41XDvGUvFWRd0XvPin02pALDwGxXDH/Wj4hQdzLruQstSriXr0vff798gafxwGGqPJ5ZJWl27lis= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=ELcD2D9i; arc=none smtp.client-ip=117.135.210.3 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="ELcD2D9i" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:Subject:Date:Message-ID:MIME-Version; bh=H5SO/ a1hfbyVpeTzy2AAy5aKvwSqfgsGs2lOMb5bsec=; b=ELcD2D9iTL4cSN5SxjBh6 BXgHtcjXd3q1Snt6RNk4YaZOuu2naSd+v2aGVrwlnyZTvk4kirg61qdU9m2/J6bd WHwF+zo+k9Z/u6AEiRrnVJRe/mY9XlCJVCu5W9h85pwJhnwxN7fme/EkWBGbZUcX 4hclGhEXcFJ5oq7C1CoeVY= Received: from jean.localdomain (unknown [27.18.168.209]) by gzga-smtp-mta-g3-3 (Coremail) with SMTP id _____wDXX36b0+dmVfTnDg--.31141S2; Mon, 16 Sep 2024 14:43:39 +0800 (CST) From: Ze Huang <18771902331@163.com> To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Ze Huang <18771902331@163.com>, Yangyu Chen Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [RESEND PATCH 1/3] dt-bindings: pinctrl: Add support for canaan,k230 SoC Date: Mon, 16 Sep 2024 14:42:23 +0800 Message-ID: <20240916064225.316863-1-18771902331@163.com> X-Mailer: git-send-email 2.46.1 In-Reply-To: <20240916063021.311721-1-18771902331@163.com> References: <20240916063021.311721-1-18771902331@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wDXX36b0+dmVfTnDg--.31141S2 X-Coremail-Antispam: 1Uf129KBjvJXoWxuF17Cr1xuw1rZr4rAryfXrb_yoWrJFyxpF ZxKa98KF1rWF47K3yfta18uF13Xa1kArsagw1Utry7tw45WF18Kr1akr4IvF4DWFn7J3Wa qFWIgry7KF47Ar7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0piL0ePUUUUU= X-CM-SenderInfo: zpryllqrzqjjitr6il2tof0z/1tbiJwBcomXAn1YeJAAAsP Content-Type: text/plain; charset="utf-8" Add device tree binding details for Canaan K230 pinctrl device. Signed-off-by: Ze Huang <18771902331@163.com> --- .../bindings/pinctrl/canaan,k230-pinctrl.yaml | 128 ++++++++++++++++++ 1 file changed, 128 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/canaan,k230-p= inctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/canaan,k230-pinctrl.= yaml b/Documentation/devicetree/bindings/pinctrl/canaan,k230-pinctrl.yaml new file mode 100644 index 000000000000..979c5bd71e3d --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/canaan,k230-pinctrl.yaml @@ -0,0 +1,128 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/canaan,k230-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Canaan Kendryte K230 Pin Controller + +maintainers: + - Ze Huang <18771902331@163.com> + +description: + The Canaan Kendryte K230 platform includes 64 IO pins, each capable of + multiplexing up to 5 different functions. Pin function configuration is + performed on a per-pin basis. + +properties: + compatible: + const: canaan,k230-pinctrl + + reg: + maxItems: 1 + +patternProperties: + '-pins$': + type: object + additionalProperties: false + description: + A pinctrl node should contain at least one subnode representing the + pinctrl groups available on the machine. + + patternProperties: + '-cfg$': + type: object + $ref: /schemas/pinctrl/pincfg-node.yaml + additionalProperties: false + description: + Each subnode will list the pins it needs, and how they should + be configured, with regard to muxer configuration, bias, input + enable/disable, input schmitt trigger, slew-rate enable/disable, + slew-rate, drive strength. + + properties: + pinmux: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + The list of GPIOs and their mux settings that properties in + the node apply to. This should be set with the macro + 'K230_PINMUX(pin, mode)' + + bias-disable: true + + bias-pull-up: true + + bias-pull-down: true + + drive-strength: + minimum: 0 + maximum: 15 + + input-enable: true + + output-enable: true + + input-schmitt-enable: true + + slew-rate: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + slew rate control enable + 0: disable + 1: enable + + enum: [0, 1] + + power-source: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Specifies the power source voltage for the IO bank that the + pin belongs to. Each bank of IO pins operate at a specific, + fixed voltage levels. Incorrect voltage configuration can + damage the chip. The defined constants represent the + possible voltage configurations: + + - K230_MSC_3V3 (value 0): 3.3V power supply + - K230_MSC_1V8 (value 1): 1.8V power supply + + The following banks have the corresponding voltage + configurations: + + - bank IO0 to IO1: Fixed at 1.8V + - bank IO2 to IO13: Fixed at 1.8V + - bank IO14 to IO25: Fixed at 1.8V + - bank IO26 to IO37: Fixed at 1.8V + - bank IO38 to IO49: Fixed at 1.8V + - bank IO50 to IO61: Fixed at 3.3V + - bank IO62 to IO63: Fixed at 1.8V + + enum: [0, 1] + + required: + - pinmux + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + pinctrl: pinctrl@91105000 { + compatible =3D "canaan,k230-pinctrl"; + reg =3D <0x91105000 0x100>; + + uart2_pins: uart2-pins { + uart2-pins-cfg { + pinmux =3D <0x503>, /* uart2 txd */ + <0x603>; /* uart2 rxd */ + slew-rate =3D <0>; + drive-strength =3D <4>; + power-source =3D <1>; + input-enable; + output-enable; + bias-disable; + }; + }; + }; --=20 2.46.1 From nobody Fri Nov 29 18:24:45 2024 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.4]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 23D0613B7A1; Mon, 16 Sep 2024 06:49:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726469362; cv=none; b=GvTJxz7GZtTNwp69KFy7oz4SdIleLaCf20B2plTgfBQWMdCSkkWVwSazMiqybp4+eHULJTw7RY7iC2nMD/PBCFdRl4ixUt1VA1aHiiwZESGzn14D6/9K3sDh8wAU8PX8TQFhfv3QaCVXh1Asay4vKzfk4NgnE0+x4Xzw2hVOJHo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726469362; c=relaxed/simple; bh=CNPLj7xqLXDAoRrH5uAwIA3pxBmybpZWxXRRxQRmY74=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=oac9t8Cyfsogl7c9fqhmlOzaFHzoLCVXR/xBNHfTg5t8uysgAtfimENJhKfzIkY4f3xCczTLVcl0D04RyGNdcnONzFwOb7Yj/nc1zf8JeacMqbhrfMHBt4K3ylmcv9gEd0VTbmy3aT+KePfDBkUnipLQ73DGWWgcjmZoEZeqYVc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=jZlqnKVB; arc=none smtp.client-ip=117.135.210.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="jZlqnKVB" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:Subject:Date:Message-ID:MIME-Version; bh=SEvZ4 zp44SBdwYbTmPTqsE/k5nDy7NKgWRHDGc1Mznc=; b=jZlqnKVBP2XNuPSydK4SV WCxoHY3yxAJs0xRy4GkfFiQ8+0WnpcHRQNDI499pm2dZLmDhwZjMR957Zg5xKNJD Uem+D/0BjZLIvEvfKvjcM2gTFfZ/0EhLpZ1SGdvsRFimZ7zVyptqVoM1itNOCTHp wVLQR5l4Y2P7F3fdfvAh6E= Received: from jean.localdomain (unknown [27.18.168.209]) by gzga-smtp-mta-g2-4 (Coremail) with SMTP id _____wDHD2du1OdmyQfeBg--.30056S2; Mon, 16 Sep 2024 14:47:10 +0800 (CST) From: Ze Huang <18771902331@163.com> To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Ze Huang <18771902331@163.com>, Yangyu Chen Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [RESEND PATCH 2/3] pinctrl: canaan: Add support for k230 SoC Date: Mon, 16 Sep 2024 14:47:04 +0800 Message-ID: <20240916064706.318793-1-18771902331@163.com> X-Mailer: git-send-email 2.46.1 In-Reply-To: <20240916063021.311721-1-18771902331@163.com> References: <20240916063021.311721-1-18771902331@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wDHD2du1OdmyQfeBg--.30056S2 X-Coremail-Antispam: 1Uf129KBjvAXoWfCw1kCr43KrW7Xw13CF4Durg_yoW8ur1kZo WI9rnrXw1rJr1xWrZ8G395KF13Z3yjkryDC3Z8Z3s8K348Zr15Kr9Fq3yfKFyYqr4rXrW7 J3s3ZrW7Aaykt3Z8n29KB7ZKAUJUUUU8529EdanIXcx71UUUUU7v73VFW2AGmfu7bjvjm3 AaLaJ3UbIYCTnIWIevJa73UjIFyTuYvjTRdOzsUUUUU X-CM-SenderInfo: zpryllqrzqjjitr6il2tof0z/1tbiNwBcomXAnRlTLAABsW Content-Type: text/plain; charset="utf-8" Configuration of the K230 is similar to that of the K210. However, in K210, the 256 functions for each pin are shared, whereas in K230, multiplex functions are different for every pin. Signed-off-by: Ze Huang <18771902331@163.com> --- drivers/pinctrl/Kconfig | 10 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-k230.c | 674 +++++++++++++++++++++++++++++++++ 3 files changed, 685 insertions(+) create mode 100644 drivers/pinctrl/pinctrl-k230.c diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 1be05efccc29..ff85dd8757fe 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -246,6 +246,16 @@ config PINCTRL_K210 Add support for the Canaan Kendryte K210 RISC-V SOC Field Programmable IO Array (FPIOA) controller. =20 +config PINCTRL_K230 + bool "Pinctrl driver for the Canaan Kendryte K230 SoC" + depends on OF + select GENERIC_PINCTRL_GROUPS + select GENERIC_PINMUX_FUNCTIONS + select GENERIC_PINCONF + select REGMAP_MMIO + help + Add support for the Canaan Kendryte K230 RISC-V SOC pin controller. + config PINCTRL_KEEMBAY tristate "Pinctrl driver for Intel Keem Bay SoC" depends on ARCH_KEEMBAY || (ARM64 && COMPILE_TEST) diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 2152539b53d5..66e7a04ecfa4 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -26,6 +26,7 @@ obj-$(CONFIG_PINCTRL_EQUILIBRIUM) +=3D pinctrl-equilibr= ium.o obj-$(CONFIG_PINCTRL_GEMINI) +=3D pinctrl-gemini.o obj-$(CONFIG_PINCTRL_INGENIC) +=3D pinctrl-ingenic.o obj-$(CONFIG_PINCTRL_K210) +=3D pinctrl-k210.o +obj-$(CONFIG_PINCTRL_K230) +=3D pinctrl-k230.o obj-$(CONFIG_PINCTRL_KEEMBAY) +=3D pinctrl-keembay.o obj-$(CONFIG_PINCTRL_LANTIQ) +=3D pinctrl-lantiq.o obj-$(CONFIG_PINCTRL_FALCON) +=3D pinctrl-falcon.o diff --git a/drivers/pinctrl/pinctrl-k230.c b/drivers/pinctrl/pinctrl-k230.c new file mode 100644 index 000000000000..a935f1f55e66 --- /dev/null +++ b/drivers/pinctrl/pinctrl-k230.c @@ -0,0 +1,674 @@ +// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +/* + * Copyright (C) 2024 Canaan Bright Sight Co. Ltd + * Copyright (C) 2024 Ze Huang <18771902331@163.com> + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "core.h" +#include "pinconf.h" + +#define K230_NPINS 64 + +#define K230_SHIFT_ST (0) +#define K230_SHIFT_DS (1) +#define K230_SHIFT_BIAS (5) +#define K230_SHIFT_PD (5) +#define K230_SHIFT_PU (6) +#define K230_SHIFT_OE (7) +#define K230_SHIFT_IE (8) +#define K230_SHIFT_MSC (9) +#define K230_SHIFT_SL (10) +#define K230_SHIFT_SEL (11) + +#define K230_PC_ST BIT(0) +#define K230_PC_DS GENMASK(4, 1) +#define K230_PC_PD BIT(5) +#define K230_PC_PU BIT(6) +#define K230_PC_BIAS GENMASK(6, 5) +#define K230_PC_OE BIT(7) +#define K230_PC_IE BIT(8) +#define K230_PC_MSC BIT(9) +#define K230_PC_SL BIT(10) +#define K230_PC_SEL GENMASK(13, 11) + +struct k230_pin_conf { + unsigned int func; + unsigned long *configs; + unsigned int nconfigs; +}; + +struct k230_pin_group { + const char *name; + unsigned int *pins; + unsigned int num_pins; + + struct k230_pin_conf *data; +}; + +struct k230_pmx_func { + const char *name; + const char **groups; + unsigned int *group_idx; + unsigned int ngroups; +}; + +struct k230_pinctrl { + struct pinctrl_desc pctl; + struct pinctrl_dev *pctl_dev; + struct regmap *regmap_base; + void __iomem *base; + struct k230_pin_group *groups; + unsigned int ngroups; + struct k230_pmx_func *functions; + unsigned int nfunctions; +}; + +static struct regmap_config k230_regmap_config =3D { + .reg_bits =3D 32, + .val_bits =3D 32, + .max_register =3D 0x100, + .reg_stride =3D 4, +}; + +static int k230_get_groups_count(struct pinctrl_dev *pctldev) +{ + struct k230_pinctrl *info =3D pinctrl_dev_get_drvdata(pctldev); + + return info->ngroups; +} + +static const char *k230_get_group_name(struct pinctrl_dev *pctldev, + unsigned int selector) +{ + struct k230_pinctrl *info =3D pinctrl_dev_get_drvdata(pctldev); + + return info->groups[selector].name; +} + +static int k230_get_group_pins(struct pinctrl_dev *pctldev, + unsigned int selector, + const unsigned int **pins, + unsigned int *num_pins) +{ + struct k230_pinctrl *info =3D pinctrl_dev_get_drvdata(pctldev); + + if (selector >=3D info->ngroups) + return -EINVAL; + + *pins =3D info->groups[selector].pins; + *num_pins =3D info->groups[selector].num_pins; + + return 0; +} + +static inline const struct k230_pmx_func *k230_name_to_funtion( + const struct k230_pinctrl *info, const char *name) +{ + unsigned int i; + + for (i =3D 0; i < info->nfunctions; i++) { + if (!strcmp(info->functions[i].name, name)) + return &info->functions[i]; + } + + return NULL; +} + +static int k230_pinctrl_parse_groups(struct device_node *np, + struct k230_pin_group *grp, + struct k230_pinctrl *info, + unsigned int index) +{ + struct device *dev =3D info->pctl_dev->dev; + const __be32 *list; + int size, i, ret; + + grp->name =3D np->name; + + list =3D of_get_property(np, "pinmux", &size); + size /=3D sizeof(*list); + + grp->num_pins =3D size; + grp->pins =3D devm_kcalloc(dev, grp->num_pins, sizeof(*grp->pins), + GFP_KERNEL); + grp->data =3D devm_kcalloc(dev, grp->num_pins, sizeof(*grp->data), + GFP_KERNEL); + if (!grp->pins || !grp->data) + return -ENOMEM; + + for (i =3D 0; i < size; i++) { + unsigned int mux_data =3D be32_to_cpu(*list++); + + grp->pins[i] =3D (mux_data >> 8); + grp->data[i].func =3D (mux_data & 0xff); + + ret =3D pinconf_generic_parse_dt_config(np, NULL, + &grp->data[i].configs, + &grp->data[i].nconfigs); + if (ret) + return ret; + } + of_node_put(np); + + return 0; +} + +static void k230_pinctrl_child_count(struct k230_pinctrl *info, + struct device_node *np) +{ + struct device_node *child; + + for_each_child_of_node(np, child) { + info->nfunctions++; + info->ngroups +=3D of_get_child_count(child); + } +} + +static int k230_pinctrl_parse_functions(struct device_node *np, + struct k230_pinctrl *info, + unsigned int index) +{ + struct device *dev =3D info->pctl_dev->dev; + struct k230_pmx_func *func; + struct k230_pin_group *grp; + struct device_node *child; + static unsigned int idx, i; + int ret; + + func =3D &info->functions[index]; + + func->name =3D np->name; + func->ngroups =3D of_get_child_count(np); + if (func->ngroups <=3D 0) + return 0; + + func->groups =3D devm_kcalloc(dev, func->ngroups, + sizeof(*func->groups), GFP_KERNEL); + func->group_idx =3D devm_kcalloc(dev, func->ngroups, + sizeof(*func->group_idx), GFP_KERNEL); + if (!func->groups || !func->group_idx) + return -ENOMEM; + + i =3D 0; + + for_each_child_of_node(np, child) { + func->groups[i] =3D child->name; + func->group_idx[i] =3D idx; + grp =3D &info->groups[idx]; + idx++; + ret =3D k230_pinctrl_parse_groups(child, grp, info, i++); + if (ret) { + of_node_put(child); + return ret; + } + } + + return 0; +} + +static int k230_pinctrl_parse_dt(struct platform_device *pdev, + struct k230_pinctrl *info) +{ + struct device *dev =3D &pdev->dev; + struct device_node *np =3D dev->of_node; + struct device_node *child; + unsigned int i; + int ret; + + k230_pinctrl_child_count(info, np); + + info->functions =3D devm_kcalloc(dev, info->nfunctions, + sizeof(*info->functions), GFP_KERNEL); + info->groups =3D devm_kcalloc(dev, info->ngroups, + sizeof(*info->groups), GFP_KERNEL); + if (!info->functions || !info->groups) + return -ENOMEM; + + i =3D 0; + + for_each_child_of_node(np, child) { + ret =3D k230_pinctrl_parse_functions(child, info, i++); + if (ret) { + dev_err(dev, "failed to parse function\n"); + of_node_put(child); + return ret; + } + } + + return 0; +} + +static struct pinctrl_pin_desc k230_pins[] =3D { + PINCTRL_PIN(0, "IO0"), PINCTRL_PIN(1, "IO1"), PINCTRL_PIN(2, "IO2"), + PINCTRL_PIN(3, "IO3"), PINCTRL_PIN(4, "IO4"), PINCTRL_PIN(5, "IO5"), + PINCTRL_PIN(6, "IO6"), PINCTRL_PIN(7, "IO7"), PINCTRL_PIN(8, "IO8"), + PINCTRL_PIN(9, "IO9"), PINCTRL_PIN(10, "IO10"), PINCTRL_PIN(11, "IO11"), + PINCTRL_PIN(12, "IO12"), PINCTRL_PIN(13, "IO13"), PINCTRL_PIN(14, "IO14"), + PINCTRL_PIN(15, "IO15"), PINCTRL_PIN(16, "IO16"), PINCTRL_PIN(17, "IO17"), + PINCTRL_PIN(18, "IO18"), PINCTRL_PIN(19, "IO19"), PINCTRL_PIN(20, "IO20"), + PINCTRL_PIN(21, "IO21"), PINCTRL_PIN(22, "IO22"), PINCTRL_PIN(23, "IO23"), + PINCTRL_PIN(24, "IO24"), PINCTRL_PIN(25, "IO25"), PINCTRL_PIN(26, "IO26"), + PINCTRL_PIN(27, "IO27"), PINCTRL_PIN(28, "IO28"), PINCTRL_PIN(29, "IO29"), + PINCTRL_PIN(30, "IO30"), PINCTRL_PIN(31, "IO31"), PINCTRL_PIN(32, "IO32"), + PINCTRL_PIN(33, "IO33"), PINCTRL_PIN(34, "IO34"), PINCTRL_PIN(35, "IO35"), + PINCTRL_PIN(36, "IO36"), PINCTRL_PIN(37, "IO37"), PINCTRL_PIN(38, "IO38"), + PINCTRL_PIN(39, "IO39"), PINCTRL_PIN(40, "IO40"), PINCTRL_PIN(41, "IO41"), + PINCTRL_PIN(42, "IO42"), PINCTRL_PIN(43, "IO43"), PINCTRL_PIN(44, "IO44"), + PINCTRL_PIN(45, "IO45"), PINCTRL_PIN(46, "IO46"), PINCTRL_PIN(47, "IO47"), + PINCTRL_PIN(48, "IO48"), PINCTRL_PIN(49, "IO49"), PINCTRL_PIN(50, "IO50"), + PINCTRL_PIN(51, "IO51"), PINCTRL_PIN(52, "IO52"), PINCTRL_PIN(53, "IO53"), + PINCTRL_PIN(54, "IO54"), PINCTRL_PIN(55, "IO55"), PINCTRL_PIN(56, "IO56"), + PINCTRL_PIN(57, "IO57"), PINCTRL_PIN(58, "IO58"), PINCTRL_PIN(59, "IO59"), + PINCTRL_PIN(60, "IO60"), PINCTRL_PIN(61, "IO61"), PINCTRL_PIN(62, "IO62"), + PINCTRL_PIN(63, "IO63") +}; + +static void k230_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *s, unsigned int offset) +{ + struct k230_pinctrl *info =3D pinctrl_dev_get_drvdata(pctldev); + u32 val, mode, bias, drive, input, output, slew, schmitt, power; + struct k230_pin_group *grp =3D k230_pins[offset].drv_data; + static const char * const biasing[] =3D { + "pull none", "pull down", "pull up", "" }; + static const char * const enable[] =3D { + "disable", "enable" }; + static const char * const power_source[] =3D { + "3V3", "1V8" }; + int ret; + + ret =3D regmap_read(info->regmap_base, offset * 4, &val); + if (ret) { + dev_err(info->pctl_dev->dev, + "failed to read offset 0x%x\n", offset * 4); + return; + } + + mode =3D (val & K230_PC_SEL) >> K230_SHIFT_SEL; + drive =3D (val & K230_PC_DS) >> K230_SHIFT_DS; + bias =3D (val & K230_PC_BIAS) >> K230_SHIFT_BIAS; + input =3D (val & K230_PC_IE) >> K230_SHIFT_IE; + output =3D (val & K230_PC_OE) >> K230_SHIFT_OE; + slew =3D (val & K230_PC_SL) >> K230_SHIFT_SL; + schmitt =3D (val & K230_PC_ST) >> K230_SHIFT_ST; + power =3D (val & K230_PC_MSC) >> K230_SHIFT_MSC; + + seq_printf(s, "%s - strength %d - %s - %s - slewrate %s - schmitt %s - %s= ", + grp ? grp->name : "unknown", + drive, + biasing[bias], + input ? "input" : "output", + enable[slew], + enable[schmitt], + power_source[power]); +} + +static int k230_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np_config, + struct pinctrl_map **map, + unsigned int *num_maps) +{ + struct k230_pinctrl *info =3D pinctrl_dev_get_drvdata(pctldev); + struct device *dev =3D info->pctl_dev->dev; + const struct k230_pmx_func *func; + const struct k230_pin_group *grp; + struct pinctrl_map *new_map; + int map_num, i, j, idx; + unsigned int grp_id; + + func =3D k230_name_to_funtion(info, np_config->name); + if (!func) { + dev_err(dev, "function %s not found\n", np_config->name); + return -EINVAL; + } + + map_num =3D 0; + for (i =3D 0; i < func->ngroups; ++i) { + grp_id =3D func->group_idx[i]; + /* npins of config map plus a mux map */ + map_num +=3D info->groups[grp_id].num_pins + 1; + } + + new_map =3D kcalloc(map_num, sizeof(*new_map), GFP_KERNEL); + if (!new_map) + return -ENOMEM; + *map =3D new_map; + *num_maps =3D map_num; + + idx =3D 0; + for (i =3D 0; i < func->ngroups; ++i) { + grp_id =3D func->group_idx[i]; + grp =3D &info->groups[grp_id]; + new_map[idx].type =3D PIN_MAP_TYPE_MUX_GROUP; + new_map[idx].data.mux.group =3D grp->name; + new_map[idx].data.mux.function =3D np_config->name; + idx++; + + for (j =3D 0; j < grp->num_pins; ++j) { + new_map[idx].type =3D PIN_MAP_TYPE_CONFIGS_PIN; + new_map[idx].data.configs.group_or_pin =3D + pin_get_name(pctldev, grp->pins[j]); + new_map[idx].data.configs.configs =3D + grp->data[j].configs; + new_map[idx].data.configs.num_configs =3D + grp->data[j].nconfigs; + idx++; + } + } + + return 0; +} + +static void k230_dt_free_map(struct pinctrl_dev *pctldev, + struct pinctrl_map *map, unsigned int num_maps) +{ + kfree(map); +} + +static const struct pinctrl_ops k230_pctrl_ops =3D { + .get_groups_count =3D k230_get_groups_count, + .get_group_name =3D k230_get_group_name, + .get_group_pins =3D k230_get_group_pins, + .pin_dbg_show =3D k230_pinctrl_pin_dbg_show, + .dt_node_to_map =3D k230_dt_node_to_map, + .dt_free_map =3D k230_dt_free_map, +}; + +static int k230_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *config) +{ + struct k230_pinctrl *info =3D pinctrl_dev_get_drvdata(pctldev); + enum pin_config_param param =3D pinconf_to_config_param(*config); + unsigned int val, arg; + int ret; + + ret =3D regmap_read(info->regmap_base, pin * 4, &val); + if (ret) { + dev_err(info->pctl_dev->dev, + "failed to read offset 0x%x\n", pin * 4); + return ret; + } + + switch (param) { + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + arg =3D (val & K230_PC_ST) ? 1 : 0; + break; + case PIN_CONFIG_DRIVE_STRENGTH: + arg =3D (val & K230_PC_DS) >> K230_SHIFT_DS; + break; + case PIN_CONFIG_BIAS_DISABLE: + arg =3D (val & K230_PC_BIAS) ? 0 : 1; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + arg =3D (val & K230_PC_PD) ? 1 : 0; + break; + case PIN_CONFIG_BIAS_PULL_UP: + arg =3D (val & K230_PC_PU) ? 1 : 0; + break; + case PIN_CONFIG_OUTPUT_ENABLE: + arg =3D (val & K230_PC_OE) ? 1 : 0; + break; + case PIN_CONFIG_INPUT_ENABLE: + arg =3D (val & K230_PC_IE) ? 1 : 0; + break; + case PIN_CONFIG_POWER_SOURCE: + arg =3D (val & K230_PC_MSC) ? 1 : 0; + break; + case PIN_CONFIG_SLEW_RATE: + arg =3D (val & K230_PC_SL) ? 1 : 0; + break; + default: + return -EINVAL; + } + + *config =3D pinconf_to_config_packed(param, arg); + + return 0; +} + +static int k230_pinconf_set_param(struct pinctrl_dev *pctldev, unsigned in= t pin, + enum pin_config_param param, unsigned int arg) +{ + struct k230_pinctrl *info =3D pinctrl_dev_get_drvdata(pctldev); + struct device *dev =3D info->pctl_dev->dev; + unsigned int val; + int ret; + + ret =3D regmap_read(info->regmap_base, pin * 4, &val); + if (ret) { + dev_err(dev, "failed to read offset 0x%x\n", pin * 4); + return ret; + } + + switch (param) { + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + if (arg) + val |=3D K230_PC_ST; + else + val &=3D ~K230_PC_ST; + break; + case PIN_CONFIG_DRIVE_STRENGTH: + val &=3D ~K230_PC_DS; + val |=3D (arg << K230_SHIFT_DS) & K230_PC_DS; + break; + case PIN_CONFIG_BIAS_DISABLE: + val &=3D ~K230_PC_BIAS; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + if (!arg) + return -EINVAL; + val |=3D K230_PC_PD; + break; + case PIN_CONFIG_BIAS_PULL_UP: + if (!arg) + return -EINVAL; + val |=3D K230_PC_PU; + break; + case PIN_CONFIG_OUTPUT_ENABLE: + if (!arg) + return -EINVAL; + val |=3D K230_PC_OE; + break; + case PIN_CONFIG_INPUT_ENABLE: + if (!arg) + return -EINVAL; + val |=3D K230_PC_IE; + break; + case PIN_CONFIG_POWER_SOURCE: + if (arg) + val |=3D K230_PC_MSC; + else + val &=3D ~K230_PC_MSC; + break; + case PIN_CONFIG_SLEW_RATE: + if (arg) + val |=3D K230_PC_SL; + else + val &=3D ~K230_PC_SL; + break; + default: + return -EINVAL; + } + + ret =3D regmap_write(info->regmap_base, pin * 4, val); + if (ret) { + dev_err(dev, "failed to write offset 0x%x\n", pin * 4); + return ret; + } + + return 0; +} + +static int k230_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *configs, unsigned int num_configs) +{ + enum pin_config_param param; + unsigned int arg, i; + int ret; + + if (WARN_ON(pin >=3D K230_NPINS)) + return -EINVAL; + + for (i =3D 0; i < num_configs; i++) { + param =3D pinconf_to_config_param(configs[i]); + arg =3D pinconf_to_config_argument(configs[i]); + ret =3D k230_pinconf_set_param(pctldev, pin, param, arg); + if (ret) + return ret; + } + + return 0; +} + +static void k230_pconf_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *s, unsigned int pin) +{ + struct k230_pinctrl *info =3D pinctrl_dev_get_drvdata(pctldev); + unsigned int val; + int ret; + + ret =3D regmap_read(info->regmap_base, pin * 4, &val); + if (ret) { + dev_err(info->pctl_dev->dev, "failed to read offset 0x%x\n", pin * 4); + return; + } + + seq_printf(s, " 0x%08x", val); +} + +static const struct pinconf_ops k230_pinconf_ops =3D { + .is_generic =3D true, + .pin_config_get =3D k230_pinconf_get, + .pin_config_set =3D k230_pinconf_set, + .pin_config_dbg_show =3D k230_pconf_dbg_show, +}; + +static int k230_get_functions_count(struct pinctrl_dev *pctldev) +{ + struct k230_pinctrl *info =3D pinctrl_dev_get_drvdata(pctldev); + + return info->nfunctions; +} + +static const char *k230_get_fname(struct pinctrl_dev *pctldev, + unsigned int selector) +{ + struct k230_pinctrl *info =3D pinctrl_dev_get_drvdata(pctldev); + + return info->functions[selector].name; +} + +static int k230_get_groups(struct pinctrl_dev *pctldev, unsigned int selec= tor, + const char * const **groups, unsigned int *num_groups) +{ + struct k230_pinctrl *info =3D pinctrl_dev_get_drvdata(pctldev); + + *groups =3D info->functions[selector].groups; + *num_groups =3D info->functions[selector].ngroups; + + return 0; +} + +static int k230_set_mux(struct pinctrl_dev *pctldev, unsigned int selector, + unsigned int group) +{ + struct k230_pinctrl *info =3D pinctrl_dev_get_drvdata(pctldev); + const struct k230_pin_conf *data =3D info->groups[group].data; + struct k230_pin_group *grp =3D &info->groups[group]; + const unsigned int *pins =3D grp->pins; + struct regmap *regmap; + unsigned int value, mask; + int cnt, reg; + + regmap =3D info->regmap_base; + + for (cnt =3D 0; cnt < grp->num_pins; cnt++) { + reg =3D pins[cnt] * 4; + value =3D data[cnt].func << K230_SHIFT_SEL; + mask =3D K230_PC_SEL; + regmap_update_bits(regmap, reg, mask, value); + k230_pins[pins[cnt]].drv_data =3D grp; + } + + return 0; +} + +static const struct pinmux_ops k230_pmxops =3D { + .get_functions_count =3D k230_get_functions_count, + .get_function_name =3D k230_get_fname, + .get_function_groups =3D k230_get_groups, + .set_mux =3D k230_set_mux, + .strict =3D true, +}; + +static int k230_pinctrl_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct k230_pinctrl *info; + struct pinctrl_desc *pctl; + + info =3D devm_kzalloc(dev, sizeof(*info), GFP_KERNEL); + if (!info) + return -ENOMEM; + + pctl =3D &info->pctl; + + pctl->name =3D "k230-pinctrl"; + pctl->owner =3D THIS_MODULE; + pctl->pins =3D k230_pins; + pctl->npins =3D ARRAY_SIZE(k230_pins); + pctl->pctlops =3D &k230_pctrl_ops; + pctl->pmxops =3D &k230_pmxops; + pctl->confops =3D &k230_pinconf_ops; + + info->base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(info->base)) + return PTR_ERR(info->base); + + k230_regmap_config.name =3D "canaan,pinctrl"; + info->regmap_base =3D devm_regmap_init_mmio(dev, info->base, + &k230_regmap_config); + if (IS_ERR(info->regmap_base)) + return dev_err_probe(dev, PTR_ERR(info->regmap_base), + "failed to init regmap\n"); + + info->pctl_dev =3D devm_pinctrl_register(dev, pctl, info); + if (IS_ERR(info->pctl_dev)) + return dev_err_probe(dev, PTR_ERR(info->pctl_dev), + "devm_pinctrl_register failed\n"); + + k230_pinctrl_parse_dt(pdev, info); + + return 0; +} + +static const struct of_device_id k230_dt_ids[] =3D { + { .compatible =3D "canaan,k230-pinctrl", }, + { /* sintenel */ } +}; +MODULE_DEVICE_TABLE(of, k230_dt_ids); + +static struct platform_driver k230_pinctrl_driver =3D { + .probe =3D k230_pinctrl_probe, + .driver =3D { + .name =3D "k230-pinctrl", + .of_match_table =3D k230_dt_ids, + }, +}; +module_platform_driver(k230_pinctrl_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Ze Huang <18771902331@163.com>"); +MODULE_DESCRIPTION("Canaan K230 pinctrl driver"); --=20 2.46.1 From nobody Fri Nov 29 18:24:45 2024 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.5]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 61EC377F01; Mon, 16 Sep 2024 06:49:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.5 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726469355; cv=none; b=PoJmcEf1VxelKj6Y+VaOU3a2k5pZGavO6WJ/fAejb/bwNdosQEKXdqDQ9fInmebnQLgX3pJ12qynkrzkNiTmD9FPXuepoBwZAhcEfVkF/BpAvNgXHmnKKuGo1yUT4VoaS1fOv2sERm9992Hf80wZDlZcmOJCM5TJIfYp2FALF6c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726469355; c=relaxed/simple; bh=OuCf5XtUpLEJAaXpvuO13tnAB9M9h8/21ajr7rCfodA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=N8W9QrgS3PYQGxuXNjIrKF6qYjJjiwK9oW9bMPOaJUDmTQFKNue1VVcUrT52xr57WqrQZbC4grtXOmCCKuwfrWkKjVqNbpO6GaYXN7rD8y/elEQMBlw5O4X6zegvb67vdiF7keGFc0zcjUTBRjK7gsgLEZggltaPYLLuVL9lmPA= ARC-Authentication-Results: i=1; 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Mon, 16 Sep 2024 14:47:13 +0800 (CST) From: Ze Huang <18771902331@163.com> To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Ze Huang <18771902331@163.com>, Yangyu Chen Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [RESEND PATCH 3/3] riscv: dts: canaan: Add k230's pinctrl node Date: Mon, 16 Sep 2024 14:47:05 +0800 Message-ID: <20240916064706.318793-2-18771902331@163.com> X-Mailer: git-send-email 2.46.1 In-Reply-To: <20240916063021.311721-1-18771902331@163.com> References: <20240916063021.311721-1-18771902331@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wDHD2du1OdmyQfeBg--.30056S3 X-Coremail-Antispam: 1Uf129KBjvJXoWxtw15Ww1DXr4Dtr4fKF1UAwb_yoW3ZF1xpF WS9rn3K34j9rWrK3y0vr1jgF1UWF4q9r1rK3srKry7tw10gFs5K3s5Cr1YqFn8ur1Yk34j g395Zw4Ivrs7JwUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0pRvPfLUUUUU= X-CM-SenderInfo: zpryllqrzqjjitr6il2tof0z/1tbiNwBcomXAnRlTLAADsU Content-Type: text/plain; charset="utf-8" Add pinctrl device, containing default config for uart, pwm, iis, iic and mmc. Signed-off-by: Ze Huang <18771902331@163.com> --- arch/riscv/boot/dts/canaan/k230-pinctrl.dtsi | 316 +++++++++++++++++++ arch/riscv/boot/dts/canaan/k230-pinctrl.h | 18 ++ arch/riscv/boot/dts/canaan/k230.dtsi | 2 + 3 files changed, 336 insertions(+) create mode 100644 arch/riscv/boot/dts/canaan/k230-pinctrl.dtsi create mode 100644 arch/riscv/boot/dts/canaan/k230-pinctrl.h diff --git a/arch/riscv/boot/dts/canaan/k230-pinctrl.dtsi b/arch/riscv/boot= /dts/canaan/k230-pinctrl.dtsi new file mode 100644 index 000000000000..0737f50d2868 --- /dev/null +++ b/arch/riscv/boot/dts/canaan/k230-pinctrl.dtsi @@ -0,0 +1,316 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2024 Ze Huang <18771902331@163.com> + */ +#include "k230-pinctrl.h" + +/ { + soc { + pinctrl: pinctrl@91105000 { + compatible =3D "canaan,k230-pinctrl"; + reg =3D <0x0 0x91105000 0x0 0x100>; + + jtag_pins: jtag-pins { + jtag-tck-cfg { + pinmux =3D ; + slew-rate =3D <0>; + drive-strength =3D <4>; + power-source =3D ; + input-enable; + bias-pull-down; + input-schmitt-enable; + }; + + jtag-tdi-cfg { + pinmux =3D ; + slew-rate =3D <0>; + drive-strength =3D <4>; + power-source =3D ; + input-enable; + bias-disable; + }; + + jtag-tdo-cfg { + pinmux =3D ; + slew-rate =3D <0>; + drive-strength =3D <4>; + power-source =3D ; + output-enable; + bias-disable; + }; + + jtag-tms-cfg { + pinmux =3D ; + slew-rate =3D <0>; + drive-strength =3D <4>; + power-source =3D ; + input-enable; + bias-pull-up; + }; + }; + + uart2_pins: uart2-pins { + uart2-pins-cfg { + pinmux =3D , /* uart2 txd */ + ; /* uart2 rxd */ + slew-rate =3D <0>; + drive-strength =3D <4>; + power-source =3D ; + input-enable; + output-enable; + bias-disable; + }; + }; + + pwm2_pins: pwm2-pins { + pwm2-pin-cfg { + pinmux =3D ; + slew-rate =3D <0>; + drive-strength =3D <7>; + power-source =3D ; + input-enable; + output-enable; + bias-disable; + input-schmitt-enable; + }; + }; + + pwm3_pins: pwm3-pins { + pwm3-pin-cfg { + pinmux =3D ; + slew-rate =3D <0>; + drive-strength =3D <7>; + power-source =3D ; + input-enable; + output-enable; + bias-disable; + input-schmitt-enable; + }; + }; + + pwm4_pins: pwm4-pins { + pwm4-pin-cfg { + pinmux =3D ; + slew-rate =3D <0>; + drive-strength =3D <7>; + power-source =3D ; + input-enable; + output-enable; + bias-disable; + input-schmitt-enable; + }; + }; + + iis_pins: iis-pins { + iis-clk-cfg { + pinmux =3D ; + slew-rate =3D <0>; + drive-strength =3D <4>; + power-source =3D ; + output-enable; + bias-disable; + }; + + iis-ws-cfg { + pinmux =3D ; + slew-rate =3D <0>; + drive-strength =3D <4>; + power-source =3D ; + output-enable; + bias-disable; + }; + + iis-din0-cfg { + pinmux =3D ; + slew-rate =3D <0>; + drive-strength =3D <4>; + power-source =3D ; + input-enable; + bias-disable; + }; + + iis-dout0-cfg { + pinmux =3D ; + slew-rate =3D <0>; + drive-strength =3D <4>; + power-source =3D ; + output-enable; + bias-disable; + }; + }; + + uart4_pins: uart4-pins { + uart4-txd-cfg { + pinmux =3D ; + slew-rate =3D <0>; + drive-strength =3D <7>; + power-source =3D ; + output-enable; + bias-disable; + input-schmitt-enable; + }; + + uart4-rxd-cfg { + pinmux =3D ; + slew-rate =3D <0>; + drive-strength =3D <7>; + power-source =3D ; + input-enable; + bias-disable; + input-schmitt-enable; + }; + }; + + uart0_pins: uart0-pins { + uart0-txd-cfg { + pinmux =3D ; + slew-rate =3D <0>; + drive-strength =3D <7>; + power-source =3D ; + output-enable; + bias-disable; + input-schmitt-enable; + }; + + uart0-rxd-cfg { + pinmux =3D ; + slew-rate =3D <0>; + drive-strength =3D <7>; + power-source =3D ; + input-enable; + bias-disable; + input-schmitt-enable; + }; + }; + + iic1_pins: iic1-pins { + iic1-pins-cfg { + pinmux =3D , /* iic1 scl */ + ; /* iic1 sda */ + slew-rate =3D <0>; + drive-strength =3D <7>; + power-source =3D ; + input-enable; + output-enable; + bias-pull-up; + input-schmitt-enable; + }; + }; + + iic3_pins: iic3-pins { + iic3-pins-cfg { + pinmux =3D , /* iic3 scl */ + ; /* iic3 sda */ + slew-rate =3D <0>; + drive-strength =3D <7>; + power-source =3D ; + input-enable; + output-enable; + bias-pull-up; + input-schmitt-enable; + }; + }; + + iic4_pins: iic4-pins { + iic4-pins-cfg { + pinmux =3D , /* iic4 scl */ + ; /* iic4 sda */ + slew-rate =3D <0>; + drive-strength =3D <7>; + power-source =3D ; + input-enable; + output-enable; + bias-pull-up; + input-schmitt-enable; + }; + }; + + iic0_pins: iic0-pins { + iic0-pins-cfg { + pinmux =3D , /* iic0 scl */ + ; /* iic0 sda */ + slew-rate =3D <0>; + drive-strength =3D <7>; + power-source =3D ; + input-enable; + output-enable; + bias-pull-up; + input-schmitt-enable; + }; + }; + + uart3_pins: uart3-pins { + uart3-txd-cfg { + pinmux =3D ; + slew-rate =3D <0>; + drive-strength =3D <7>; + power-source =3D ; + output-enable; + bias-disable; + input-schmitt-enable; + }; + + uart3-rxd-cfg { + pinmux =3D ; + slew-rate =3D <0>; + drive-strength =3D <7>; + power-source =3D ; + input-enable; + bias-disable; + input-schmitt-enable; + }; + }; + + key_pins: key-pins { + key-pins-cfg { + pinmux =3D , /* key0 */ + ; /* key1 */ + slew-rate =3D <0>; + drive-strength =3D <7>; + power-source =3D ; + input-enable; + output-enable; + bias-disable; + input-schmitt-enable; + }; + }; + + mmc1_pins: mmc1-pins { + mmc1-cmd-cfg { + pinmux =3D ; + slew-rate =3D <0>; + drive-strength =3D <7>; + power-source =3D ; + input-enable; + output-enable; + bias-pull-up; + input-schmitt-enable; + }; + + mmc1-clk-cfg { + pinmux =3D ; + slew-rate =3D <0>; + drive-strength =3D <7>; + power-source =3D ; + output-enable; + bias-disable; + input-schmitt-enable; + }; + + mmc1-data-cfg { + pinmux =3D , /* mmc1 data0 */ + , /* mmc1 data1 */ + , /* mmc1 data2 */ + ; /* mmc1 data3 */ + slew-rate =3D <0>; + drive-strength =3D <7>; + power-source =3D ; + input-enable; + output-enable; + bias-pull-up; + input-schmitt-enable; + }; + }; + }; + }; +}; diff --git a/arch/riscv/boot/dts/canaan/k230-pinctrl.h b/arch/riscv/boot/dt= s/canaan/k230-pinctrl.h new file mode 100644 index 000000000000..f240a980f37a --- /dev/null +++ b/arch/riscv/boot/dts/canaan/k230-pinctrl.h @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +/* + * Copyright (C) 2024 Canaan Bright Sight Co. Ltd + * Copyright (C) 2024 Ze Huang <18771902331@163.com> + */ + +#ifndef _K230_PINCTRL_H +#define _K230_PINCTRL_H + +#define K230_MSC_3V3 0 +#define K230_MSC_1V8 1 + +#define BANK_VOLTAGE_DEFAULT K230_MSC_1V8 +#define BANK_VOLTAGE_IO50_IO61 K230_MSC_3V3 + +#define K230_PINMUX(pin, mode) (((pin) << 8) | (mode)) + +#endif /* _K230_PINCTRL_H */ diff --git a/arch/riscv/boot/dts/canaan/k230.dtsi b/arch/riscv/boot/dts/can= aan/k230.dtsi index 95c1a3d8fb11..a9354e538642 100644 --- a/arch/riscv/boot/dts/canaan/k230.dtsi +++ b/arch/riscv/boot/dts/canaan/k230.dtsi @@ -140,3 +140,5 @@ uart4: serial@91404000 { }; }; }; + +#include "k230-pinctrl.dtsi" --=20 2.46.1