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[75.72.166.104]) by smtp.gmail.com with ESMTPSA id 8926c6da1cb9f-4d37ed35572sm350307173.131.2024.09.14.04.28.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 14 Sep 2024 04:28:45 -0700 (PDT) From: Adam Ford To: linux-phy@lists.infradead.org Cc: dominique.martinet@atmark-techno.com, linux-imx@nxp.com, festevam@gmail.com, frieder.schrempf@kontron.de, aford@beaconembedded.com, Sandor.yu@nxp.com, neil.armstrong@linaro.org, Adam Ford , Vinod Koul , Kishon Vijay Abraham I , Marco Felsch , Lucas Stach , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , linux-kernel@vger.kernel.org Subject: [PATCH V8 4/5] phy: freescale: fsl-samsung-hdmi: Use closest divider Date: Sat, 14 Sep 2024 06:27:48 -0500 Message-ID: <20240914112816.520224-5-aford173@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240914112816.520224-1-aford173@gmail.com> References: <20240914112816.520224-1-aford173@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Currently, if the clock values cannot be set to the exact rate, the round_rate and set_rate functions use the closest value found in the look-up-table. In preparation of removing values from the LUT that can be calculated evenly with the integer calculator, it's necessary to ensure to check both the look-up-table and the integer divider clock values to get the closest values to the requested value. It does this by measuring the difference between the requested clock value and the closest value in both integer divider calucator and the fractional clock look-up-table. Which ever has the smallest difference between them is returned as the closest rate. Signed-off-by: Adam Ford Reviewed-by: Dominique Martinet Tested-by: Dominique Martinet Reviewed-by: Frieder Schrempf --- V8: Replace Goto statement with calls to helper functions use ABS for both integer and fractional divider entries. V7: Because of the previous patch refactoring, the flow of this patch changed quite a bit to use more help functions and goto statements to hopefully make the code flow better and improve comment readability. Because of the change, I removed s-o-b and r-b, and t-b tags. V6: Simplify the calculation of the closest rate and fix a situation where the integer divider values may not be properly setup before they are used. Fixup some comments V5: No Change V4: New to series --- drivers/phy/freescale/phy-fsl-samsung-hdmi.c | 40 ++++++++++++++------ 1 file changed, 29 insertions(+), 11 deletions(-) diff --git a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c b/drivers/phy/fre= escale/phy-fsl-samsung-hdmi.c index 029de69fbeaf..381742e8b618 100644 --- a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c +++ b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c @@ -577,6 +577,16 @@ static void fsl_samsung_hdmi_calculate_phy(struct phy_= config *cal_phy, unsigned /* pll_div_regs 3-6 are fixed and pre-defined already */ } =20 +static u32 fsl_samsung_hdmi_phy_get_closest_rate(unsigned long rate, + u32 int_div_clk, u32 frac_div_clk) +{ + /* Calculate the absolute value of the differences and return whichever i= s closest */ + if (abs((long)rate - (long)int_div_clk) < abs((long)(rate - (long)frac_di= v_clk))) + return int_div_clk; + + return frac_div_clk; +} + static long phy_clk_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) { @@ -615,6 +625,15 @@ static int phy_use_fract_div(struct fsl_samsung_hdmi_p= hy *phy, const struct phy_ return fsl_samsung_hdmi_phy_configure(phy, phy->cur_cfg); } =20 +static int phy_use_integer_div(struct fsl_samsung_hdmi_phy *phy, + const struct phy_config *int_div_clk) +{ + phy->cur_cfg =3D &calculated_phy_pll_cfg; + dev_dbg(phy->dev, "fsl_samsung_hdmi_phy: integer divider rate =3D %u\n", + phy->cur_cfg->pixclk); + return fsl_samsung_hdmi_phy_configure(phy, phy->cur_cfg); +} + static int phy_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { @@ -636,20 +655,19 @@ static int phy_clk_set_rate(struct clk_hw *hw, * and use it if that value is an exact match. */ int_div_clk =3D fsl_samsung_hdmi_phy_find_pms(rate, &p, &m, &s); - if (int_div_clk =3D=3D rate) { - dev_dbg(phy->dev, "fsl_samsung_hdmi_phy: integer divider rate =3D %u\n", - int_div_clk); - - fsl_samsung_hdmi_calculate_phy(&calculated_phy_pll_cfg, int_div_clk, p, = m, s); - phy->cur_cfg =3D &calculated_phy_pll_cfg; - return fsl_samsung_hdmi_phy_configure(phy, phy->cur_cfg); - } + fsl_samsung_hdmi_calculate_phy(&calculated_phy_pll_cfg, int_div_clk, p, m= , s); + if (int_div_clk =3D=3D rate) + return phy_use_integer_div(phy, &calculated_phy_pll_cfg); =20 /* - * If neither the fractional divider nor the integer divider can find an = exact value - * fall back to using the fractional divider + * Compare the difference between the integer clock and the fractional cl= ock against + * the desired clock and which whichever is closest. */ - return phy_use_fract_div(phy, fract_div_phy); + if (fsl_samsung_hdmi_phy_get_closest_rate(rate, int_div_clk, + fract_div_phy->pixclk) =3D=3D fract_div_phy->pixclk) + return phy_use_fract_div(phy, fract_div_phy); + else + return phy_use_integer_div(phy, &calculated_phy_pll_cfg); } =20 static const struct clk_ops phy_clk_ops =3D { --=20 2.43.0