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Sat, 14 Sep 2024 09:51:21 +0000 From: William Qiu To: linux-kernel@vger.kernel.org, linux-pwm@vger.kernel.org Cc: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Hal Feng , Philipp Zabel , William Qiu Subject: [PATCH v15] pwm: opencores: Add PWM driver support Date: Sat, 14 Sep 2024 17:51:14 +0800 Message-Id: <20240914095114.31100-1-william.qiu@starfivetech.com> X-Mailer: git-send-email 2.34.1 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SH0PR01CA0002.CHNPR01.prod.partner.outlook.cn (2406:e500:c311:5::14) To ZQ0PR01MB1253.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:1b::8) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: ZQ0PR01MB1253:EE_|ZQ0PR01MB1142:EE_ X-MS-Office365-Filtering-Correlation-Id: 604908e4-adc9-4242-8fb6-08dcd4a2c9c9 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|52116014|366016|41320700013|38350700014; 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charset="utf-8" Add driver for OpenCores PWM Controller. And add compatibility code which based on StarFive SoC. Co-developed-by: Hal Feng Signed-off-by: Hal Feng Signed-off-by: William Qiu --- MAINTAINERS | 7 ++ drivers/pwm/Kconfig | 12 ++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-ocores.c | 241 +++++++++++++++++++++++++++++++++++++++ 4 files changed, 261 insertions(+) create mode 100644 drivers/pwm/pwm-ocores.c diff --git a/MAINTAINERS b/MAINTAINERS index 10430778c998..f0475a3b8683 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -17148,6 +17148,13 @@ F: Documentation/i2c/busses/i2c-ocores.rst F: drivers/i2c/busses/i2c-ocores.c F: include/linux/platform_data/i2c-ocores.h =20 +OPENCORES PWM DRIVER +M: William Qiu +M: Hal Feng +S: Supported +F: Documentation/devicetree/bindings/pwm/opencores,pwm.yaml +F: drivers/pwm/pwm-ocores.c + OPENRISC ARCHITECTURE M: Jonas Bonn M: Stefan Kristiansson diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 3e53838990f5..7682936484aa 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -464,6 +464,18 @@ config PWM_NTXEC controller found in certain e-book readers designed by the original design manufacturer Netronix. =20 +config PWM_OCORES + tristate "OpenCores PTC PWM support" + depends on HAS_IOMEM && OF + depends on COMMON_CLK + depends on ARCH_STARFIVE || COMPILE_TEST + help + If you say yes to this option, support will be included for the + OpenCores PWM. For details see https://opencores.org/projects/ptc. + + To compile this driver as a module, choose M here: the module + will be called pwm-ocores. + config PWM_OMAP_DMTIMER tristate "OMAP Dual-Mode Timer PWM support" depends on OF diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 0be4f3e6dd43..5d87811e8537 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -41,6 +41,7 @@ obj-$(CONFIG_PWM_MICROCHIP_CORE) +=3D pwm-microchip-core.o obj-$(CONFIG_PWM_MTK_DISP) +=3D pwm-mtk-disp.o obj-$(CONFIG_PWM_MXS) +=3D pwm-mxs.o obj-$(CONFIG_PWM_NTXEC) +=3D pwm-ntxec.o +obj-$(CONFIG_PWM_OCORES) +=3D pwm-ocores.o obj-$(CONFIG_PWM_OMAP_DMTIMER) +=3D pwm-omap-dmtimer.o obj-$(CONFIG_PWM_PCA9685) +=3D pwm-pca9685.o obj-$(CONFIG_PWM_PXA) +=3D pwm-pxa.o diff --git a/drivers/pwm/pwm-ocores.c b/drivers/pwm/pwm-ocores.c new file mode 100644 index 000000000000..d0161b9379d1 --- /dev/null +++ b/drivers/pwm/pwm-ocores.c @@ -0,0 +1,241 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * OpenCores PWM Driver + * + * https://opencores.org/projects/ptc + * + * Copyright (C) 2018-2023 StarFive Technology Co., Ltd. + * + * Limitations: + * - The hardware only supports inverted polarity. + * - The hardware minimum period / duty_cycle is (1 / pwm_apb clock freque= ncy). + * - The hardware maximum period / duty_cycle is (U32_MAX / pwm_apb clock = frequency). + * - The output is set to a low level immediately when disabled. + * - When configuration changes are done, they get active immediately with= out resetting + * the counter. This might result in one period affected by both old and= new settings. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* OpenCores Register offsets */ +#define REG_OCPWM_CNTR 0x0 +#define REG_OCPWM_HRC 0x4 +#define REG_OCPWM_LRC 0x8 +#define REG_OCPWM_CTRL 0xC + +/* OCPWM_CTRL register bits*/ +#define REG_OCPWM_CNTR_EN BIT(0) +#define REG_OCPWM_CNTR_ECLK BIT(1) +#define REG_OCPWM_CNTR_NEC BIT(2) +#define REG_OCPWM_CNTR_OE BIT(3) +#define REG_OCPWM_CNTR_SIGNLE BIT(4) +#define REG_OCPWM_CNTR_INTE BIT(5) +#define REG_OCPWM_CNTR_INT BIT(6) +#define REG_OCPWM_CNTR_RST BIT(7) +#define REG_OCPWM_CNTR_CAPTE BIT(8) + +struct ocores_pwm_data { + void __iomem *(*get_ch_base)(void __iomem *base, unsigned int channel); +}; + +struct ocores_pwm_device { + const struct ocores_pwm_data *data; + void __iomem *regs; + u32 clk_rate; /* PWM APB clock frequency */ +}; + +static inline u32 ocores_pwm_readl(struct ocores_pwm_device *ddata, + unsigned int channel, + unsigned int offset) +{ + void __iomem *base =3D ddata->data->get_ch_base ? + ddata->data->get_ch_base(ddata->regs, channel) : ddata->regs; + + return readl(base + offset); +} + +static inline void ocores_pwm_writel(struct ocores_pwm_device *ddata, + unsigned int channel, + unsigned int offset, u32 val) +{ + void __iomem *base =3D ddata->data->get_ch_base ? + ddata->data->get_ch_base(ddata->regs, channel) : ddata->regs; + + writel(val, base + offset); +} + +static inline struct ocores_pwm_device *chip_to_ocores(struct pwm_chip *ch= ip) +{ + return pwmchip_get_drvdata(chip); +} + +static void __iomem *starfive_get_ch_base(void __iomem *base, + unsigned int channel) +{ + unsigned int offset =3D (channel & 4) << 13 | (channel & 3) << 4; + + return base + offset; +} + +static int ocores_pwm_get_state(struct pwm_chip *chip, + struct pwm_device *pwm, + struct pwm_state *state) +{ + struct ocores_pwm_device *ddata =3D chip_to_ocores(chip); + u32 period_data, duty_data, ctrl_data; + + period_data =3D ocores_pwm_readl(ddata, pwm->hwpwm, REG_OCPWM_LRC); + duty_data =3D ocores_pwm_readl(ddata, pwm->hwpwm, REG_OCPWM_HRC); + ctrl_data =3D ocores_pwm_readl(ddata, pwm->hwpwm, REG_OCPWM_CTRL); + + state->period =3D DIV_ROUND_UP_ULL((u64)period_data * NSEC_PER_SEC, ddata= ->clk_rate); + state->duty_cycle =3D DIV_ROUND_UP_ULL((u64)duty_data * NSEC_PER_SEC, dda= ta->clk_rate); + state->polarity =3D PWM_POLARITY_INVERSED; + state->enabled =3D (ctrl_data & REG_OCPWM_CNTR_EN) ? true : false; + + return 0; +} + +static int ocores_pwm_apply(struct pwm_chip *chip, + struct pwm_device *pwm, + const struct pwm_state *state) +{ + struct ocores_pwm_device *ddata =3D chip_to_ocores(chip); + u32 ctrl_data =3D 0; + u64 period_data, duty_data; + + if (state->polarity !=3D PWM_POLARITY_INVERSED) + return -EINVAL; + + period_data =3D mul_u64_u32_div(state->period, ddata->clk_rate, NSEC_PER_= SEC); + if (!period_data) + return -EINVAL; + + if (period_data > U32_MAX) + period_data =3D U32_MAX; + + ocores_pwm_writel(ddata, pwm->hwpwm, REG_OCPWM_LRC, (u32)period_data); + + duty_data =3D mul_u64_u32_div(state->duty_cycle, ddata->clk_rate, NSEC_PE= R_SEC); + if (!duty_data) + return -EINVAL; + + if (duty_data > U32_MAX) + duty_data =3D U32_MAX; + + ocores_pwm_writel(ddata, pwm->hwpwm, REG_OCPWM_HRC, (u32)duty_data); + + ctrl_data =3D ocores_pwm_readl(ddata, pwm->hwpwm, REG_OCPWM_CTRL); + if (state->enabled) + ocores_pwm_writel(ddata, pwm->hwpwm, REG_OCPWM_CTRL, + ctrl_data | REG_OCPWM_CNTR_EN | REG_OCPWM_CNTR_OE); + else + ocores_pwm_writel(ddata, pwm->hwpwm, REG_OCPWM_CTRL, + ctrl_data & ~(REG_OCPWM_CNTR_EN | REG_OCPWM_CNTR_OE)); + + return 0; +} + +static const struct pwm_ops ocores_pwm_ops =3D { + .get_state =3D ocores_pwm_get_state, + .apply =3D ocores_pwm_apply, +}; + +static const struct ocores_pwm_data starfive_pwm_data =3D { + .get_ch_base =3D starfive_get_ch_base, +}; + +static const struct of_device_id ocores_pwm_of_match[] =3D { + { .compatible =3D "opencores,pwm-v1" }, + { .compatible =3D "starfive,jh7100-pwm", .data =3D &starfive_pwm_data}, + { .compatible =3D "starfive,jh7110-pwm", .data =3D &starfive_pwm_data}, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, ocores_pwm_of_match); + +static void ocores_pwm_reset_control_assert(void *data) +{ + reset_control_assert(data); +} + +static int ocores_pwm_probe(struct platform_device *pdev) +{ + const struct of_device_id *id; + struct device *dev =3D &pdev->dev; + struct ocores_pwm_device *ddata; + struct pwm_chip *chip; + struct clk *clk; + struct reset_control *rst; + int ret; + + id =3D of_match_device(ocores_pwm_of_match, dev); + if (!id) + return -EINVAL; + + chip =3D devm_pwmchip_alloc(&pdev->dev, 8, sizeof(*ddata)); + if (IS_ERR(chip)) + return -ENOMEM; + + ddata =3D chip_to_ocores(chip); + ddata->data =3D id->data; + chip->ops =3D &ocores_pwm_ops; + + ddata->regs =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(ddata->regs)) + return dev_err_probe(dev, PTR_ERR(ddata->regs), + "Unable to map IO resources\n"); + + clk =3D devm_clk_get_enabled(dev, NULL); + if (IS_ERR(clk)) + return dev_err_probe(dev, PTR_ERR(clk), + "Unable to get pwm's clock\n"); + + ret =3D devm_clk_rate_exclusive_get(dev, clk); + if (ret) + return ret; + + rst =3D devm_reset_control_get_optional_exclusive(dev, NULL); + if (IS_ERR(rst)) + return dev_err_probe(dev, PTR_ERR(rst), + "Unable to get pwm's reset\n"); + + ret =3D reset_control_deassert(rst); + if (ret) + return ret; + + ret =3D devm_add_action_or_reset(dev, ocores_pwm_reset_control_assert, rs= t); + if (ret) + return ret; + + ddata->clk_rate =3D clk_get_rate(clk); + if (ddata->clk_rate > NSEC_PER_SEC) + return -EINVAL; + + ret =3D devm_pwmchip_add(dev, chip); + if (ret < 0) + return dev_err_probe(dev, ret, "Could not register PWM chip\n"); + + return 0; +} + +static struct platform_driver ocores_pwm_driver =3D { + .probe =3D ocores_pwm_probe, + .driver =3D { + .name =3D "ocores-pwm", + .of_match_table =3D ocores_pwm_of_match, + }, +}; +module_platform_driver(ocores_pwm_driver); + +MODULE_AUTHOR("Jieqin Chen"); +MODULE_AUTHOR("Hal Feng "); +MODULE_DESCRIPTION("OpenCores PTC PWM driver"); +MODULE_LICENSE("GPL"); --=20 2.34.1