From nobody Fri Nov 29 23:55:21 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 69CAC8289C; Sat, 14 Sep 2024 05:25:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726291533; cv=none; b=qddRWiOR71V8yV33WIOLSIINlT9oOz1huzAgrP6yfXHhyBg2OMW/eulY2C+jG2yvW2Va+Uo47LzW7RLVREtvs9hJHpdxLrO1FaTUQS0OiUgxBP6AqzCdCo/+WYubUCKbvty1qp/GUKT/r9TA2TleC6+2ECvbIdIKewsswM0e+yc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726291533; c=relaxed/simple; bh=czVl8Hk0Vvy9SV5nolPykcop/GQI0G4YNQxbfG/ZTr4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=uWixm8xMDfA4h8MwYgiVGOXNh6zdwLx2meajnNts4ZbO1Sr0oNaFvZIKbo9UZBy9z8XlO8mcVcR8h3xFksPxbk3fi+UiYyZmhVLj63G1L1fQy+Np3yNZy3l23ypH6E8FF6qOnnXOpH5SLy/lZqZcn72EG+bzoPMapMq8n6tNl70= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=j6wRxLtC; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="j6wRxLtC" Received: by smtp.kernel.org (Postfix) with ESMTPS id 9FD39C4CED7; Sat, 14 Sep 2024 05:25:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1726291532; bh=czVl8Hk0Vvy9SV5nolPykcop/GQI0G4YNQxbfG/ZTr4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=j6wRxLtCP3M8Gv3Cj5bwML9xuRnbjJkprmx3lP+FOibk4YeVDtxS33P+hJVjAOP5G yzYfkc7SUqqP43xQhGvO6Fgll3KcN35JLXg5Ga8K5xKLDN+VfvSeRdFNgZPJgciDgc ImyJG/c8yb/WSDcw8elgsKUkE5k/la/54pcyqN0bt7gkprVgzGR8fVta9pZ975SXMm OPiK8H2wKufWndAUMmuh2NX+ymMIpYuM2plnF/ynZstZfxxITjfscXu+58yWagE/b7 tBwWvANrg7ABuQXbhPVxYL/AjEObxKto5jxKa2CWMds56Iar38fmlcpHVnB1lzZR0u CCIxTjhBGmu5w== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 98B8FFC6190; Sat, 14 Sep 2024 05:25:32 +0000 (UTC) From: Xianwei Zhao via B4 Relay Date: Sat, 14 Sep 2024 13:25:27 +0800 Subject: [PATCH 5/5] clk: meson: add A5 clock peripherals controller driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240914-a5-clk-v1-5-5ee2c4f1b08c@amlogic.com> References: <20240914-a5-clk-v1-0-5ee2c4f1b08c@amlogic.com> In-Reply-To: <20240914-a5-clk-v1-0-5ee2c4f1b08c@amlogic.com> To: Neil Armstrong , Jerome Brunet , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chuan Liu , Kevin Hilman , Martin Blumenstingl Cc: linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Xianwei Zhao X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=ed25519-sha256; t=1726291530; l=44579; i=xianwei.zhao@amlogic.com; s=20231208; h=from:subject:message-id; bh=Kve/Gn0UwoXQmUJZd0owhVCEANqSb5b0EGitN/vOiXY=; b=CSlSdmmXjUN96Gl/W/Ed8/MzhG2iJH9QS5gW9QBwuKSeNlTSLiUqsZwo+MmFC380j+2WqJI9V dooY5nd7r9wBCyFiZzxWJ/+R1cvD4ym5bpYoa+gUkPs+emsk00LsDNj X-Developer-Key: i=xianwei.zhao@amlogic.com; a=ed25519; pk=o4fDH8ZXL6xQg5h17eNzRljf6pwZHWWjqcOSsj3dW24= X-Endpoint-Received: by B4 Relay for xianwei.zhao@amlogic.com/20231208 with auth_id=107 X-Original-From: Xianwei Zhao Reply-To: xianwei.zhao@amlogic.com From: Chuan Liu Add the peripherals clock controller driver in the A5 SoC family. Signed-off-by: Chuan Liu Signed-off-by: Xianwei Zhao --- drivers/clk/meson/Kconfig | 14 + drivers/clk/meson/Makefile | 1 + drivers/clk/meson/a5-peripherals.c | 1471 ++++++++++++++++++++++++++++++++= ++++ 3 files changed, 1486 insertions(+) diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig index 2a713276e46c..21845edcd8ef 100644 --- a/drivers/clk/meson/Kconfig +++ b/drivers/clk/meson/Kconfig @@ -146,6 +146,20 @@ config COMMON_CLK_A5_PLL Say Y if you want the board to work, because PLLs are the parent of most peripherals. =20 +config COMMON_CLK_A5_PERIPHERALS + tristate "Amlogic A5 peripherals clock controller" + depends on ARM64 + default y + imply ARM_SCMI_PROTOCOL + imply COMMON_CLK_SCMI + imply COMMON_CLK_A5_PLL + select COMMON_CLK_MESON_REGMAP + select COMMON_CLK_MESON_DUALDIV + select COMMON_CLK_MESON_CLKC_UTILS + help + Support for the Peripherals clock controller on Amlogic AV40x device, + AKA A5. Say Y if you want the peripherals clock to work. + config COMMON_CLK_C3_PLL tristate "Amlogic C3 PLL clock controller" depends on ARM64 diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile index fc4b8a723145..58236c6e8377 100644 --- a/drivers/clk/meson/Makefile +++ b/drivers/clk/meson/Makefile @@ -21,6 +21,7 @@ obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) +=3D axg-audio.o obj-$(CONFIG_COMMON_CLK_A1_PLL) +=3D a1-pll.o obj-$(CONFIG_COMMON_CLK_A1_PERIPHERALS) +=3D a1-peripherals.o obj-$(CONFIG_COMMON_CLK_A5_PLL) +=3D a5-pll.o +obj-$(CONFIG_COMMON_CLK_A5_PERIPHERALS) +=3D a5-peripherals.o obj-$(CONFIG_COMMON_CLK_C3_PLL) +=3D c3-pll.o obj-$(CONFIG_COMMON_CLK_C3_PERIPHERALS) +=3D c3-peripherals.o obj-$(CONFIG_COMMON_CLK_GXBB) +=3D gxbb.o gxbb-aoclk.o diff --git a/drivers/clk/meson/a5-peripherals.c b/drivers/clk/meson/a5-peri= pherals.c new file mode 100644 index 000000000000..c28da340a5af --- /dev/null +++ b/drivers/clk/meson/a5-peripherals.c @@ -0,0 +1,1471 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Amlogic A5 Peripherals Clock Controller Driver + * + * Copyright (c) 2024 Amlogic, inc. + * Author: Chuan Liu + */ + +#include +#include +#include "clk-regmap.h" +#include "clk-dualdiv.h" +#include "meson-clkc-utils.h" +#include + +#define CLKCTRL_RTC_BY_OSCIN_CTRL0 0x8 +#define CLKCTRL_RTC_BY_OSCIN_CTRL1 0xc +#define CLKCTRL_RTC_CTRL 0x10 +#define CLKCTRL_SYS_CLK_EN0_REG0 0x44 +#define CLKCTRL_SYS_CLK_EN0_REG1 0x48 +#define CLKCTRL_DSPA_CLK_CTRL0 0x9c +#define CLKCTRL_CLK12_24_CTRL 0xa8 +#define CLKCTRL_AXI_CLK_EN0 0xac +#define CLKCTRL_TS_CLK_CTRL 0x158 +#define CLKCTRL_ETH_CLK_CTRL 0x164 +#define CLKCTRL_NAND_CLK_CTRL 0x168 +#define CLKCTRL_SD_EMMC_CLK_CTRL 0x16c +#define CLKCTRL_SPICC_CLK_CTRL 0x174 +#define CLKCTRL_GEN_CLK_CTRL 0x178 +#define CLKCTRL_SAR_CLK_CTRL0 0x17c +#define CLKCTRL_PWM_CLK_AB_CTRL 0x180 +#define CLKCTRL_PWM_CLK_CD_CTRL 0x184 +#define CLKCTRL_PWM_CLK_EF_CTRL 0x188 +#define CLKCTRL_PWM_CLK_GH_CTRL 0x18c +#define CLKCTRL_NNA_CLK_CNTL 0x220 + +static struct clk_regmap rtc_xtal_clkin =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D CLKCTRL_RTC_BY_OSCIN_CTRL0, + .bit_idx =3D 31, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "rtc_xtal_clkin", + .ops =3D &clk_regmap_gate_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "oscin", + }, + .num_parents =3D 1, + }, +}; + +static const struct meson_clk_dualdiv_param rtc_32k_div_table[] =3D { + { 733, 732, 8, 11, 1 }, + { /* sentinel */ } +}; + +static struct clk_regmap rtc_32k_div =3D { + .data =3D &(struct meson_clk_dualdiv_data) { + .n1 =3D { + .reg_off =3D CLKCTRL_RTC_BY_OSCIN_CTRL0, + .shift =3D 0, + .width =3D 12, + }, + .n2 =3D { + .reg_off =3D CLKCTRL_RTC_BY_OSCIN_CTRL0, + .shift =3D 12, + .width =3D 12, + }, + .m1 =3D { + .reg_off =3D CLKCTRL_RTC_BY_OSCIN_CTRL1, + .shift =3D 0, + .width =3D 12, + }, + .m2 =3D { + .reg_off =3D CLKCTRL_RTC_BY_OSCIN_CTRL1, + .shift =3D 12, + .width =3D 12, + }, + .dual =3D { + .reg_off =3D CLKCTRL_RTC_BY_OSCIN_CTRL0, + .shift =3D 28, + .width =3D 1, + }, + .table =3D rtc_32k_div_table, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "rtc_32k_div", + .ops =3D &meson_clk_dualdiv_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &rtc_xtal_clkin.hw + }, + .num_parents =3D 1, + }, +}; + +static const struct clk_parent_data rtc_32k_mux_parent_data[] =3D { + { .hw =3D &rtc_32k_div.hw }, + { .hw =3D &rtc_xtal_clkin.hw } +}; + +static struct clk_regmap rtc_32k_mux =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D CLKCTRL_RTC_BY_OSCIN_CTRL1, + .mask =3D 0x1, + .shift =3D 24, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "rtc_32k_mux", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D rtc_32k_mux_parent_data, + .num_parents =3D ARRAY_SIZE(rtc_32k_mux_parent_data), + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap rtc_32k =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D CLKCTRL_RTC_BY_OSCIN_CTRL0, + .bit_idx =3D 30, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "rtc_32k", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &rtc_32k_mux.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static const struct clk_parent_data rtc_clk_mux_parent_data[] =3D { + { .fw_name =3D "oscin" }, + { .hw =3D &rtc_32k.hw }, + { .fw_name =3D "pad_osc" } +}; + +static struct clk_regmap rtc_clk =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D CLKCTRL_RTC_CTRL, + .mask =3D 0x3, + .shift =3D 0, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "rtc_clk", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D rtc_clk_mux_parent_data, + .num_parents =3D ARRAY_SIZE(rtc_clk_mux_parent_data), + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +#define A4_CLK_GATE(_name, _reg, _bit, _fw_name, _ops, _flags) \ +struct clk_regmap _name =3D { \ + .data =3D &(struct clk_regmap_gate_data){ \ + .offset =3D (_reg), \ + .bit_idx =3D (_bit), \ + }, \ + .hw.init =3D &(struct clk_init_data) { \ + .name =3D #_name, \ + .ops =3D _ops, \ + .parent_data =3D &(const struct clk_parent_data) { \ + .fw_name =3D #_fw_name, \ + }, \ + .num_parents =3D 1, \ + .flags =3D (_flags), \ + }, \ +} + +#define A4_SYS_GATE(_name, _reg, _bit, _flags) \ + A4_CLK_GATE(_name, _reg, _bit, sysclk, \ + &clk_regmap_gate_ops, _flags) + +#define A4_SYS_GATE_RO(_name, _reg, _bit) \ + A4_CLK_GATE(_name, _reg, _bit, sysclk, \ + &clk_regmap_gate_ro_ops, 0) + +static A4_SYS_GATE(sys_reset_ctrl, CLKCTRL_SYS_CLK_EN0_REG0, 1, 0); +static A4_SYS_GATE(sys_pwr_ctrl, CLKCTRL_SYS_CLK_EN0_REG0, 3, 0); +static A4_SYS_GATE(sys_pad_ctrl, CLKCTRL_SYS_CLK_EN0_REG0, 4, 0); +static A4_SYS_GATE(sys_ctrl, CLKCTRL_SYS_CLK_EN0_REG0, 5, 0); +static A4_SYS_GATE(sys_ts_pll, CLKCTRL_SYS_CLK_EN0_REG0, 6, 0); + +/* + * NOTE: sys_dev_arb provides the clock to the ETH and SPICC arbiters that + * access the AXI bus. + */ +static A4_SYS_GATE(sys_dev_arb, CLKCTRL_SYS_CLK_EN0_REG0, 7, 0); + +/* + * FIXME: sys_mmc_pclk provides the clock for the DDR PHY, DDR will only be + * initialized in bl2, and this clock should not be touched in linux. + */ +static A4_SYS_GATE_RO(sys_mmc_pclk, CLKCTRL_SYS_CLK_EN0_REG0, 8); +static A4_SYS_GATE(sys_mailbox, CLKCTRL_SYS_CLK_EN0_REG0, 10, 0); + +/* + * NOTE: sys_cpu_ctrl provides the clock for CPU controller. After clock is + * disabled, cpu_clk and other key CPU-related configurations cannot take = effect. + */ +static A4_SYS_GATE(sys_cpu_ctrl, CLKCTRL_SYS_CLK_EN0_REG0, 11, CLK_IS_CRIT= ICAL); +static A4_SYS_GATE(sys_jtag_ctrl, CLKCTRL_SYS_CLK_EN0_REG0, 12, 0); +static A4_SYS_GATE(sys_ir_ctrl, CLKCTRL_SYS_CLK_EN0_REG0, 13, 0); + +/* + * NOTE: sys_irq_ctrl provides the clock for IRQ controller. The IRQ contr= oller + * collects and distributes the interrupt signal to the GIC, PWR_CTRL, and + * AOCPU. If the clock is disabled, interrupt-related functions will occur= s an + * exception. + */ +static A4_SYS_GATE(sys_irq_ctrl, CLKCTRL_SYS_CLK_EN0_REG0, 14, CLK_IS_CRIT= ICAL); +static A4_SYS_GATE(sys_msr_clk, CLKCTRL_SYS_CLK_EN0_REG0, 15, 0); +static A4_SYS_GATE(sys_rom, CLKCTRL_SYS_CLK_EN0_REG0, 16, 0); +static A4_SYS_GATE(sys_cpu_apb, CLKCTRL_SYS_CLK_EN0_REG0, 18, 0); +static A4_SYS_GATE(sys_rsa, CLKCTRL_SYS_CLK_EN0_REG0, 19, 0); +static A4_SYS_GATE(sys_sar_adc, CLKCTRL_SYS_CLK_EN0_REG0, 20, 0); +static A4_SYS_GATE(sys_startup, CLKCTRL_SYS_CLK_EN0_REG0, 21, 0); +static A4_SYS_GATE(sys_secure, CLKCTRL_SYS_CLK_EN0_REG0, 22, 0); +static A4_SYS_GATE(sys_spifc, CLKCTRL_SYS_CLK_EN0_REG0, 23, 0); +static A4_SYS_GATE(sys_dspa, CLKCTRL_SYS_CLK_EN0_REG0, 24, 0); +static A4_SYS_GATE(sys_nna, CLKCTRL_SYS_CLK_EN0_REG0, 25, 0); +static A4_SYS_GATE(sys_eth_mac, CLKCTRL_SYS_CLK_EN0_REG0, 26, 0); + +/* + * FIXME: sys_gic provides the clock for GIC(Generic Interrupt Controller). + * After clock is disabled, The GIC cannot work properly. At present, the = driver + * used by our GIC is the public driver in kernel, and there is no managem= ent + * clock in the driver. + */ +static A4_SYS_GATE(sys_gic, CLKCTRL_SYS_CLK_EN0_REG0, 27, CLK_IS_CRITICAL= ); +static A4_SYS_GATE(sys_rama, CLKCTRL_SYS_CLK_EN0_REG0, 28, 0); + +/* + * NOTE: sys_big_nic provides the clock to the control bus of the NIC(Netw= ork + * Interface Controller) between multiple devices(CPU, DDR, RAM, ROM, GIC, + * SPIFC, CAPU, JTAG, EMMC, SDIO, sec_top, USB, Audio, ETH, SPICC) in the + * system. After clock is disabled, The NIC cannot work. + */ +static A4_SYS_GATE(sys_big_nic, CLKCTRL_SYS_CLK_EN0_REG0, 29, CLK_IS_CRIT= ICAL); +static A4_SYS_GATE(sys_ramb, CLKCTRL_SYS_CLK_EN0_REG0, 30, 0); +static A4_SYS_GATE(sys_audio_top, CLKCTRL_SYS_CLK_EN0_REG1, 0, 0); +static A4_SYS_GATE(sys_audio_vad, CLKCTRL_SYS_CLK_EN0_REG1, 1, 0); +static A4_SYS_GATE(sys_usb, CLKCTRL_SYS_CLK_EN0_REG1, 2, 0); +static A4_SYS_GATE(sys_sd_emmc_a, CLKCTRL_SYS_CLK_EN0_REG1, 3, 0); +static A4_SYS_GATE(sys_sd_emmc_c, CLKCTRL_SYS_CLK_EN0_REG1, 4, 0); +static A4_SYS_GATE(sys_pwm_ab, CLKCTRL_SYS_CLK_EN0_REG1, 5, 0); +static A4_SYS_GATE(sys_pwm_cd, CLKCTRL_SYS_CLK_EN0_REG1, 6, 0); +static A4_SYS_GATE(sys_pwm_ef, CLKCTRL_SYS_CLK_EN0_REG1, 7, 0); +static A4_SYS_GATE(sys_pwm_gh, CLKCTRL_SYS_CLK_EN0_REG1, 8, 0); +static A4_SYS_GATE(sys_spicc_1, CLKCTRL_SYS_CLK_EN0_REG1, 9, 0); +static A4_SYS_GATE(sys_spicc_0, CLKCTRL_SYS_CLK_EN0_REG1, 10, 0); +static A4_SYS_GATE(sys_uart_a, CLKCTRL_SYS_CLK_EN0_REG1, 11, 0); +static A4_SYS_GATE(sys_uart_b, CLKCTRL_SYS_CLK_EN0_REG1, 12, 0); +static A4_SYS_GATE(sys_uart_c, CLKCTRL_SYS_CLK_EN0_REG1, 13, 0); +static A4_SYS_GATE(sys_uart_d, CLKCTRL_SYS_CLK_EN0_REG1, 14, 0); +static A4_SYS_GATE(sys_uart_e, CLKCTRL_SYS_CLK_EN0_REG1, 15, 0); +static A4_SYS_GATE(sys_i2c_m_a, CLKCTRL_SYS_CLK_EN0_REG1, 16, 0); +static A4_SYS_GATE(sys_i2c_m_b, CLKCTRL_SYS_CLK_EN0_REG1, 17, 0); +static A4_SYS_GATE(sys_i2c_m_c, CLKCTRL_SYS_CLK_EN0_REG1, 18, 0); +static A4_SYS_GATE(sys_i2c_m_d, CLKCTRL_SYS_CLK_EN0_REG1, 19, 0); +static A4_SYS_GATE(sys_rtc, CLKCTRL_SYS_CLK_EN0_REG1, 21, 0); + +#define A4_AXI_GATE(_name, _reg, _bit, _flags) \ + A4_CLK_GATE(_name, _reg, _bit, axiclk, \ + &clk_regmap_gate_ops, _flags) + +static A4_AXI_GATE(axi_audio_vad, CLKCTRL_AXI_CLK_EN0, 0, 0); +static A4_AXI_GATE(axi_audio_top, CLKCTRL_AXI_CLK_EN0, 1, 0); + +/* + * NOTE: axi_sys_nic provides the clock to the AXI bus of the system NIC. = After + * clock is disabled, The NIC cannot work. + */ +static A4_AXI_GATE(axi_sys_nic, CLKCTRL_AXI_CLK_EN0, 2, CLK_IS_CRITICAL); +static A4_AXI_GATE(axi_ramb, CLKCTRL_AXI_CLK_EN0, 5, 0); +static A4_AXI_GATE(axi_rama, CLKCTRL_AXI_CLK_EN0, 6, 0); + +/* + * NOTE: axi_cpu_dmc provides the clock to the AXI bus where the CPU acces= ses + * the DDR. After clock is disabled, The CPU will not have access to the D= DR. + */ +static A4_AXI_GATE(axi_cpu_dmc, CLKCTRL_AXI_CLK_EN0, 7, CLK_IS_CRITICAL); +static A4_AXI_GATE(axi_nna, CLKCTRL_AXI_CLK_EN0, 12, 0); + +/* + * NOTE: axi_dev1_dmc provides the clock for the peripherals(EMMC, SDIO, + * sec_top, USB, Audio) to access the AXI bus of the DDR. + */ +static A4_AXI_GATE(axi_dev1_dmc, CLKCTRL_AXI_CLK_EN0, 13, 0); + +/* + * NOTE: axi_dev0_dmc provides the clock for the peripherals(ETH and SPICC) + * to access the AXI bus of the DDR. + */ +static A4_AXI_GATE(axi_dev0_dmc, CLKCTRL_AXI_CLK_EN0, 14, 0); +static A4_AXI_GATE(axi_dsp_dmc, CLKCTRL_AXI_CLK_EN0, 15, 0); + +static struct clk_regmap clk_12_24m_in =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D CLKCTRL_CLK12_24_CTRL, + .bit_idx =3D 11, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "clk_12_24m_in", + .ops =3D &clk_regmap_gate_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "xtal_24m", + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap clk_12_24m =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D CLKCTRL_CLK12_24_CTRL, + .shift =3D 10, + .width =3D 1, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "clk_12_24m", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &clk_12_24m_in.hw + }, + .num_parents =3D 1, + }, +}; + +/* FIXME: set value 0 will div by 2 like value 1 */ +static struct clk_regmap fclk_25m_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D CLKCTRL_CLK12_24_CTRL, + .shift =3D 0, + .width =3D 8, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "fclk_25m_div", + .ops =3D &clk_regmap_divider_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "fix", + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap fclk_25m =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D CLKCTRL_CLK12_24_CTRL, + .bit_idx =3D 12, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "fclk_25m", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &fclk_25m_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +/* + * Channel 3(ddr_dpll_pt_clk) is manged by the DDR module; channel 12(cts_= msr_clk) + * is manged by clock measures module. Their hardware are out of clock tre= e. + * Channel 4 5 8 9 10 11 13 14 15 16 18 are not connected. + * + * gp1 is designed for DSU (DynamIQ Shared Unit) alone. It cannot be chang= ed + * arbitrarily. gp1 is read-only in the kernel and is only open for debug = purposes. + */ +static u32 gen_parent_table[] =3D { 0, 1, 2, 6, 7, 17, 19, 20, 21, 22, 23,= 24, 25, + 26, 27, 28}; + +static const struct clk_parent_data gen_parent_data[] =3D { + { .fw_name =3D "oscin" }, + { .hw =3D &rtc_clk.hw }, + { .fw_name =3D "sysplldiv16" }, + { .fw_name =3D "gp1" }, + { .fw_name =3D "hifi" }, + { .fw_name =3D "cpudiv16" }, + { .fw_name =3D "fdiv2" }, + { .fw_name =3D "fdiv2p5" }, + { .fw_name =3D "fdiv3" }, + { .fw_name =3D "fdiv4" }, + { .fw_name =3D "fdiv5" }, + { .fw_name =3D "fdiv7" }, + { .fw_name =3D "mpll0" }, + { .fw_name =3D "mpll1" }, + { .fw_name =3D "mpll2" }, + { .fw_name =3D "mpll3" } +}; + +static struct clk_regmap gen_sel =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D CLKCTRL_GEN_CLK_CTRL, + .mask =3D 0x1f, + .shift =3D 12, + .table =3D gen_parent_table, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "gen_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D gen_parent_data, + .num_parents =3D ARRAY_SIZE(gen_parent_data), + }, +}; + +static struct clk_regmap gen_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D CLKCTRL_GEN_CLK_CTRL, + .shift =3D 0, + .width =3D 11, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "gen_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &gen_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap gen =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D CLKCTRL_GEN_CLK_CTRL, + .bit_idx =3D 11, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "gen", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &gen_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static const struct clk_parent_data saradc_parent_data[] =3D { + { .fw_name =3D "oscin" }, + { .fw_name =3D "sysclk" } +}; + +static struct clk_regmap saradc_sel =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D CLKCTRL_SAR_CLK_CTRL0, + .mask =3D 0x1, + .shift =3D 9, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "saradc_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D saradc_parent_data, + .num_parents =3D ARRAY_SIZE(saradc_parent_data), + }, +}; + +static struct clk_regmap saradc_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D CLKCTRL_SAR_CLK_CTRL0, + .shift =3D 0, + .width =3D 8, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "saradc_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &saradc_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap saradc =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D CLKCTRL_SAR_CLK_CTRL0, + .bit_idx =3D 8, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "saradc", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &saradc_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static const struct clk_parent_data pwm_parent_data[] =3D { + { .fw_name =3D "oscin" }, + { .hw =3D &rtc_clk.hw }, + { .fw_name =3D "fdiv4" }, + { .fw_name =3D "fdiv3" } +}; + +#define AML_PWM_CLK_MUX(_name, _reg, _shift) { \ + .data =3D &(struct clk_regmap_mux_data) { \ + .offset =3D _reg, \ + .mask =3D 0x3, \ + .shift =3D _shift, \ + }, \ + .hw.init =3D &(struct clk_init_data) { \ + .name =3D #_name "_sel", \ + .ops =3D &clk_regmap_mux_ops, \ + .parent_data =3D pwm_parent_data, \ + .num_parents =3D ARRAY_SIZE(pwm_parent_data), \ + }, \ +} + +#define AML_PWM_CLK_DIV(_name, _reg, _shift) { \ + .data =3D &(struct clk_regmap_div_data) { \ + .offset =3D _reg, \ + .shift =3D _shift, \ + .width =3D 8, \ + }, \ + .hw.init =3D &(struct clk_init_data) { \ + .name =3D #_name "_div", \ + .ops =3D &clk_regmap_divider_ops, \ + .parent_names =3D (const char *[]) { #_name "_sel" },\ + .num_parents =3D 1, \ + .flags =3D CLK_SET_RATE_PARENT, \ + }, \ +} + +#define AML_PWM_CLK_GATE(_name, _reg, _bit) { \ + .data =3D &(struct clk_regmap_gate_data) { \ + .offset =3D _reg, \ + .bit_idx =3D _bit, \ + }, \ + .hw.init =3D &(struct clk_init_data) { \ + .name =3D #_name, \ + .ops =3D &clk_regmap_gate_ops, \ + .parent_names =3D (const char *[]) { #_name "_div" },\ + .num_parents =3D 1, \ + .flags =3D CLK_SET_RATE_PARENT, \ + }, \ +} + +static struct clk_regmap pwm_a_sel =3D + AML_PWM_CLK_MUX(pwm_a, CLKCTRL_PWM_CLK_AB_CTRL, 9); +static struct clk_regmap pwm_a_div =3D + AML_PWM_CLK_DIV(pwm_a, CLKCTRL_PWM_CLK_AB_CTRL, 0); +static struct clk_regmap pwm_a =3D + AML_PWM_CLK_GATE(pwm_a, CLKCTRL_PWM_CLK_AB_CTRL, 8); + +static struct clk_regmap pwm_b_sel =3D + AML_PWM_CLK_MUX(pwm_b, CLKCTRL_PWM_CLK_AB_CTRL, 25); +static struct clk_regmap pwm_b_div =3D + AML_PWM_CLK_DIV(pwm_b, CLKCTRL_PWM_CLK_AB_CTRL, 16); +static struct clk_regmap pwm_b =3D + AML_PWM_CLK_GATE(pwm_b, CLKCTRL_PWM_CLK_AB_CTRL, 24); + +static struct clk_regmap pwm_c_sel =3D + AML_PWM_CLK_MUX(pwm_c, CLKCTRL_PWM_CLK_CD_CTRL, 9); +static struct clk_regmap pwm_c_div =3D + AML_PWM_CLK_DIV(pwm_c, CLKCTRL_PWM_CLK_CD_CTRL, 0); +static struct clk_regmap pwm_c =3D + AML_PWM_CLK_GATE(pwm_c, CLKCTRL_PWM_CLK_CD_CTRL, 8); + +static struct clk_regmap pwm_d_sel =3D + AML_PWM_CLK_MUX(pwm_d, CLKCTRL_PWM_CLK_CD_CTRL, 25); +static struct clk_regmap pwm_d_div =3D + AML_PWM_CLK_DIV(pwm_d, CLKCTRL_PWM_CLK_CD_CTRL, 16); +static struct clk_regmap pwm_d =3D + AML_PWM_CLK_GATE(pwm_d, CLKCTRL_PWM_CLK_CD_CTRL, 24); + +static struct clk_regmap pwm_e_sel =3D + AML_PWM_CLK_MUX(pwm_e, CLKCTRL_PWM_CLK_EF_CTRL, 9); +static struct clk_regmap pwm_e_div =3D + AML_PWM_CLK_DIV(pwm_e, CLKCTRL_PWM_CLK_EF_CTRL, 0); +static struct clk_regmap pwm_e =3D + AML_PWM_CLK_GATE(pwm_e, CLKCTRL_PWM_CLK_EF_CTRL, 8); + +static struct clk_regmap pwm_f_sel =3D + AML_PWM_CLK_MUX(pwm_f, CLKCTRL_PWM_CLK_EF_CTRL, 25); +static struct clk_regmap pwm_f_div =3D + AML_PWM_CLK_DIV(pwm_f, CLKCTRL_PWM_CLK_EF_CTRL, 16); +static struct clk_regmap pwm_f =3D + AML_PWM_CLK_GATE(pwm_f, CLKCTRL_PWM_CLK_EF_CTRL, 24); + +static struct clk_regmap pwm_g_sel =3D + AML_PWM_CLK_MUX(pwm_g, CLKCTRL_PWM_CLK_GH_CTRL, 9); +static struct clk_regmap pwm_g_div =3D + AML_PWM_CLK_DIV(pwm_g, CLKCTRL_PWM_CLK_GH_CTRL, 0); +static struct clk_regmap pwm_g =3D + AML_PWM_CLK_GATE(pwm_g, CLKCTRL_PWM_CLK_GH_CTRL, 8); + +static struct clk_regmap pwm_h_sel =3D + AML_PWM_CLK_MUX(pwm_h, CLKCTRL_PWM_CLK_GH_CTRL, 25); +static struct clk_regmap pwm_h_div =3D + AML_PWM_CLK_DIV(pwm_h, CLKCTRL_PWM_CLK_GH_CTRL, 16); +static struct clk_regmap pwm_h =3D + AML_PWM_CLK_GATE(pwm_h, CLKCTRL_PWM_CLK_GH_CTRL, 24); + +/* Channel 7 is gp1. */ +static const struct clk_parent_data spicc_parent_data[] =3D { + { .fw_name =3D "oscin" }, + { .fw_name =3D "sysclk" }, + { .fw_name =3D "fdiv4" }, + { .fw_name =3D "fdiv3" }, + { .fw_name =3D "fdiv2" }, + { .fw_name =3D "fdiv5" }, + { .fw_name =3D "fdiv7" } +}; + +static struct clk_regmap spicc_0_sel =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D CLKCTRL_SPICC_CLK_CTRL, + .mask =3D 0x7, + .shift =3D 7, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "spicc_0_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D spicc_parent_data, + .num_parents =3D ARRAY_SIZE(spicc_parent_data), + }, +}; + +static struct clk_regmap spicc_0_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D CLKCTRL_SPICC_CLK_CTRL, + .shift =3D 0, + .width =3D 6, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "spicc_0_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &spicc_0_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap spicc_0 =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D CLKCTRL_SPICC_CLK_CTRL, + .bit_idx =3D 6, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "spicc_0", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &spicc_0_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap spicc_1_sel =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D CLKCTRL_SPICC_CLK_CTRL, + .mask =3D 0x7, + .shift =3D 23, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "spicc_1_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D spicc_parent_data, + .num_parents =3D ARRAY_SIZE(spicc_parent_data), + }, +}; + +static struct clk_regmap spicc_1_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D CLKCTRL_SPICC_CLK_CTRL, + .shift =3D 16, + .width =3D 6, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "spicc_1_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &spicc_1_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap spicc_1 =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D CLKCTRL_SPICC_CLK_CTRL, + .bit_idx =3D 22, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "spicc_1", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &spicc_1_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static const struct clk_parent_data emmc_parent_data[] =3D { + { .fw_name =3D "oscin" }, + { .fw_name =3D "fdiv2" }, + { .fw_name =3D "fdiv3" }, + { .fw_name =3D "hifi" }, + { .fw_name =3D "fdiv2p5" }, + { .fw_name =3D "mpll2" }, + { .fw_name =3D "mpll3" }, + { .fw_name =3D "gp0" } +}; + +static struct clk_regmap sd_emmc_a_sel =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D CLKCTRL_SD_EMMC_CLK_CTRL, + .mask =3D 0x7, + .shift =3D 9, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "sd_emmc_a_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D emmc_parent_data, + .num_parents =3D ARRAY_SIZE(emmc_parent_data), + }, +}; + +static struct clk_regmap sd_emmc_a_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D CLKCTRL_SD_EMMC_CLK_CTRL, + .shift =3D 0, + .width =3D 7, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "sd_emmc_a_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &sd_emmc_a_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap sd_emmc_a =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D CLKCTRL_SD_EMMC_CLK_CTRL, + .bit_idx =3D 7, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "sd_emmc_a", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &sd_emmc_a_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap sd_emmc_c_sel =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D CLKCTRL_NAND_CLK_CTRL, + .mask =3D 0x7, + .shift =3D 9, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "sd_emmc_c_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D emmc_parent_data, + .num_parents =3D ARRAY_SIZE(emmc_parent_data), + }, +}; + +static struct clk_regmap sd_emmc_c_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D CLKCTRL_NAND_CLK_CTRL, + .shift =3D 0, + .width =3D 7, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "sd_emmc_c_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &sd_emmc_c_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap sd_emmc_c =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D CLKCTRL_NAND_CLK_CTRL, + .bit_idx =3D 7, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "sd_emmc_c", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &sd_emmc_c_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap ts_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D CLKCTRL_TS_CLK_CTRL, + .shift =3D 0, + .width =3D 8, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "ts_div", + .ops =3D &clk_regmap_divider_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "oscin", + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap ts =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D CLKCTRL_TS_CLK_CTRL, + .bit_idx =3D 8, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "ts", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &ts_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_fixed_factor eth_125m_div =3D { + .mult =3D 1, + .div =3D 8, + .hw.init =3D &(struct clk_init_data) { + .name =3D "eth_125m_div", + .ops =3D &clk_fixed_factor_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "fdiv2", + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap eth_125m =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D CLKCTRL_ETH_CLK_CTRL, + .bit_idx =3D 7, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "eth_125m", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + ð_125m_div.hw + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap eth_rmii_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D CLKCTRL_ETH_CLK_CTRL, + .shift =3D 0, + .width =3D 7, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "eth_rmii_div", + .ops =3D &clk_regmap_divider_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "fdiv2", + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap eth_rmii =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D CLKCTRL_ETH_CLK_CTRL, + .bit_idx =3D 8, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "eth_rmii", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + ð_rmii_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +/* Channel 6 is gp1. */ +static u32 dspa_parent_table[] =3D { 0, 1, 2, 3, 4, 5, 7}; + +static const struct clk_parent_data dspa_parent_data[] =3D { + { .fw_name =3D "oscin" }, + { .fw_name =3D "fdiv2p5" }, + { .fw_name =3D "fdiv3" }, + { .fw_name =3D "rtc" }, + { .fw_name =3D "hifi" }, + { .fw_name =3D "fdiv4" }, + { .hw =3D &rtc_clk.hw } +}; + +static struct clk_regmap dspa_0_sel =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D CLKCTRL_DSPA_CLK_CTRL0, + .mask =3D 0x7, + .shift =3D 10, + .table =3D dspa_parent_table, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "dspa_0_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D dspa_parent_data, + .num_parents =3D ARRAY_SIZE(dspa_parent_data), + }, +}; + +static struct clk_regmap dspa_0_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D CLKCTRL_DSPA_CLK_CTRL0, + .shift =3D 0, + .width =3D 10, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "dspa_0_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &dspa_0_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap dspa_0 =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D CLKCTRL_DSPA_CLK_CTRL0, + .bit_idx =3D 13, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "dspa_0", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &dspa_0_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap dspa_1_sel =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D CLKCTRL_DSPA_CLK_CTRL0, + .mask =3D 0x7, + .shift =3D 26, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "dspa_1_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D dspa_parent_data, + .num_parents =3D ARRAY_SIZE(dspa_parent_data), + }, +}; + +static struct clk_regmap dspa_1_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D CLKCTRL_DSPA_CLK_CTRL0, + .shift =3D 16, + .width =3D 10, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "dspa_1_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &dspa_1_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap dspa_1 =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D CLKCTRL_DSPA_CLK_CTRL0, + .bit_idx =3D 29, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "dspa_1", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &dspa_1_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap dspa =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D CLKCTRL_DSPA_CLK_CTRL0, + .mask =3D 0x1, + .shift =3D 15, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "dspa", + .ops =3D &clk_regmap_mux_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &dspa_0.hw, + &dspa_1.hw + }, + .num_parents =3D 2, + /* + * NOTE: This level of mux is "no glitch mux", and mux_0 + * (here dspa_0) is not only the clock source for mux, but also + * provides a working clock for "no glitch mux". "no glitch mux" + * can be switched only when mux_0 has a clock input. Therefore, + * add flag CLK_OPS_PARENT_ENABLE to ensure that mux_0 has clock + * when "no glitch mux" works. + */ + .flags =3D CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, + }, +}; + +/* Channel 6 is gp1. */ +static u32 nna_parent_table[] =3D { 0, 1, 2, 3, 4, 5, 7}; + +static const struct clk_parent_data nna_parent_data[] =3D { + { .fw_name =3D "oscin" }, + { .fw_name =3D "fdiv2p5" }, + { .fw_name =3D "fdiv4" }, + { .fw_name =3D "fdiv3" }, + { .fw_name =3D "fdiv5" }, + { .fw_name =3D "fdiv2" }, + { .fw_name =3D "hifi" } +}; + +static struct clk_regmap nna_core_sel =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D CLKCTRL_NNA_CLK_CNTL, + .mask =3D 0x7, + .shift =3D 9, + .table =3D nna_parent_table, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "nna_core_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D nna_parent_data, + .num_parents =3D ARRAY_SIZE(nna_parent_data), + }, +}; + +static struct clk_regmap nna_core_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D CLKCTRL_NNA_CLK_CNTL, + .shift =3D 0, + .width =3D 7, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "nna_core_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &nna_core_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap nna_core =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D CLKCTRL_NNA_CLK_CNTL, + .bit_idx =3D 8, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "nna_core", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &nna_core_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap nna_axi_sel =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D CLKCTRL_NNA_CLK_CNTL, + .mask =3D 0x7, + .shift =3D 25, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "nna_axi_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D nna_parent_data, + .num_parents =3D ARRAY_SIZE(nna_parent_data), + }, +}; + +static struct clk_regmap nna_axi_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D CLKCTRL_NNA_CLK_CNTL, + .shift =3D 16, + .width =3D 7, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "nna_axi_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &nna_axi_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap nna_axi =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D CLKCTRL_NNA_CLK_CNTL, + .bit_idx =3D 24, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "nna_axi", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &nna_axi_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_hw *a5_periphs_hw_clks[] =3D { + [CLKID_RTC_XTAL_CLKIN] =3D &rtc_xtal_clkin.hw, + [CLKID_RTC_32K_DIV] =3D &rtc_32k_div.hw, + [CLKID_RTC_32K_MUX] =3D &rtc_32k_mux.hw, + [CLKID_RTC_32K] =3D &rtc_32k.hw, + [CLKID_RTC_CLK] =3D &rtc_clk.hw, + [CLKID_SYS_RESET_CTRL] =3D &sys_reset_ctrl.hw, + [CLKID_SYS_PWR_CTRL] =3D &sys_pwr_ctrl.hw, + [CLKID_SYS_PAD_CTRL] =3D &sys_pad_ctrl.hw, + [CLKID_SYS_CTRL] =3D &sys_ctrl.hw, + [CLKID_SYS_TS_PLL] =3D &sys_ts_pll.hw, + [CLKID_SYS_DEV_ARB] =3D &sys_dev_arb.hw, + [CLKID_SYS_MMC_PCLK] =3D &sys_mmc_pclk.hw, + [CLKID_SYS_MAILBOX] =3D &sys_mailbox.hw, + [CLKID_SYS_CPU_CTRL] =3D &sys_cpu_ctrl.hw, + [CLKID_SYS_JTAG_CTRL] =3D &sys_jtag_ctrl.hw, + [CLKID_SYS_IR_CTRL] =3D &sys_ir_ctrl.hw, + [CLKID_SYS_IRQ_CTRL] =3D &sys_irq_ctrl.hw, + [CLKID_SYS_MSR_CLK] =3D &sys_msr_clk.hw, + [CLKID_SYS_ROM] =3D &sys_rom.hw, + [CLKID_SYS_CPU_ARB] =3D &sys_cpu_apb.hw, + [CLKID_SYS_RSA] =3D &sys_rsa.hw, + [CLKID_SYS_SAR_ADC] =3D &sys_sar_adc.hw, + [CLKID_SYS_STARTUP] =3D &sys_startup.hw, + [CLKID_SYS_SECURE] =3D &sys_secure.hw, + [CLKID_SYS_SPIFC] =3D &sys_spifc.hw, + [CLKID_SYS_DSPA] =3D &sys_dspa.hw, + [CLKID_SYS_NNA] =3D &sys_nna.hw, + [CLKID_SYS_ETH_MAC] =3D &sys_eth_mac.hw, + [CLKID_SYS_GIC] =3D &sys_gic.hw, + [CLKID_SYS_RAMA] =3D &sys_rama.hw, + [CLKID_SYS_BIG_NIC] =3D &sys_big_nic.hw, + [CLKID_SYS_RAMB] =3D &sys_ramb.hw, + [CLKID_SYS_AUDIO_TOP] =3D &sys_audio_top.hw, + [CLKID_SYS_AUDIO_VAD] =3D &sys_audio_vad.hw, + [CLKID_SYS_USB] =3D &sys_usb.hw, + [CLKID_SYS_SD_EMMC_A] =3D &sys_sd_emmc_a.hw, + [CLKID_SYS_SD_EMMC_C] =3D &sys_sd_emmc_c.hw, + [CLKID_SYS_PWM_AB] =3D &sys_pwm_ab.hw, + [CLKID_SYS_PWM_CD] =3D &sys_pwm_cd.hw, + [CLKID_SYS_PWM_EF] =3D &sys_pwm_ef.hw, + [CLKID_SYS_PWM_GH] =3D &sys_pwm_gh.hw, + [CLKID_SYS_SPICC_1] =3D &sys_spicc_1.hw, + [CLKID_SYS_SPICC_0] =3D &sys_spicc_0.hw, + [CLKID_SYS_UART_A] =3D &sys_uart_a.hw, + [CLKID_SYS_UART_B] =3D &sys_uart_b.hw, + [CLKID_SYS_UART_C] =3D &sys_uart_c.hw, + [CLKID_SYS_UART_D] =3D &sys_uart_d.hw, + [CLKID_SYS_UART_E] =3D &sys_uart_e.hw, + [CLKID_SYS_I2C_M_A] =3D &sys_i2c_m_a.hw, + [CLKID_SYS_I2C_M_B] =3D &sys_i2c_m_b.hw, + [CLKID_SYS_I2C_M_C] =3D &sys_i2c_m_c.hw, + [CLKID_SYS_I2C_M_D] =3D &sys_i2c_m_d.hw, + [CLKID_SYS_RTC] =3D &sys_rtc.hw, + [CLKID_AXI_AUDIO_VAD] =3D &axi_audio_vad.hw, + [CLKID_AXI_AUDIO_TOP] =3D &axi_audio_top.hw, + [CLKID_AXI_SYS_NIC] =3D &axi_sys_nic.hw, + [CLKID_AXI_RAMB] =3D &axi_ramb.hw, + [CLKID_AXI_RAMA] =3D &axi_rama.hw, + [CLKID_AXI_CPU_DMC] =3D &axi_cpu_dmc.hw, + [CLKID_AXI_NNA] =3D &axi_nna.hw, + [CLKID_AXI_DEV1_DMC] =3D &axi_dev1_dmc.hw, + [CLKID_AXI_DEV0_DMC] =3D &axi_dev0_dmc.hw, + [CLKID_AXI_DSP_DMC] =3D &axi_dsp_dmc.hw, + [CLKID_12_24M_IN] =3D &clk_12_24m_in.hw, + [CLKID_12M_24M] =3D &clk_12_24m.hw, + [CLKID_FCLK_25M_DIV] =3D &fclk_25m_div.hw, + [CLKID_FCLK_25M] =3D &fclk_25m.hw, + [CLKID_GEN_SEL] =3D &gen_sel.hw, + [CLKID_GEN_DIV] =3D &gen_div.hw, + [CLKID_GEN] =3D &gen.hw, + [CLKID_SARADC_SEL] =3D &saradc_sel.hw, + [CLKID_SARADC_DIV] =3D &saradc_div.hw, + [CLKID_SARADC] =3D &saradc.hw, + [CLKID_PWM_A_SEL] =3D &pwm_a_sel.hw, + [CLKID_PWM_A_DIV] =3D &pwm_a_div.hw, + [CLKID_PWM_A] =3D &pwm_a.hw, + [CLKID_PWM_B_SEL] =3D &pwm_b_sel.hw, + [CLKID_PWM_B_DIV] =3D &pwm_b_div.hw, + [CLKID_PWM_B] =3D &pwm_b.hw, + [CLKID_PWM_C_SEL] =3D &pwm_c_sel.hw, + [CLKID_PWM_C_DIV] =3D &pwm_c_div.hw, + [CLKID_PWM_C] =3D &pwm_c.hw, + [CLKID_PWM_D_SEL] =3D &pwm_d_sel.hw, + [CLKID_PWM_D_DIV] =3D &pwm_d_div.hw, + [CLKID_PWM_D] =3D &pwm_d.hw, + [CLKID_PWM_E_SEL] =3D &pwm_e_sel.hw, + [CLKID_PWM_E_DIV] =3D &pwm_e_div.hw, + [CLKID_PWM_E] =3D &pwm_e.hw, + [CLKID_PWM_F_SEL] =3D &pwm_f_sel.hw, + [CLKID_PWM_F_DIV] =3D &pwm_f_div.hw, + [CLKID_PWM_F] =3D &pwm_f.hw, + [CLKID_PWM_G_SEL] =3D &pwm_g_sel.hw, + [CLKID_PWM_G_DIV] =3D &pwm_g_div.hw, + [CLKID_PWM_G] =3D &pwm_g.hw, + [CLKID_PWM_H_SEL] =3D &pwm_h_sel.hw, + [CLKID_PWM_H_DIV] =3D &pwm_h_div.hw, + [CLKID_PWM_H] =3D &pwm_h.hw, + [CLKID_SPICC_0_SEL] =3D &spicc_0_sel.hw, + [CLKID_SPICC_0_DIV] =3D &spicc_0_div.hw, + [CLKID_SPICC_0] =3D &spicc_0.hw, + [CLKID_SPICC_1_SEL] =3D &spicc_1_sel.hw, + [CLKID_SPICC_1_DIV] =3D &spicc_1_div.hw, + [CLKID_SPICC_1] =3D &spicc_1.hw, + [CLKID_SD_EMMC_A_SEL] =3D &sd_emmc_a_sel.hw, + [CLKID_SD_EMMC_A_DIV] =3D &sd_emmc_a_div.hw, + [CLKID_SD_EMMC_A] =3D &sd_emmc_a.hw, + [CLKID_SD_EMMC_C_SEL] =3D &sd_emmc_c_sel.hw, + [CLKID_SD_EMMC_C_DIV] =3D &sd_emmc_c_div.hw, + [CLKID_SD_EMMC_C] =3D &sd_emmc_c.hw, + [CLKID_TS_DIV] =3D &ts_div.hw, + [CLKID_TS] =3D &ts.hw, + [CLKID_ETH_125M_DIV] =3D ð_125m_div.hw, + [CLKID_ETH_125M] =3D ð_125m.hw, + [CLKID_ETH_RMII_DIV] =3D ð_rmii_div.hw, + [CLKID_ETH_RMII] =3D ð_rmii.hw, + [CLKID_DSPA_0_SEL] =3D &dspa_0_sel.hw, + [CLKID_DSPA_0_DIV] =3D &dspa_0_div.hw, + [CLKID_DSPA_0] =3D &dspa_0.hw, + [CLKID_DSPA_1_SEL] =3D &dspa_1_sel.hw, + [CLKID_DSPA_1_DIV] =3D &dspa_1_div.hw, + [CLKID_DSPA_1] =3D &dspa_1.hw, + [CLKID_DSPA] =3D &dspa.hw, + [CLKID_NNA_CORE_SEL] =3D &nna_core_sel.hw, + [CLKID_NNA_CORE_DIV] =3D &nna_core_div.hw, + [CLKID_NNA_CORE] =3D &nna_core.hw, + [CLKID_NNA_AXI_SEL] =3D &nna_axi_sel.hw, + [CLKID_NNA_AXI_DIV] =3D &nna_axi_div.hw, + [CLKID_NNA_AXI] =3D &nna_axi.hw, +}; + +/* Convenience table to populate regmap in .probe */ +static struct clk_regmap *const a5_periphs_clk_regmaps[] =3D { + &rtc_xtal_clkin, + &rtc_32k_div, + &rtc_32k_mux, + &rtc_32k, + &rtc_clk, + &sys_reset_ctrl, + &sys_pwr_ctrl, + &sys_pad_ctrl, + &sys_ctrl, + &sys_ts_pll, + &sys_dev_arb, + &sys_mmc_pclk, + &sys_mailbox, + &sys_cpu_ctrl, + &sys_jtag_ctrl, + &sys_ir_ctrl, + &sys_irq_ctrl, + &sys_msr_clk, + &sys_rom, + &sys_cpu_apb, + &sys_rsa, + &sys_sar_adc, + &sys_startup, + &sys_secure, + &sys_spifc, + &sys_dspa, + &sys_nna, + &sys_eth_mac, + &sys_gic, + &sys_rama, + &sys_big_nic, + &sys_ramb, + &sys_audio_top, + &sys_audio_vad, + &sys_usb, + &sys_sd_emmc_a, + &sys_sd_emmc_c, + &sys_pwm_ab, + &sys_pwm_cd, + &sys_pwm_ef, + &sys_pwm_gh, + &sys_spicc_1, + &sys_spicc_0, + &sys_uart_a, + &sys_uart_b, + &sys_uart_c, + &sys_uart_d, + &sys_uart_e, + &sys_i2c_m_a, + &sys_i2c_m_b, + &sys_i2c_m_c, + &sys_i2c_m_d, + &sys_rtc, + &axi_audio_vad, + &axi_audio_top, + &axi_sys_nic, + &axi_ramb, + &axi_rama, + &axi_cpu_dmc, + &axi_nna, + &axi_dev1_dmc, + &axi_dev0_dmc, + &axi_dsp_dmc, + &clk_12_24m_in, + &clk_12_24m, + &fclk_25m_div, + &fclk_25m, + &gen_sel, + &gen_div, + &gen, + &saradc_sel, + &saradc_div, + &saradc, + &pwm_a_sel, + &pwm_a_div, + &pwm_a, + &pwm_b_sel, + &pwm_b_div, + &pwm_b, + &pwm_c_sel, + &pwm_c_div, + &pwm_c, + &pwm_d_sel, + &pwm_d_div, + &pwm_d, + &pwm_e_sel, + &pwm_e_div, + &pwm_e, + &pwm_f_sel, + &pwm_f_div, + &pwm_f, + &pwm_g_sel, + &pwm_g_div, + &pwm_g, + &pwm_h_sel, + &pwm_h_div, + &pwm_h, + &spicc_0_sel, + &spicc_0_div, + &spicc_0, + &spicc_1_sel, + &spicc_1_div, + &spicc_1, + &sd_emmc_a_sel, + &sd_emmc_a_div, + &sd_emmc_a, + &sd_emmc_c_sel, + &sd_emmc_c_div, + &sd_emmc_c, + &ts_div, + &ts, + ð_125m, + ð_rmii_div, + ð_rmii, + &dspa_0_sel, + &dspa_0_div, + &dspa_0, + &dspa_1_sel, + &dspa_1_div, + &dspa_1, + &dspa, + &nna_core_sel, + &nna_core_div, + &nna_core, + &nna_axi_sel, + &nna_axi_div, + &nna_axi +}; + +static const struct regmap_config clkc_regmap_config =3D { + .reg_bits =3D 32, + .val_bits =3D 32, + .reg_stride =3D 4, + .max_register =3D CLKCTRL_NNA_CLK_CNTL, +}; + +static struct meson_clk_hw_data a5_periphs_clks =3D { + .hws =3D a5_periphs_hw_clks, + .num =3D ARRAY_SIZE(a5_periphs_hw_clks), +}; + +static int aml_a5_peripherals_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct regmap *regmap; + void __iomem *base; + int clkid, ret, i; + + base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + regmap =3D devm_regmap_init_mmio(dev, base, &clkc_regmap_config); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + /* Populate regmap for the regmap backed clocks */ + for (i =3D 0; i < ARRAY_SIZE(a5_periphs_clk_regmaps); i++) + a5_periphs_clk_regmaps[i]->map =3D regmap; + + for (clkid =3D 0; clkid < a5_periphs_clks.num; clkid++) { + /* array might be sparse */ + if (!a5_periphs_clks.hws[clkid]) + continue; + + ret =3D devm_clk_hw_register(dev, a5_periphs_clks.hws[clkid]); + if (ret) { + dev_err(dev, "Clock registration failed\n"); + return ret; + } + } + + return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, + &a5_periphs_clks); +} + +static const struct of_device_id a5_peripherals_clkc_match_table[] =3D { + { + .compatible =3D "amlogic,a5-peripherals-clkc", + }, + { /* sentinel */ } +}; + +MODULE_DEVICE_TABLE(of, a5_peripherals_clkc_match_table); + +static struct platform_driver a5_peripherals_driver =3D { + .probe =3D aml_a5_peripherals_probe, + .driver =3D { + .name =3D "a5-peripherals-clkc", + .of_match_table =3D a5_peripherals_clkc_match_table, + }, +}; +module_platform_driver(a5_peripherals_driver); + +MODULE_DESCRIPTION("Amlogic A5 Peripherals Clock Controller driver"); +MODULE_AUTHOR("Chuan Liu "); +MODULE_LICENSE("GPL"); --=20 2.37.1