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charset="utf-8" The am625 is capable of running at 1.4 GHz when VDD_CORE is increased from 0.75V to 0.85V. Here we add a 1.4 GHz node to the a53_opp_table and increase the VDD_CORE voltage accordingly. Signed-off-by: Garrett Giordano --- arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi b/arch/arm64/b= oot/dts/ti/k3-am62-phycore-som.dtsi index ac8959f3d953..8acbd4facf37 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi @@ -205,6 +205,13 @@ AM62X_IOPAD(0x01f4, PIN_INPUT, 0) /* (D16) EXTINTn */ }; }; =20 +&a53_opp_table { + opp-1400000000 { + opp-hz =3D /bits/ 64 <1400000000>; + opp-supported-hw =3D <0x01 0x0004>; + }; +}; + &mcu_m4fss { mboxes =3D <&mailbox0_cluster0 &mbox_m4_0>; memory-region =3D <&mcu_m4fss_dma_memory_region>, @@ -265,8 +272,8 @@ pmic@30 { regulators { vdd_core: buck1 { regulator-name =3D "VDD_CORE"; - regulator-min-microvolt =3D <750000>; - regulator-max-microvolt =3D <750000>; + regulator-min-microvolt =3D <850000>; + regulator-max-microvolt =3D <850000>; regulator-boot-on; regulator-always-on; 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b=Pqs7hYDT5Aid4aN57Cl0gPIlO8FFxc7iuHmwufILhAN0WTrrUIc9ozSU81LDkCxfFH2bIo6P8M5WNi+3sKQ7Puf6W0HUCYNO0HtH+HsAcI916jgZ4fbt5iO9QnrYdDt3Nie7VvYrnXpzwaslF8hwiZtiWtifwXKyL1an2ZSBlCc= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=phytec.com; Received: from SJ2PR22MB4354.namprd22.prod.outlook.com (2603:10b6:a03:537::8) by MW6PR22MB4151.namprd22.prod.outlook.com (2603:10b6:303:249::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7962.18; Fri, 13 Sep 2024 17:56:54 +0000 Received: from SJ2PR22MB4354.namprd22.prod.outlook.com ([fe80::789c:e41e:1367:383d]) by SJ2PR22MB4354.namprd22.prod.outlook.com ([fe80::789c:e41e:1367:383d%5]) with mapi id 15.20.7962.016; Fri, 13 Sep 2024 17:56:53 +0000 From: Garrett Giordano To: nm@ti.com, vigneshr@ti.com, kristo@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, w.egorov@phytec.de Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, upstream@lists.phytec.de Subject: [PATCH 2/2] arm64: dts: ti: Remove k3-am625-phyboard-lyra-1-4-ghz-opp overlay Date: Fri, 13 Sep 2024 10:56:25 -0700 Message-Id: <20240913175625.3190757-3-ggiordano@phytec.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240913175625.3190757-1-ggiordano@phytec.com> References: <20240913175625.3190757-1-ggiordano@phytec.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: CH2PR07CA0038.namprd07.prod.outlook.com (2603:10b6:610:5b::12) To SJ2PR22MB4354.namprd22.prod.outlook.com (2603:10b6:a03:537::8) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ2PR22MB4354:EE_|MW6PR22MB4151:EE_ X-MS-Office365-Filtering-Correlation-Id: 869b92f3-efbc-4a80-e0db-08dcd41d735c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|52116014|376014|7416014|1800799024|366016|38350700014; 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charset="utf-8" Remove the k3-am625-phyboard-lyra-1-4-ghz-opp overlay. We now configure the a53_opp_table to include a 1.4 GHz node and set our VDD_CORE to 0.85v in the k3-am62-phycore-som.dtsi. This change is to match our PMIC which is now set to output 0.85v by default. Signed-off-by: Garrett Giordano --- .../k3-am625-phyboard-lyra-1-4-ghz-opp.dtso | 20 ------------------- 1 file changed, 20 deletions(-) delete mode 100644 arch/arm64/boot/dts/ti/k3-am625-phyboard-lyra-1-4-ghz-o= pp.dtso diff --git a/arch/arm64/boot/dts/ti/k3-am625-phyboard-lyra-1-4-ghz-opp.dtso= b/arch/arm64/boot/dts/ti/k3-am625-phyboard-lyra-1-4-ghz-opp.dtso deleted file mode 100644 index 6ec6d57ec49c..000000000000 --- a/arch/arm64/boot/dts/ti/k3-am625-phyboard-lyra-1-4-ghz-opp.dtso +++ /dev/null @@ -1,20 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only OR MIT -/* - * Copyright (C) 2024 PHYTEC America LLC - * Author: Nathan Morrisson - */ - -/dts-v1/; -/plugin/; - -&vdd_core { - regulator-min-microvolt =3D <850000>; - regulator-max-microvolt =3D <850000>; -}; - -&a53_opp_table { - opp-1400000000 { - opp-hz =3D /bits/ 64 <1400000000>; - opp-supported-hw =3D <0x01 0x0004>; - }; -}; --=20 2.25.1