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Peter Anvin" , Sean Christopherson , Paolo Bonzini , Pawan Gupta , Josh Poimboeuf , Jim Mattson , Sandipan Das , Kai Huang , x86@kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: Venkatesh Srinivas Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" AMD's initial implementation of IBPB did not clear the return address predictor. Beginning with Zen4, AMD's IBPB *does* clear the return address predictor. This behavior is enumerated by CPUID.80000008H:EBX.IBPB_RET[bit 30]. Define X86_FEATURE_AMD_IBPB_RET for use in KVM_GET_SUPPORTED_CPUID, when determining cross-vendor capabilities. Suggested-by: Venkatesh Srinivas Signed-off-by: Jim Mattson --- arch/x86/include/asm/cpufeatures.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpuf= eatures.h index cabd6b58e8ec..a222a24677d7 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -215,7 +215,7 @@ #define X86_FEATURE_SPEC_STORE_BYPASS_DISABLE ( 7*32+23) /* Disable Specul= ative Store Bypass. */ #define X86_FEATURE_LS_CFG_SSBD ( 7*32+24) /* AMD SSBD implementation vi= a LS_CFG MSR */ #define X86_FEATURE_IBRS ( 7*32+25) /* "ibrs" Indirect Branch Restricted = Speculation */ -#define X86_FEATURE_IBPB ( 7*32+26) /* "ibpb" Indirect Branch Prediction = Barrier without RSB flush */ +#define X86_FEATURE_IBPB ( 7*32+26) /* "ibpb" Indirect Branch Prediction = Barrier without a guaranteed RSB flush */ #define X86_FEATURE_STIBP ( 7*32+27) /* "stibp" Single Thread Indirect Br= anch Predictors */ #define X86_FEATURE_ZEN ( 7*32+28) /* Generic flag for all Zen and newer= */ #define X86_FEATURE_L1TF_PTEINV ( 7*32+29) /* L1TF workaround PTE inversi= on */ @@ -348,6 +348,7 @@ #define X86_FEATURE_CPPC (13*32+27) /* "cppc" Collaborative Processor Per= formance Control */ #define X86_FEATURE_AMD_PSFD (13*32+28) /* Predictive Store For= warding Disable */ #define X86_FEATURE_BTC_NO (13*32+29) /* Not vulnerable to Branch Type Co= nfusion */ +#define X86_FEATURE_AMD_IBPB_RET (13*32+30) /* IBPB clears return address = predictor */ #define X86_FEATURE_BRS (13*32+31) /* "brs" Branch Sampling available */ =20 /* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 1= 4 */ --=20 2.46.0.662.g92d0881bb0-goog From nobody Fri Nov 29 23:35:23 2024 Received: from mail-yw1-f201.google.com (mail-yw1-f201.google.com [209.85.128.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6C9EF126C01 for ; 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Fri, 13 Sep 2024 10:32:54 -0700 (PDT) Date: Fri, 13 Sep 2024 10:32:28 -0700 In-Reply-To: <20240913173242.3271406-1-jmattson@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240913173242.3271406-1-jmattson@google.com> X-Mailer: git-send-email 2.46.0.662.g92d0881bb0-goog Message-ID: <20240913173242.3271406-3-jmattson@google.com> Subject: [PATCH v4 2/3] KVM: x86: Advertise AMD_IBPB_RET to userspace From: Jim Mattson To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Sean Christopherson , Paolo Bonzini , Pawan Gupta , Josh Poimboeuf , Jim Mattson , Sandipan Das , Kai Huang , x86@kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: Tom Lendacky Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This is an inherent feature of IA32_PRED_CMD[0], so it is trivially virtualizable (as long as IA32_PRED_CMD[0] is virtualized). Suggested-by: Tom Lendacky Signed-off-by: Jim Mattson --- arch/x86/kvm/cpuid.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index 2617be544480..ec7b2ca3b4d3 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -751,7 +751,7 @@ void kvm_set_cpu_caps(void) F(CLZERO) | F(XSAVEERPTR) | F(WBNOINVD) | F(AMD_IBPB) | F(AMD_IBRS) | F(AMD_SSBD) | F(VIRT_SSBD) | F(AMD_SSB_NO) | F(AMD_STIBP) | F(AMD_STIBP_ALWAYS_ON) | - F(AMD_PSFD) + F(AMD_PSFD) | F(AMD_IBPB_RET) ); =20 /* --=20 2.46.0.662.g92d0881bb0-goog From nobody Fri Nov 29 23:35:23 2024 Received: from mail-yw1-f201.google.com (mail-yw1-f201.google.com [209.85.128.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 312C812BF25 for ; Fri, 13 Sep 2024 17:32:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726248778; cv=none; b=k1Htre5uqYpFT3X1YYut2xThOLE4tZU/VWf/9bzRQVurTVzOR5MgYObNaL74k91IFvA81areCMpiGAjnwxheb935ONgnMffBMx3S7mp6PjiY/tCLpawmJ5IGgcQec4X40qHqSau4xFfUHy54+tcklHn1A9uDi+1M2gI5O7GoyEo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726248778; c=relaxed/simple; bh=INXEGqBpdqXknfmZSD/sh52qeMFtGxNFla/jPofoHTg=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=DvgIHlHzDC+RhoehBcGOlnO/NKH15teQ5zsoIPWsPCkQrIgIgEpxpgN5/q0CJHrXK1TLYn/qXStv2n75JG3XJabECvfoTLVZV9chQTDNfaIFZF9UBtJtvOqlMuIOc5z28GSKslurPKI1fTpxTWy231jjZ0uRT4XbmkPDhPKg4zc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--jmattson.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=EWXdHCXk; arc=none smtp.client-ip=209.85.128.201 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--jmattson.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="EWXdHCXk" Received: by mail-yw1-f201.google.com with SMTP id 00721157ae682-6d470831e3aso26242977b3.3 for ; Fri, 13 Sep 2024 10:32:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1726248776; x=1726853576; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=g8wmRU1VBjftYUbE8QWox2vZgYnjmK1j3kpaMosk3/s=; b=EWXdHCXkW5znDv/JsjN+fX1/Z4mNgAAtnYKHXtG89ipLjOi7hBfN2uXR/mzFm2eDXQ pWgrgC6xggoKHw0qWlODXUbdCQWR4AtjWhu2HueD0x0CR6J2aHEF2Iq8A39wI86EzZYu rnMXdgNt5bDlEajhf8ZT4Ef5LkcITZPM39eYnwFarhMfvXJddPpwMek7GsRBlRIslO/t H16+fYdUmb2W3k+VZmKArqlOUxIF72aZvid8+HufUBZlOpULgd6Znb7a/TMHY6BzZQKF Besp3n6+VdZozN9jR4rQJ0IYpeRV/blP5lhDUhMnPtiVHlNyoiQOYiJQMQdN4sUF27Av nKdw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726248776; x=1726853576; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=g8wmRU1VBjftYUbE8QWox2vZgYnjmK1j3kpaMosk3/s=; b=i1Cr/g6XwyH6LqsYtCBBNeR9vWdW786BxyfHHV4Kx3Xplg9CWhr5x3NVMYGklLwzUE M9zzV0Fi9/KWzO1LLmfX6L1FrxrVTgUZja6vq/gevXTfU6oRDuRlNM5+SgtjR54G2J0p dViIdc4hZrgq3cuIA2dfyhshRFE+gyMg0efOVv3skSnSdIoW2EBGTY4CCKVWP05UNIKt 0rWUOs1GL2FBu5tksSV5ReA9c/gbwEfSPXOqJ30Xpg9Fv4tgL0HVFgVUlehCd9UDj2mo Fs6mHZTYabuCcFXoLpY284y2GDoO+I9CB93apQKxnhIK+aEymOw0Jj92iuugyZjf4fbf kaCg== X-Forwarded-Encrypted: i=1; AJvYcCWTFhWxSBoctlkUUNRliOtPIBxfK62/hVH3QMnwUhn4wTZ2TSFVa2hAdZpA2CmYesw20xfrNyaU4MUJXOI=@vger.kernel.org X-Gm-Message-State: AOJu0YzPu1C70i9LS5ONi3Yk4qNeezYBYRcbQLDFvtdxPZuCWhxVVkMI 2Q2W8yNHmRNETRD85uv9seuQEZ2d1NWhY0DPVNSLXVgNmc+BuDLbFJVVpHsThaBzzOibLKaDDO6 dxx9bbsyBAg== X-Google-Smtp-Source: AGHT+IGSFsTgCDbNetbXcYx95b1Niemc1TyU+mUuvVsCWCrCX6LdU1NXur64D5AtqnSZJbSSZ+54bB9edgoiUg== X-Received: from loggerhead.c.googlers.com ([fda3:e722:ac3:cc00:f3:525d:ac13:60e1]) (user=jmattson job=sendgmr) by 2002:a25:b2a4:0:b0:e11:5807:1072 with SMTP id 3f1490d57ef6-e1db00f2edemr4504276.8.1726248776127; Fri, 13 Sep 2024 10:32:56 -0700 (PDT) Date: Fri, 13 Sep 2024 10:32:29 -0700 In-Reply-To: <20240913173242.3271406-1-jmattson@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240913173242.3271406-1-jmattson@google.com> X-Mailer: git-send-email 2.46.0.662.g92d0881bb0-goog Message-ID: <20240913173242.3271406-4-jmattson@google.com> Subject: [PATCH v4 3/3] KVM: x86: AMD's IBPB is not equivalent to Intel's IBPB From: Jim Mattson To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Sean Christopherson , Paolo Bonzini , Pawan Gupta , Josh Poimboeuf , Jim Mattson , Sandipan Das , Kai Huang , x86@kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: Venkatesh Srinivas Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From Intel's documention [1], "CPUID.(EAX=3D07H,ECX=3D0):EDX[26] enumerates support for indirect branch restricted speculation (IBRS) and the indirect branch predictor barrier (IBPB)." Further, from [2], "Software that executed before the IBPB command cannot control the predicted targets of indirect branches (4) executed after the command on the same logical processor," where footnote 4 reads, "Note that indirect branches include near call indirect, near jump indirect and near return instructions. Because it includes near returns, it follows that **RSB entries created before an IBPB command cannot control the predicted targets of returns executed after the command on the same logical processor.**" [emphasis mine] On the other hand, AMD's IBPB "may not prevent return branch predictions from being specified by pre-IBPB branch targets" [3]. However, some AMD processors have an "enhanced IBPB" [terminology mine] which does clear the return address predictor. This feature is enumerated by CPUID.80000008:EDX.IBPB_RET[bit 30] [4]. Adjust the cross-vendor features enumerated by KVM_GET_SUPPORTED_CPUID accordingly. [1] https://www.intel.com/content/www/us/en/developer/articles/technical/so= ftware-security-guidance/technical-documentation/cpuid-enumeration-and-arch= itectural-msrs.html [2] https://www.intel.com/content/www/us/en/developer/articles/technical/so= ftware-security-guidance/technical-documentation/speculative-execution-side= -channel-mitigations.html#Footnotes [3] https://www.amd.com/en/resources/product-security/bulletin/amd-sb-1040.= html [4] https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/pr= ogrammer-references/24594.pdf Fixes: 0c54914d0c52 ("KVM: x86: use Intel speculation bugs and features as = derived in generic x86 code") Suggested-by: Venkatesh Srinivas Signed-off-by: Jim Mattson --- arch/x86/kvm/cpuid.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index ec7b2ca3b4d3..600d79ea22be 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -690,7 +690,9 @@ void kvm_set_cpu_caps(void) kvm_cpu_cap_set(X86_FEATURE_TSC_ADJUST); kvm_cpu_cap_set(X86_FEATURE_ARCH_CAPABILITIES); =20 - if (boot_cpu_has(X86_FEATURE_IBPB) && boot_cpu_has(X86_FEATURE_IBRS)) + if (boot_cpu_has(X86_FEATURE_AMD_IBPB_RET) && + boot_cpu_has(X86_FEATURE_AMD_IBPB) && + boot_cpu_has(X86_FEATURE_AMD_IBRS)) kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL); if (boot_cpu_has(X86_FEATURE_STIBP)) kvm_cpu_cap_set(X86_FEATURE_INTEL_STIBP); @@ -759,8 +761,12 @@ void kvm_set_cpu_caps(void) * arch/x86/kernel/cpu/bugs.c is kind enough to * record that in cpufeatures so use them. */ - if (boot_cpu_has(X86_FEATURE_IBPB)) + if (boot_cpu_has(X86_FEATURE_IBPB)) { kvm_cpu_cap_set(X86_FEATURE_AMD_IBPB); + if (boot_cpu_has(X86_FEATURE_SPEC_CTRL) && + !boot_cpu_has_bug(X86_BUG_EIBRS_PBRSB)) + kvm_cpu_cap_set(X86_FEATURE_AMD_IBPB_RET); + } if (boot_cpu_has(X86_FEATURE_IBRS)) kvm_cpu_cap_set(X86_FEATURE_AMD_IBRS); if (boot_cpu_has(X86_FEATURE_STIBP)) --=20 2.46.0.662.g92d0881bb0-goog