From nobody Sat Nov 30 01:00:51 2024 Received: from mx1.sberdevices.ru (mx1.sberdevices.ru [37.18.73.165]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 44F071DA61F; Fri, 13 Sep 2024 12:14:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=37.18.73.165 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726229647; cv=none; b=mmbA8rt75jHKmoxwYwaSnYTylw1dEKxrSIjpWFJf+IX1LdUooXRyLhAzDZxcFqr8D9MOsnVVb3G20mCfKI72WB2HmlI9y9drreZaraMlBvTd69Mo3WTIN1iG+Wx1lnPMeD6yeCB5Cxhwq54V+vQf7wBeTPTNGVvWqbHOwbkFFg8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726229647; c=relaxed/simple; bh=7CuqfBP/27/r7OJDJK9qkeWYOpYfeDymAalIYlW0/6A=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=PPl8VQt2O4IrM8QqlTfa69N7XILP/iiWENil87gV+Db7deZcpDgooqzM6Y4HK79v0fxqcCfU+aJE3VUeCbW8DCZBxVBxOfPw4Hz+ggJ24dCvKtwsIfcG/k4RZzQ81Tep8WCtwUBLYM0oU4z6DgNqOpLjdpvVBWy7zRwQ3l7OOr0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=salutedevices.com; spf=pass smtp.mailfrom=sberdevices.ru; dkim=pass (2048-bit key) header.d=salutedevices.com header.i=@salutedevices.com header.b=u88BGvsZ; arc=none smtp.client-ip=37.18.73.165 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=salutedevices.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sberdevices.ru Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=salutedevices.com header.i=@salutedevices.com header.b="u88BGvsZ" Received: from p-infra-ksmg-sc-msk01.sberdevices.ru (localhost [127.0.0.1]) by mx1.sberdevices.ru (Postfix) with ESMTP id A405C10002C; Fri, 13 Sep 2024 15:13:53 +0300 (MSK) DKIM-Filter: OpenDKIM Filter v2.11.0 mx1.sberdevices.ru A405C10002C DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=salutedevices.com; s=mail; t=1726229633; bh=rPQw2F08Uz4xjVSwdhVa7ZBFlR+M5A8/MM2JJ0d09Ek=; h=From:To:Subject:Date:Message-ID:MIME-Version:Content-Type:From; b=u88BGvsZ7TlnGfnkgrQDbRP/2ei9GK8oGlsIr8txKU2lwG6DWZIqLa8nycsYdqKlv JA5OZCpgR2k+jjwGkNRVT4/KVexp8+m+/NKvMk6R+876EWY95DHXyC4Q6obsHu76xD jKtWsm0DJcx2Z3s86Lo5/lBJWJ8ud0+DINqcV+KXACfSEEO55/90NFuj01d/F7NMih ZLGl2OvULDnnJd6plIrVKpDiq5bve3DKm+aHHdcriqfmUA6oGR9T6HotpjVbR1J9IL rnPFn4E5nFCM4229RSljye7r5EAopOU5Er5s246pm7E0cZZZEkMJcStK6oh+LIFw/2 VvVHuLMmJZG3g== Received: from smtp.sberdevices.ru (p-i-exch-sc-m01.sberdevices.ru [172.16.192.107]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.sberdevices.ru (Postfix) with ESMTPS; Fri, 13 Sep 2024 15:13:53 +0300 (MSK) From: Jan Dakinevich To: Jan Dakinevich , Conor Dooley , , Jerome Brunet , Kevin Hilman , "Krzysztof Kozlowski" , , , , , Martin Blumenstingl , Michael Turquette , Neil Armstrong , Philipp Zabel , Rob Herring , Stephen Boyd Subject: [RFC PATCH v4 1/5] reset: amlogic: add support for A1 SoC in auxiliary reset driver Date: Fri, 13 Sep 2024 15:11:48 +0300 Message-ID: <20240913121152.817575-2-jan.dakinevich@salutedevices.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240913121152.817575-1-jan.dakinevich@salutedevices.com> References: <20240913121152.817575-1-jan.dakinevich@salutedevices.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: p-i-exch-a-m1.sberdevices.ru (172.24.196.116) To p-i-exch-a-m1.sberdevices.ru (172.24.196.116) X-KSMG-Rule-ID: 10 X-KSMG-Message-Action: clean X-KSMG-AntiSpam-Lua-Profiles: 187732 [Sep 13 2024] X-KSMG-AntiSpam-Version: 6.1.1.5 X-KSMG-AntiSpam-Envelope-From: YVDakinevich@sberdevices.ru X-KSMG-AntiSpam-Rate: 0 X-KSMG-AntiSpam-Status: not_detected X-KSMG-AntiSpam-Method: none X-KSMG-AntiSpam-Auth: dkim=none X-KSMG-AntiSpam-Info: LuaCore: 34 0.3.34 8a1fac695d5606478feba790382a59668a4f0039, {Tracking_smtp_not_equal_from}, salutedevices.com:7.1.1;d41d8cd98f00b204e9800998ecf8427e.com:7.1.1;sberdevices.ru:7.1.1,5.0.1;127.0.0.199:7.1.2;smtp.sberdevices.ru:7.1.1,5.0.1, {Tracking_smtp_domain_mismatch}, {Tracking_smtp_domain_2level_mismatch}, {Tracking_sender_alignment_int}, {Tracking_white_helo}, FromAlignment: n X-MS-Exchange-Organization-SCL: -1 X-KSMG-AntiSpam-Interceptor-Info: scan successful X-KSMG-AntiPhishing: Clean X-KSMG-LinksScanning: Clean X-KSMG-AntiVirus: Kaspersky Secure Mail Gateway, version 2.0.1.6960, bases: 2024/09/13 11:43:00 #26577866 X-KSMG-AntiVirus-Status: Clean, skipped Content-Type: text/plain; charset="utf-8" Add support for the reset controller present in the audio clock controller of A1 SoC families, using the auxiliary bus. Signed-off-by: Jan Dakinevich --- drivers/reset/amlogic/reset-meson-aux.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/reset/amlogic/reset-meson-aux.c b/drivers/reset/amlogi= c/reset-meson-aux.c index dd8453001db9..a385c0125836 100644 --- a/drivers/reset/amlogic/reset-meson-aux.c +++ b/drivers/reset/amlogic/reset-meson-aux.c @@ -26,6 +26,12 @@ struct meson_reset_adev { #define to_meson_reset_adev(_adev) \ container_of((_adev), struct meson_reset_adev, adev) =20 +static const struct meson_reset_param meson_a1_audio_param =3D { + .reset_ops =3D &meson_reset_toggle_ops, + .reset_num =3D 32, + .level_offset =3D 0x28, +}; + static const struct meson_reset_param meson_g12a_audio_param =3D { .reset_ops =3D &meson_reset_toggle_ops, .reset_num =3D 26, @@ -40,6 +46,9 @@ static const struct meson_reset_param meson_sm1_audio_par= am =3D { =20 static const struct auxiliary_device_id meson_reset_aux_ids[] =3D { { + .name =3D "a1-audio-clkc.rst-a1", + .driver_data =3D (kernel_ulong_t)&meson_a1_audio_param, + }, { .name =3D "axg-audio-clkc.rst-g12a", .driver_data =3D (kernel_ulong_t)&meson_g12a_audio_param, }, { --=20 2.34.1 From nobody Sat Nov 30 01:00:51 2024 Received: from mx1.sberdevices.ru (mx2.sberdevices.ru [45.89.224.132]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6FC261DA0F5; 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Fri, 13 Sep 2024 15:13:53 +0300 (MSK) From: Jan Dakinevich To: Jan Dakinevich , Conor Dooley , , Jerome Brunet , Kevin Hilman , "Krzysztof Kozlowski" , , , , , Martin Blumenstingl , Michael Turquette , Neil Armstrong , Philipp Zabel , Rob Herring , Stephen Boyd Subject: [RFC PATCH v4 2/5] clk: meson: axg: share the set of audio helper macro Date: Fri, 13 Sep 2024 15:11:49 +0300 Message-ID: <20240913121152.817575-3-jan.dakinevich@salutedevices.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240913121152.817575-1-jan.dakinevich@salutedevices.com> References: <20240913121152.817575-1-jan.dakinevich@salutedevices.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: p-i-exch-a-m1.sberdevices.ru (172.24.196.116) To p-i-exch-a-m1.sberdevices.ru (172.24.196.116) X-KSMG-Rule-ID: 10 X-KSMG-Message-Action: clean X-KSMG-AntiSpam-Lua-Profiles: 187732 [Sep 13 2024] X-KSMG-AntiSpam-Version: 6.1.1.5 X-KSMG-AntiSpam-Envelope-From: YVDakinevich@sberdevices.ru X-KSMG-AntiSpam-Rate: 0 X-KSMG-AntiSpam-Status: not_detected X-KSMG-AntiSpam-Method: none X-KSMG-AntiSpam-Auth: dkim=none X-KSMG-AntiSpam-Info: LuaCore: 34 0.3.34 8a1fac695d5606478feba790382a59668a4f0039, {Tracking_smtp_not_equal_from}, sberdevices.ru:5.0.1,7.1.1;smtp.sberdevices.ru:5.0.1,7.1.1;salutedevices.com:7.1.1;127.0.0.199:7.1.2;d41d8cd98f00b204e9800998ecf8427e.com:7.1.1, {Tracking_smtp_domain_mismatch}, {Tracking_smtp_domain_2level_mismatch}, {Tracking_sender_alignment_int}, {Tracking_white_helo}, FromAlignment: n X-MS-Exchange-Organization-SCL: -1 X-KSMG-AntiSpam-Interceptor-Info: scan successful X-KSMG-AntiPhishing: Clean X-KSMG-LinksScanning: Clean X-KSMG-AntiVirus: Kaspersky Secure Mail Gateway, version 2.0.1.6960, bases: 2024/09/13 10:05:00 #26575345 X-KSMG-AntiVirus-Status: Clean, skipped Content-Type: text/plain; charset="utf-8" These macro will be used in upcoming audio clock controller for Meson A1 SoC. Signed-off-by: Jan Dakinevich --- drivers/clk/meson/axg-audio.c | 138 +----------------------------- drivers/clk/meson/meson-audio.h | 143 ++++++++++++++++++++++++++++++++ 2 files changed, 144 insertions(+), 137 deletions(-) create mode 100644 drivers/clk/meson/meson-audio.h diff --git a/drivers/clk/meson/axg-audio.c b/drivers/clk/meson/axg-audio.c index beda86349389..0d911e06a29f 100644 --- a/drivers/clk/meson/axg-audio.c +++ b/drivers/clk/meson/axg-audio.c @@ -16,6 +16,7 @@ #include =20 #include "meson-clkc-utils.h" +#include "meson-audio.h" #include "axg-audio.h" #include "clk-regmap.h" #include "clk-phase.h" @@ -23,52 +24,6 @@ =20 #include =20 -#define AUD_GATE(_name, _reg, _bit, _pname, _iflags) { \ - .data =3D &(struct clk_regmap_gate_data){ \ - .offset =3D (_reg), \ - .bit_idx =3D (_bit), \ - }, \ - .hw.init =3D &(struct clk_init_data) { \ - .name =3D "aud_"#_name, \ - .ops =3D &clk_regmap_gate_ops, \ - .parent_names =3D (const char *[]){ #_pname }, \ - .num_parents =3D 1, \ - .flags =3D CLK_DUTY_CYCLE_PARENT | (_iflags), \ - }, \ -} - -#define AUD_MUX(_name, _reg, _mask, _shift, _dflags, _pdata, _iflags) { \ - .data =3D &(struct clk_regmap_mux_data){ \ - .offset =3D (_reg), \ - .mask =3D (_mask), \ - .shift =3D (_shift), \ - .flags =3D (_dflags), \ - }, \ - .hw.init =3D &(struct clk_init_data){ \ - .name =3D "aud_"#_name, \ - .ops =3D &clk_regmap_mux_ops, \ - .parent_data =3D _pdata, \ - .num_parents =3D ARRAY_SIZE(_pdata), \ - .flags =3D CLK_DUTY_CYCLE_PARENT | (_iflags), \ - }, \ -} - -#define AUD_DIV(_name, _reg, _shift, _width, _dflags, _pname, _iflags) { \ - .data =3D &(struct clk_regmap_div_data){ \ - .offset =3D (_reg), \ - .shift =3D (_shift), \ - .width =3D (_width), \ - .flags =3D (_dflags), \ - }, \ - .hw.init =3D &(struct clk_init_data){ \ - .name =3D "aud_"#_name, \ - .ops =3D &clk_regmap_divider_ops, \ - .parent_names =3D (const char *[]){ #_pname }, \ - .num_parents =3D 1, \ - .flags =3D (_iflags), \ - }, \ -} - #define AUD_PCLK_GATE(_name, _reg, _bit) { \ .data =3D &(struct clk_regmap_gate_data){ \ .offset =3D (_reg), \ @@ -82,97 +37,6 @@ }, \ } =20 -#define AUD_SCLK_DIV(_name, _reg, _div_shift, _div_width, \ - _hi_shift, _hi_width, _pname, _iflags) { \ - .data =3D &(struct meson_sclk_div_data) { \ - .div =3D { \ - .reg_off =3D (_reg), \ - .shift =3D (_div_shift), \ - .width =3D (_div_width), \ - }, \ - .hi =3D { \ - .reg_off =3D (_reg), \ - .shift =3D (_hi_shift), \ - .width =3D (_hi_width), \ - }, \ - }, \ - .hw.init =3D &(struct clk_init_data) { \ - .name =3D "aud_"#_name, \ - .ops =3D &meson_sclk_div_ops, \ - .parent_names =3D (const char *[]){ #_pname }, \ - .num_parents =3D 1, \ - .flags =3D (_iflags), \ - }, \ -} - -#define AUD_TRIPHASE(_name, _reg, _width, _shift0, _shift1, _shift2, \ - _pname, _iflags) { \ - .data =3D &(struct meson_clk_triphase_data) { \ - .ph0 =3D { \ - .reg_off =3D (_reg), \ - .shift =3D (_shift0), \ - .width =3D (_width), \ - }, \ - .ph1 =3D { \ - .reg_off =3D (_reg), \ - .shift =3D (_shift1), \ - .width =3D (_width), \ - }, \ - .ph2 =3D { \ - .reg_off =3D (_reg), \ - .shift =3D (_shift2), \ - .width =3D (_width), \ - }, \ - }, \ - .hw.init =3D &(struct clk_init_data) { \ - .name =3D "aud_"#_name, \ - .ops =3D &meson_clk_triphase_ops, \ - .parent_names =3D (const char *[]){ #_pname }, \ - .num_parents =3D 1, \ - .flags =3D CLK_DUTY_CYCLE_PARENT | (_iflags), \ - }, \ -} - -#define AUD_PHASE(_name, _reg, _width, _shift, _pname, _iflags) { \ - .data =3D &(struct meson_clk_phase_data) { \ - .ph =3D { \ - .reg_off =3D (_reg), \ - .shift =3D (_shift), \ - .width =3D (_width), \ - }, \ - }, \ - .hw.init =3D &(struct clk_init_data) { \ - .name =3D "aud_"#_name, \ - .ops =3D &meson_clk_phase_ops, \ - .parent_names =3D (const char *[]){ #_pname }, \ - .num_parents =3D 1, \ - .flags =3D (_iflags), \ - }, \ -} - -#define AUD_SCLK_WS(_name, _reg, _width, _shift_ph, _shift_ws, _pname, \ - _iflags) { \ - .data =3D &(struct meson_sclk_ws_inv_data) { \ - .ph =3D { \ - .reg_off =3D (_reg), \ - .shift =3D (_shift_ph), \ - .width =3D (_width), \ - }, \ - .ws =3D { \ - .reg_off =3D (_reg), \ - .shift =3D (_shift_ws), \ - .width =3D (_width), \ - }, \ - }, \ - .hw.init =3D &(struct clk_init_data) { \ - .name =3D "aud_"#_name, \ - .ops =3D &meson_clk_phase_ops, \ - .parent_names =3D (const char *[]){ #_pname }, \ - .num_parents =3D 1, \ - .flags =3D (_iflags), \ - }, \ -} - /* Audio Master Clocks */ static const struct clk_parent_data mst_mux_parent_data[] =3D { { .fw_name =3D "mst_in0", }, diff --git a/drivers/clk/meson/meson-audio.h b/drivers/clk/meson/meson-audi= o.h new file mode 100644 index 000000000000..cbcdbd487d4a --- /dev/null +++ b/drivers/clk/meson/meson-audio.h @@ -0,0 +1,143 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ + +#ifndef __MESON_AUDIO_H__ +#define __MESON_AUDIO_H__ + +#define AUD_GATE(_name, _reg, _bit, _pname, _iflags) { \ + .data =3D &(struct clk_regmap_gate_data){ \ + .offset =3D (_reg), \ + .bit_idx =3D (_bit), \ + }, \ + .hw.init =3D &(struct clk_init_data) { \ + .name =3D "aud_"#_name, \ + .ops =3D &clk_regmap_gate_ops, \ + .parent_names =3D (const char *[]){ #_pname }, \ + .num_parents =3D 1, \ + .flags =3D CLK_DUTY_CYCLE_PARENT | (_iflags), \ + }, \ +} + +#define AUD_MUX(_name, _reg, _mask, _shift, _dflags, _pdata, _iflags) { \ + .data =3D &(struct clk_regmap_mux_data){ \ + .offset =3D (_reg), \ + .mask =3D (_mask), \ + .shift =3D (_shift), \ + .flags =3D (_dflags), \ + }, \ + .hw.init =3D &(struct clk_init_data){ \ + .name =3D "aud_"#_name, \ + .ops =3D &clk_regmap_mux_ops, \ + .parent_data =3D _pdata, \ + .num_parents =3D ARRAY_SIZE(_pdata), \ + .flags =3D CLK_DUTY_CYCLE_PARENT | (_iflags), \ + }, \ +} + +#define AUD_DIV(_name, _reg, _shift, _width, _dflags, _pname, _iflags) { \ + .data =3D &(struct clk_regmap_div_data){ \ + .offset =3D (_reg), \ + .shift =3D (_shift), \ + .width =3D (_width), \ + .flags =3D (_dflags), \ + }, \ + .hw.init =3D &(struct clk_init_data){ \ + .name =3D "aud_"#_name, \ + .ops =3D &clk_regmap_divider_ops, \ + .parent_names =3D (const char *[]){ #_pname }, \ + .num_parents =3D 1, \ + .flags =3D (_iflags), \ + }, \ +} + +#define AUD_SCLK_DIV(_name, _reg, _div_shift, _div_width, \ + _hi_shift, _hi_width, _pname, _iflags) { \ + .data =3D &(struct meson_sclk_div_data) { \ + .div =3D { \ + .reg_off =3D (_reg), \ + .shift =3D (_div_shift), \ + .width =3D (_div_width), \ + }, \ + .hi =3D { \ + .reg_off =3D (_reg), \ + .shift =3D (_hi_shift), \ + .width =3D (_hi_width), \ + }, \ + }, \ + .hw.init =3D &(struct clk_init_data) { \ + .name =3D "aud_"#_name, \ + .ops =3D &meson_sclk_div_ops, \ + .parent_names =3D (const char *[]){ #_pname }, \ + .num_parents =3D 1, \ + .flags =3D (_iflags), \ + }, \ +} + +#define AUD_TRIPHASE(_name, _reg, _width, _shift0, _shift1, _shift2, \ + _pname, _iflags) { \ + .data =3D &(struct meson_clk_triphase_data) { \ + .ph0 =3D { \ + .reg_off =3D (_reg), \ + .shift =3D (_shift0), \ + .width =3D (_width), \ + }, \ + .ph1 =3D { \ + .reg_off =3D (_reg), \ + .shift =3D (_shift1), \ + .width =3D (_width), \ + }, \ + .ph2 =3D { \ + .reg_off =3D (_reg), \ + .shift =3D (_shift2), \ + .width =3D (_width), \ + }, \ + }, \ + .hw.init =3D &(struct clk_init_data) { \ + .name =3D "aud_"#_name, \ + .ops =3D &meson_clk_triphase_ops, \ + .parent_names =3D (const char *[]){ #_pname }, \ + .num_parents =3D 1, \ + .flags =3D CLK_DUTY_CYCLE_PARENT | (_iflags), \ + }, \ +} + +#define AUD_PHASE(_name, _reg, _width, _shift, _pname, _iflags) { \ + .data =3D &(struct meson_clk_phase_data) { \ + .ph =3D { \ + .reg_off =3D (_reg), \ + .shift =3D (_shift), \ + .width =3D (_width), \ + }, \ + }, \ + .hw.init =3D &(struct clk_init_data) { \ + .name =3D "aud_"#_name, \ + .ops =3D &meson_clk_phase_ops, \ + .parent_names =3D (const char *[]){ #_pname }, \ + .num_parents =3D 1, \ + .flags =3D (_iflags), \ + }, \ +} + +#define AUD_SCLK_WS(_name, _reg, _width, _shift_ph, _shift_ws, _pname, \ + _iflags) { \ + .data =3D &(struct meson_sclk_ws_inv_data) { \ + .ph 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X-MS-Exchange-Organization-SCL: -1 X-KSMG-AntiSpam-Interceptor-Info: scan successful X-KSMG-AntiPhishing: Clean X-KSMG-LinksScanning: Clean X-KSMG-AntiVirus: Kaspersky Secure Mail Gateway, version 2.0.1.6960, bases: 2024/09/13 10:05:00 #26575345 X-KSMG-AntiVirus-Status: Clean, skipped Content-Type: text/plain; charset="utf-8" Add device tree bindings for A1 SoC audio clock and reset controllers. Signed-off-by: Jan Dakinevich Acked-by: Conor Dooley --- .../clock/amlogic,axg-audio-clkc.yaml | 3 + .../dt-bindings/clock/amlogic,a1-audio-clkc.h | 122 ++++++++++++++++++ .../reset/amlogic,meson-a1-audio-reset.h | 29 +++++ 3 files changed, 154 insertions(+) create mode 100644 include/dt-bindings/clock/amlogic,a1-audio-clkc.h create mode 100644 include/dt-bindings/reset/amlogic,meson-a1-audio-reset.h diff --git a/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc= .yaml b/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.yaml index fd7982dd4cea..df9eb8ce28dc 100644 --- a/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.yaml +++ b/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.yaml @@ -18,6 +18,8 @@ description: properties: compatible: enum: + - amlogic,a1-audio-clkc + - amlogic,a1-audio-vad-clkc - amlogic,axg-audio-clkc - amlogic,g12a-audio-clkc - amlogic,sm1-audio-clkc @@ -114,6 +116,7 @@ allOf: compatible: contains: enum: + - amlogic,a1-audio-clkc - amlogic,g12a-audio-clkc - amlogic,sm1-audio-clkc then: diff --git a/include/dt-bindings/clock/amlogic,a1-audio-clkc.h b/include/dt= -bindings/clock/amlogic,a1-audio-clkc.h new file mode 100644 index 000000000000..6534d1878816 --- /dev/null +++ b/include/dt-bindings/clock/amlogic,a1-audio-clkc.h @@ -0,0 +1,122 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Copyright (c) 2024, SaluteDevices. All Rights Reserved. + * + * Author: Jan Dakinevich + */ + +#ifndef __A1_AUDIO_CLKC_BINDINGS_H +#define __A1_AUDIO_CLKC_BINDINGS_H + +#define AUD_CLKID_DDR_ARB 1 +#define AUD_CLKID_TDMIN_A 2 +#define AUD_CLKID_TDMIN_B 3 +#define AUD_CLKID_TDMIN_LB 4 +#define AUD_CLKID_LOOPBACK 5 +#define AUD_CLKID_TDMOUT_A 6 +#define AUD_CLKID_TDMOUT_B 7 +#define AUD_CLKID_FRDDR_A 8 +#define AUD_CLKID_FRDDR_B 9 +#define AUD_CLKID_TODDR_A 10 +#define AUD_CLKID_TODDR_B 11 +#define AUD_CLKID_SPDIFIN 12 +#define AUD_CLKID_RESAMPLE 13 +#define AUD_CLKID_EQDRC 14 +#define AUD_CLKID_LOCKER 15 +#define AUD_CLKID_MST_A_MCLK_SEL 16 +#define AUD_CLKID_MST_A_MCLK_DIV 17 +#define AUD_CLKID_MST_A_MCLK 18 +#define AUD_CLKID_MST_B_MCLK_SEL 19 +#define AUD_CLKID_MST_B_MCLK_DIV 20 +#define AUD_CLKID_MST_B_MCLK 21 +#define AUD_CLKID_MST_C_MCLK_SEL 22 +#define AUD_CLKID_MST_C_MCLK_DIV 23 +#define AUD_CLKID_MST_C_MCLK 24 +#define AUD_CLKID_MST_D_MCLK_SEL 25 +#define AUD_CLKID_MST_D_MCLK_DIV 26 +#define AUD_CLKID_MST_D_MCLK 27 +#define AUD_CLKID_SPDIFIN_CLK_SEL 28 +#define AUD_CLKID_SPDIFIN_CLK_DIV 29 +#define AUD_CLKID_SPDIFIN_CLK 30 +#define AUD_CLKID_RESAMPLE_CLK_SEL 31 +#define AUD_CLKID_RESAMPLE_CLK_DIV 32 +#define AUD_CLKID_RESAMPLE_CLK 33 +#define AUD_CLKID_LOCKER_IN_CLK_SEL 34 +#define AUD_CLKID_LOCKER_IN_CLK_DIV 35 +#define AUD_CLKID_LOCKER_IN_CLK 36 +#define AUD_CLKID_LOCKER_OUT_CLK_SEL 37 +#define AUD_CLKID_LOCKER_OUT_CLK_DIV 38 +#define AUD_CLKID_LOCKER_OUT_CLK 39 +#define AUD_CLKID_EQDRC_CLK_SEL 40 +#define AUD_CLKID_EQDRC_CLK_DIV 41 +#define AUD_CLKID_EQDRC_CLK 42 +#define AUD_CLKID_MST_A_SCLK_PRE_EN 43 +#define AUD_CLKID_MST_A_SCLK_DIV 44 +#define AUD_CLKID_MST_A_SCLK_POST_EN 45 +#define AUD_CLKID_MST_A_SCLK 46 +#define AUD_CLKID_MST_B_SCLK_PRE_EN 47 +#define AUD_CLKID_MST_B_SCLK_DIV 48 +#define AUD_CLKID_MST_B_SCLK_POST_EN 49 +#define AUD_CLKID_MST_B_SCLK 50 +#define AUD_CLKID_MST_C_SCLK_PRE_EN 51 +#define AUD_CLKID_MST_C_SCLK_DIV 52 +#define AUD_CLKID_MST_C_SCLK_POST_EN 53 +#define AUD_CLKID_MST_C_SCLK 54 +#define AUD_CLKID_MST_D_SCLK_PRE_EN 55 +#define AUD_CLKID_MST_D_SCLK_DIV 56 +#define AUD_CLKID_MST_D_SCLK_POST_EN 57 +#define AUD_CLKID_MST_D_SCLK 58 +#define AUD_CLKID_MST_A_LRCLK_DIV 59 +#define AUD_CLKID_MST_A_LRCLK 60 +#define AUD_CLKID_MST_B_LRCLK_DIV 61 +#define AUD_CLKID_MST_B_LRCLK 62 +#define AUD_CLKID_MST_C_LRCLK_DIV 63 +#define AUD_CLKID_MST_C_LRCLK 64 +#define AUD_CLKID_MST_D_LRCLK_DIV 65 +#define AUD_CLKID_MST_D_LRCLK 66 +#define AUD_CLKID_TDMIN_A_SCLK_SEL 67 +#define AUD_CLKID_TDMIN_A_SCLK_PRE_EN 68 +#define AUD_CLKID_TDMIN_A_SCLK_POST_EN 69 +#define AUD_CLKID_TDMIN_A_SCLK 70 +#define AUD_CLKID_TDMIN_A_LRCLK 71 +#define AUD_CLKID_TDMIN_B_SCLK_SEL 72 +#define AUD_CLKID_TDMIN_B_SCLK_PRE_EN 73 +#define AUD_CLKID_TDMIN_B_SCLK_POST_EN 74 +#define AUD_CLKID_TDMIN_B_SCLK 75 +#define AUD_CLKID_TDMIN_B_LRCLK 76 +#define AUD_CLKID_TDMIN_LB_SCLK_SEL 77 +#define AUD_CLKID_TDMIN_LB_SCLK_PRE_EN 78 +#define AUD_CLKID_TDMIN_LB_SCLK_POST_EN 79 +#define AUD_CLKID_TDMIN_LB_SCLK 80 +#define AUD_CLKID_TDMIN_LB_LRCLK 81 +#define AUD_CLKID_TDMOUT_A_SCLK_SEL 82 +#define AUD_CLKID_TDMOUT_A_SCLK_PRE_EN 83 +#define AUD_CLKID_TDMOUT_A_SCLK_POST_EN 84 +#define AUD_CLKID_TDMOUT_A_SCLK 85 +#define AUD_CLKID_TDMOUT_A_LRCLK 86 +#define AUD_CLKID_TDMOUT_B_SCLK_SEL 87 +#define AUD_CLKID_TDMOUT_B_SCLK_PRE_EN 88 +#define AUD_CLKID_TDMOUT_B_SCLK_POST_EN 89 +#define AUD_CLKID_TDMOUT_B_SCLK 90 +#define AUD_CLKID_TDMOUT_B_LRCLK 91 + +#define AUD_CLKID_VAD_DDR_ARB 1 +#define AUD_CLKID_VAD_PDM 2 +#define AUD_CLKID_VAD_TDMIN 3 +#define AUD_CLKID_VAD_TODDR 4 +#define AUD_CLKID_VAD 5 +#define AUD_CLKID_VAD_AUDIOTOP 6 +#define AUD_CLKID_VAD_MCLK_SEL 7 +#define AUD_CLKID_VAD_MCLK_DIV 8 +#define AUD_CLKID_VAD_MCLK 9 +#define AUD_CLKID_VAD_CLK_SEL 10 +#define AUD_CLKID_VAD_CLK_DIV 11 +#define AUD_CLKID_VAD_CLK 12 +#define AUD_CLKID_VAD_PDM_DCLK_SEL 13 +#define AUD_CLKID_VAD_PDM_DCLK_DIV 14 +#define AUD_CLKID_VAD_PDM_DCLK 15 +#define AUD_CLKID_VAD_PDM_SYSCLK_SEL 16 +#define AUD_CLKID_VAD_PDM_SYSCLK_DIV 17 +#define AUD_CLKID_VAD_PDM_SYSCLK 18 + +#endif /* __A1_AUDIO_CLKC_BINDINGS_H */ diff --git a/include/dt-bindings/reset/amlogic,meson-a1-audio-reset.h b/inc= lude/dt-bindings/reset/amlogic,meson-a1-audio-reset.h new file mode 100644 index 000000000000..653fddba1d8f --- /dev/null +++ b/include/dt-bindings/reset/amlogic,meson-a1-audio-reset.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Copyright (c) 2024, SaluteDevices. All Rights Reserved. + * + * Author: Jan Dakinevich + */ + +#ifndef _DT_BINDINGS_AMLOGIC_MESON_A1_AUDIO_RESET_H +#define _DT_BINDINGS_AMLOGIC_MESON_A1_AUDIO_RESET_H + +#define AUD_RESET_DDRARB 0 +#define AUD_RESET_TDMIN_A 1 +#define AUD_RESET_TDMIN_B 2 +#define AUD_RESET_TDMIN_LB 3 +#define AUD_RESET_LOOPBACK 4 +#define AUD_RESET_TDMOUT_A 5 +#define AUD_RESET_TDMOUT_B 6 +#define AUD_RESET_FRDDR_A 7 +#define AUD_RESET_FRDDR_B 8 +#define AUD_RESET_TODDR_A 9 +#define AUD_RESET_TODDR_B 10 +#define AUD_RESET_SPDIFIN 11 +#define AUD_RESET_RESAMPLE 12 +#define AUD_RESET_EQDRC 13 +#define AUD_RESET_LOCKER 14 +#define AUD_RESET_TOACODEC 30 +#define AUD_RESET_CLKTREE 31 + +#endif /* _DT_BINDINGS_AMLOGIC_MESON_A1_AUDIO_RESET_H */ --=20 2.34.1 From nobody Sat Nov 30 01:00:51 2024 Received: from mx1.sberdevices.ru (mx2.sberdevices.ru [45.89.224.132]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4B70E1DA10B; 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Fri, 13 Sep 2024 15:13:54 +0300 (MSK) From: Jan Dakinevich To: Jan Dakinevich , Conor Dooley , , Jerome Brunet , Kevin Hilman , "Krzysztof Kozlowski" , , , , , Martin Blumenstingl , Michael Turquette , Neil Armstrong , Philipp Zabel , Rob Herring , Stephen Boyd Subject: [RFC PATCH v4 4/5] clk: meson: a1: add the audio clock controller driver Date: Fri, 13 Sep 2024 15:11:51 +0300 Message-ID: <20240913121152.817575-5-jan.dakinevich@salutedevices.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240913121152.817575-1-jan.dakinevich@salutedevices.com> References: <20240913121152.817575-1-jan.dakinevich@salutedevices.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: p-i-exch-a-m1.sberdevices.ru (172.24.196.116) To p-i-exch-a-m1.sberdevices.ru (172.24.196.116) X-KSMG-Rule-ID: 10 X-KSMG-Message-Action: clean X-KSMG-AntiSpam-Lua-Profiles: 187732 [Sep 13 2024] X-KSMG-AntiSpam-Version: 6.1.1.5 X-KSMG-AntiSpam-Envelope-From: YVDakinevich@sberdevices.ru X-KSMG-AntiSpam-Rate: 0 X-KSMG-AntiSpam-Status: not_detected X-KSMG-AntiSpam-Method: none X-KSMG-AntiSpam-Auth: dkim=none X-KSMG-AntiSpam-Info: LuaCore: 34 0.3.34 8a1fac695d5606478feba790382a59668a4f0039, {Tracking_smtp_not_equal_from}, smtp.sberdevices.ru:7.1.1,5.0.1;d41d8cd98f00b204e9800998ecf8427e.com:7.1.1;sberdevices.ru:7.1.1,5.0.1;127.0.0.199:7.1.2;salutedevices.com:7.1.1, {Tracking_smtp_domain_mismatch}, {Tracking_smtp_domain_2level_mismatch}, {Tracking_sender_alignment_int}, {Tracking_white_helo}, FromAlignment: n X-MS-Exchange-Organization-SCL: -1 X-KSMG-AntiSpam-Interceptor-Info: scan successful X-KSMG-AntiPhishing: Clean X-KSMG-LinksScanning: Clean X-KSMG-AntiVirus: Kaspersky Secure Mail Gateway, version 2.0.1.6960, bases: 2024/09/13 10:05:00 #26575345 X-KSMG-AntiVirus-Status: Clean, skipped Content-Type: text/plain; charset="utf-8" This controller provides clocks and reset functionality for audio peripherals on Amlogic A1 SoC family. The driver is almost identical to 'axg-audio', however it would be better to keep it separate due to following reasons: - significant amount of bits has another definition. I will bring there a mess of new defines with A1_ suffixes. - registers of this controller are located in two separate regions. It will give a lot of complications for 'axg-audio' to support this. Signed-off-by: Jan Dakinevich --- drivers/clk/meson/Kconfig | 14 + drivers/clk/meson/Makefile | 3 + drivers/clk/meson/a1-audio-clkc.c | 359 ++++++++++++++++++++++++++ drivers/clk/meson/a1-audio-drv.c | 104 ++++++++ drivers/clk/meson/a1-audio-vad-clkc.c | 85 ++++++ drivers/clk/meson/a1-audio.h | 131 ++++++++++ 6 files changed, 696 insertions(+) create mode 100644 drivers/clk/meson/a1-audio-clkc.c create mode 100644 drivers/clk/meson/a1-audio-drv.c create mode 100644 drivers/clk/meson/a1-audio-vad-clkc.c create mode 100644 drivers/clk/meson/a1-audio.h diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig index 78f648c9c97d..b558288a6b78 100644 --- a/drivers/clk/meson/Kconfig +++ b/drivers/clk/meson/Kconfig @@ -132,6 +132,20 @@ config COMMON_CLK_A1_PERIPHERALS device, A1 SoC Family. Say Y if you want A1 Peripherals clock controller to work. =20 +config COMMON_CLK_A1_AUDIO + tristate "Amlogic A1 SoC Audio clock controller support" + depends on ARM64 + select COMMON_CLK_MESON_REGMAP + select COMMON_CLK_MESON_PHASE + select COMMON_CLK_MESON_SCLK_DIV + select COMMON_CLK_MESON_CLKC_UTILS + select REGMAP_MMIO + imply RESET_MESON_AUX + help + Support for the Audio clock controller on Amlogic A113L based + device, A1 SoC Family. Say Y if you want A1 Audio clock controller + to work. + config COMMON_CLK_C3_PLL tristate "Amlogic C3 PLL clock controller" depends on ARM64 diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile index bc56a47931c1..f7ea11df1de3 100644 --- a/drivers/clk/meson/Makefile +++ b/drivers/clk/meson/Makefile @@ -16,10 +16,13 @@ obj-$(CONFIG_COMMON_CLK_MESON_VCLK) +=3D vclk.o =20 # Amlogic Clock controllers =20 +a1-audio-y :=3D a1-audio-drv.o a1-audio-clkc.o a1-audio-vad-clkc.o + obj-$(CONFIG_COMMON_CLK_AXG) +=3D axg.o axg-aoclk.o obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) +=3D axg-audio.o obj-$(CONFIG_COMMON_CLK_A1_PLL) +=3D a1-pll.o obj-$(CONFIG_COMMON_CLK_A1_PERIPHERALS) +=3D a1-peripherals.o +obj-$(CONFIG_COMMON_CLK_A1_AUDIO) +=3D a1-audio.o obj-$(CONFIG_COMMON_CLK_C3_PLL) +=3D c3-pll.o obj-$(CONFIG_COMMON_CLK_C3_PERIPHERALS) +=3D c3-peripherals.o obj-$(CONFIG_COMMON_CLK_GXBB) +=3D gxbb.o gxbb-aoclk.o diff --git a/drivers/clk/meson/a1-audio-clkc.c b/drivers/clk/meson/a1-audio= -clkc.c new file mode 100644 index 000000000000..48160dcb7f47 --- /dev/null +++ b/drivers/clk/meson/a1-audio-clkc.c @@ -0,0 +1,359 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (c) 2024, SaluteDevices. All Rights Reserved. + * + * Author: Jan Dakinevich + */ + +#include + +#include "a1-audio.h" + +#define AUDIO_CLK_GATE_EN0 0x000 +#define AUDIO_MCLK_A_CTRL 0x008 +#define AUDIO_MCLK_B_CTRL 0x00c +#define AUDIO_MCLK_C_CTRL 0x010 +#define AUDIO_MCLK_D_CTRL 0x014 +#define AUDIO_MCLK_E_CTRL 0x018 +#define AUDIO_MCLK_F_CTRL 0x01c +#define AUDIO_SW_RESET0 0x028 +#define AUDIO_MST_A_SCLK_CTRL0 0x040 +#define AUDIO_MST_A_SCLK_CTRL1 0x044 +#define AUDIO_MST_B_SCLK_CTRL0 0x048 +#define AUDIO_MST_B_SCLK_CTRL1 0x04c +#define AUDIO_MST_C_SCLK_CTRL0 0x050 +#define AUDIO_MST_C_SCLK_CTRL1 0x054 +#define AUDIO_MST_D_SCLK_CTRL0 0x058 +#define AUDIO_MST_D_SCLK_CTRL1 0x05c +#define AUDIO_CLK_TDMIN_A_CTRL 0x080 +#define AUDIO_CLK_TDMIN_B_CTRL 0x084 +#define AUDIO_CLK_TDMIN_LB_CTRL 0x08c +#define AUDIO_CLK_TDMOUT_A_CTRL 0x090 +#define AUDIO_CLK_TDMOUT_B_CTRL 0x094 +#define AUDIO_CLK_SPDIFIN_CTRL 0x09c +#define AUDIO_CLK_RESAMPLE_CTRL 0x0a4 +#define AUDIO_CLK_LOCKER_CTRL 0x0a8 +#define AUDIO_CLK_EQDRC_CTRL 0x0c0 + +struct clk_regmap aud_ddr_arb =3D + AUD_PCLK_GATE(ddr_arb, AUDIO_CLK_GATE_EN0, 0); +struct clk_regmap aud_tdmin_a =3D + AUD_PCLK_GATE(tdmin_a, AUDIO_CLK_GATE_EN0, 1); +struct clk_regmap aud_tdmin_b =3D + AUD_PCLK_GATE(tdmin_b, AUDIO_CLK_GATE_EN0, 2); +struct clk_regmap aud_tdmin_lb =3D + AUD_PCLK_GATE(tdmin_lb, AUDIO_CLK_GATE_EN0, 3); +struct clk_regmap aud_loopback =3D + AUD_PCLK_GATE(loopback, AUDIO_CLK_GATE_EN0, 4); +struct clk_regmap aud_tdmout_a =3D + AUD_PCLK_GATE(tdmout_a, AUDIO_CLK_GATE_EN0, 5); +struct clk_regmap aud_tdmout_b =3D + AUD_PCLK_GATE(tdmout_b, AUDIO_CLK_GATE_EN0, 6); +struct clk_regmap aud_frddr_a =3D + AUD_PCLK_GATE(frddr_a, AUDIO_CLK_GATE_EN0, 7); +struct clk_regmap aud_frddr_b =3D + AUD_PCLK_GATE(frddr_b, AUDIO_CLK_GATE_EN0, 8); +struct clk_regmap aud_toddr_a =3D + AUD_PCLK_GATE(toddr_a, AUDIO_CLK_GATE_EN0, 9); +struct clk_regmap aud_toddr_b =3D + AUD_PCLK_GATE(toddr_b, AUDIO_CLK_GATE_EN0, 10); +struct clk_regmap aud_spdifin =3D + AUD_PCLK_GATE(spdifin, AUDIO_CLK_GATE_EN0, 11); +struct clk_regmap aud_resample =3D + AUD_PCLK_GATE(resample, AUDIO_CLK_GATE_EN0, 12); +struct clk_regmap aud_eqdrc =3D + AUD_PCLK_GATE(eqdrc, AUDIO_CLK_GATE_EN0, 13); +struct clk_regmap aud_audiolocker =3D + AUD_PCLK_GATE(audiolocker, AUDIO_CLK_GATE_EN0, 14); + +struct clk_regmap aud_mst_a_mclk_sel =3D + AUD_MST_MCLK_MUX(mst_a_mclk, AUDIO_MCLK_A_CTRL); +struct clk_regmap aud_mst_a_mclk_div =3D + AUD_MST_MCLK_DIV(mst_a_mclk, AUDIO_MCLK_A_CTRL); +struct clk_regmap aud_mst_a_mclk =3D + AUD_MST_MCLK_GATE(mst_a_mclk, AUDIO_MCLK_A_CTRL); + +struct clk_regmap aud_mst_b_mclk_sel =3D + AUD_MST_MCLK_MUX(mst_b_mclk, AUDIO_MCLK_B_CTRL); +struct clk_regmap aud_mst_b_mclk_div =3D + AUD_MST_MCLK_DIV(mst_b_mclk, AUDIO_MCLK_B_CTRL); +struct clk_regmap aud_mst_b_mclk =3D + AUD_MST_MCLK_GATE(mst_b_mclk, AUDIO_MCLK_B_CTRL); + +struct clk_regmap aud_mst_c_mclk_sel =3D + AUD_MST_MCLK_MUX(mst_c_mclk, AUDIO_MCLK_C_CTRL); +struct clk_regmap aud_mst_c_mclk_div =3D + AUD_MST_MCLK_DIV(mst_c_mclk, AUDIO_MCLK_C_CTRL); +struct clk_regmap aud_mst_c_mclk =3D + AUD_MST_MCLK_GATE(mst_c_mclk, AUDIO_MCLK_C_CTRL); + +struct clk_regmap aud_mst_d_mclk_sel =3D + AUD_MST_MCLK_MUX(mst_d_mclk, AUDIO_MCLK_D_CTRL); +struct clk_regmap aud_mst_d_mclk_div =3D + AUD_MST_MCLK_DIV(mst_d_mclk, AUDIO_MCLK_D_CTRL); +struct clk_regmap aud_mst_d_mclk =3D + AUD_MST_MCLK_GATE(mst_d_mclk, AUDIO_MCLK_D_CTRL); + +struct clk_regmap aud_spdifin_clk_sel =3D + AUD_MST_MCLK_MUX(spdifin_clk, AUDIO_CLK_SPDIFIN_CTRL); +struct clk_regmap aud_spdifin_clk_div =3D + AUD_MST_MCLK_DIV(spdifin_clk, AUDIO_CLK_SPDIFIN_CTRL); +struct clk_regmap aud_spdifin_clk =3D + AUD_MST_MCLK_GATE(spdifin_clk, AUDIO_CLK_SPDIFIN_CTRL); + +struct clk_regmap aud_eqdrc_clk_sel =3D + AUD_MST_MCLK_MUX(eqdrc_clk, AUDIO_CLK_EQDRC_CTRL); +struct clk_regmap aud_eqdrc_clk_div =3D + AUD_MST_MCLK_DIV(eqdrc_clk, AUDIO_CLK_EQDRC_CTRL); +struct clk_regmap aud_eqdrc_clk =3D + AUD_MST_MCLK_GATE(eqdrc_clk, AUDIO_CLK_EQDRC_CTRL); + +struct clk_regmap aud_resample_clk_sel =3D + AUD_MUX(resample_clk_sel, AUDIO_CLK_RESAMPLE_CTRL, 0xf, 24, + CLK_MUX_ROUND_CLOSEST, AUD_MST_MCLK_PDATA, 0); +struct clk_regmap aud_resample_clk_div =3D + AUD_DIV(resample_clk_div, AUDIO_CLK_RESAMPLE_CTRL, 0, 8, + CLK_DIVIDER_ROUND_CLOSEST, aud_resample_clk_sel, + CLK_SET_RATE_PARENT); +struct clk_regmap aud_resample_clk =3D + AUD_GATE(resample_clk, AUDIO_CLK_RESAMPLE_CTRL, 31, + aud_resample_clk_div, CLK_SET_RATE_PARENT); + +struct clk_regmap aud_locker_in_clk_sel =3D + AUD_MUX(locker_in_clk_sel, AUDIO_CLK_LOCKER_CTRL, 0xf, 8, + CLK_MUX_ROUND_CLOSEST, AUD_MST_MCLK_PDATA, 0); +struct clk_regmap aud_locker_in_clk_div =3D + AUD_DIV(locker_in_clk_div, AUDIO_CLK_LOCKER_CTRL, 0, 8, + CLK_DIVIDER_ROUND_CLOSEST, aud_locker_in_clk_sel, + CLK_SET_RATE_PARENT); +struct clk_regmap aud_locker_in_clk =3D + AUD_GATE(locker_in_clk, AUDIO_CLK_LOCKER_CTRL, 15, + aud_locker_in_clk_div, CLK_SET_RATE_PARENT); + +struct clk_regmap aud_locker_out_clk_sel =3D + AUD_MUX(locker_out_clk_sel, AUDIO_CLK_LOCKER_CTRL, 0xf, 24, + CLK_MUX_ROUND_CLOSEST, AUD_MST_MCLK_PDATA, 0); +struct clk_regmap aud_locker_out_clk_div =3D + AUD_DIV(locker_out_clk_div, AUDIO_CLK_LOCKER_CTRL, 16, 8, + CLK_DIVIDER_ROUND_CLOSEST, aud_locker_out_clk_sel, + CLK_SET_RATE_PARENT); +struct clk_regmap aud_locker_out_clk =3D + AUD_GATE(locker_out_clk, AUDIO_CLK_LOCKER_CTRL, 31, + aud_locker_out_clk_div, CLK_SET_RATE_PARENT); + +struct clk_regmap aud_mst_a_sclk_pre_en =3D + AUD_MST_SCLK_PRE_EN(mst_a_sclk, AUDIO_MST_A_SCLK_CTRL0, mst_a_mclk); +struct clk_regmap aud_mst_a_sclk_div =3D + AUD_MST_SCLK_DIV(mst_a_sclk, AUDIO_MST_A_SCLK_CTRL0); +struct clk_regmap aud_mst_a_sclk_post_en =3D + AUD_MST_SCLK_POST_EN(mst_a_sclk, AUDIO_MST_A_SCLK_CTRL0); +struct clk_regmap aud_mst_a_sclk =3D + AUD_MST_SCLK(mst_a_sclk, AUDIO_MST_A_SCLK_CTRL1); + +struct clk_regmap aud_mst_b_sclk_pre_en =3D + AUD_MST_SCLK_PRE_EN(mst_b_sclk, AUDIO_MST_B_SCLK_CTRL0, mst_b_mclk); +struct clk_regmap aud_mst_b_sclk_div =3D + AUD_MST_SCLK_DIV(mst_b_sclk, AUDIO_MST_B_SCLK_CTRL0); +struct clk_regmap aud_mst_b_sclk_post_en =3D + AUD_MST_SCLK_POST_EN(mst_b_sclk, AUDIO_MST_B_SCLK_CTRL0); +struct clk_regmap aud_mst_b_sclk =3D + AUD_MST_SCLK(mst_b_sclk, AUDIO_MST_B_SCLK_CTRL1); + +struct clk_regmap aud_mst_c_sclk_pre_en =3D + AUD_MST_SCLK_PRE_EN(mst_c_sclk, AUDIO_MST_C_SCLK_CTRL0, mst_c_mclk); +struct clk_regmap aud_mst_c_sclk_div =3D + AUD_MST_SCLK_DIV(mst_c_sclk, AUDIO_MST_C_SCLK_CTRL0); +struct clk_regmap aud_mst_c_sclk_post_en =3D + AUD_MST_SCLK_POST_EN(mst_c_sclk, AUDIO_MST_C_SCLK_CTRL0); +struct clk_regmap aud_mst_c_sclk =3D + AUD_MST_SCLK(mst_c_sclk, AUDIO_MST_C_SCLK_CTRL1); + +struct clk_regmap aud_mst_d_sclk_pre_en =3D + AUD_MST_SCLK_PRE_EN(mst_d_sclk, AUDIO_MST_D_SCLK_CTRL0, mst_d_mclk); +struct clk_regmap aud_mst_d_sclk_div =3D + AUD_MST_SCLK_DIV(mst_d_sclk, AUDIO_MST_D_SCLK_CTRL0); +struct clk_regmap aud_mst_d_sclk_post_en =3D + AUD_MST_SCLK_POST_EN(mst_d_sclk, AUDIO_MST_D_SCLK_CTRL0); +struct clk_regmap aud_mst_d_sclk =3D + AUD_MST_SCLK(mst_d_sclk, AUDIO_MST_D_SCLK_CTRL1); + +struct clk_regmap aud_mst_a_lrclk_div =3D + AUD_MST_LRCLK_DIV(mst_a_lrclk, AUDIO_MST_A_SCLK_CTRL0, + mst_a_sclk_post_en); +struct clk_regmap aud_mst_a_lrclk =3D + AUD_MST_LRCLK(mst_a_lrclk, AUDIO_MST_A_SCLK_CTRL1); + +struct clk_regmap aud_mst_b_lrclk_div =3D + AUD_MST_LRCLK_DIV(mst_b_lrclk, AUDIO_MST_B_SCLK_CTRL0, + mst_b_sclk_post_en); +struct clk_regmap aud_mst_b_lrclk =3D + AUD_MST_LRCLK(mst_b_lrclk, AUDIO_MST_B_SCLK_CTRL1); + +struct clk_regmap aud_mst_c_lrclk_div =3D + AUD_MST_LRCLK_DIV(mst_c_lrclk, AUDIO_MST_C_SCLK_CTRL0, + mst_c_sclk_post_en); +struct clk_regmap aud_mst_c_lrclk =3D + AUD_MST_LRCLK(mst_c_lrclk, AUDIO_MST_C_SCLK_CTRL1); + +struct clk_regmap aud_mst_d_lrclk_div =3D + AUD_MST_LRCLK_DIV(mst_d_lrclk, AUDIO_MST_D_SCLK_CTRL0, + mst_d_sclk_post_en); +struct clk_regmap aud_mst_d_lrclk =3D + AUD_MST_LRCLK(mst_d_lrclk, AUDIO_MST_D_SCLK_CTRL1); + +struct clk_regmap aud_tdmin_a_sclk_sel =3D + AUD_TDM_SCLK_MUX(tdmin_a_sclk, AUDIO_CLK_TDMIN_A_CTRL); +struct clk_regmap aud_tdmin_a_sclk_pre_en =3D + AUD_TDM_SCLK_PRE_EN(tdmin_a_sclk, AUDIO_CLK_TDMIN_A_CTRL); +struct clk_regmap aud_tdmin_a_sclk_post_en =3D + AUD_TDM_SCLK_POST_EN(tdmin_a_sclk, AUDIO_CLK_TDMIN_A_CTRL); +struct clk_regmap aud_tdmin_a_sclk =3D + AUD_TDM_SCLK_WS(tdmin_a_sclk, AUDIO_CLK_TDMIN_A_CTRL); +struct clk_regmap aud_tdmin_a_lrclk =3D + AUD_TDM_LRLCK(tdmin_a_lrclk, AUDIO_CLK_TDMIN_A_CTRL); + +struct clk_regmap aud_tdmin_b_sclk_sel =3D + AUD_TDM_SCLK_MUX(tdmin_b_sclk, AUDIO_CLK_TDMIN_B_CTRL); +struct clk_regmap aud_tdmin_b_sclk_pre_en =3D + AUD_TDM_SCLK_PRE_EN(tdmin_b_sclk, AUDIO_CLK_TDMIN_B_CTRL); +struct clk_regmap aud_tdmin_b_sclk_post_en =3D + AUD_TDM_SCLK_POST_EN(tdmin_b_sclk, AUDIO_CLK_TDMIN_B_CTRL); +struct clk_regmap aud_tdmin_b_sclk =3D + AUD_TDM_SCLK_WS(tdmin_b_sclk, AUDIO_CLK_TDMIN_B_CTRL); +struct clk_regmap aud_tdmin_b_lrclk =3D + AUD_TDM_LRLCK(tdmin_b_lrclk, AUDIO_CLK_TDMIN_B_CTRL); + +struct clk_regmap aud_tdmin_lb_sclk_sel =3D + AUD_TDM_SCLK_MUX(tdmin_lb_sclk, AUDIO_CLK_TDMIN_LB_CTRL); +struct clk_regmap aud_tdmin_lb_sclk_pre_en =3D + AUD_TDM_SCLK_PRE_EN(tdmin_lb_sclk, AUDIO_CLK_TDMIN_LB_CTRL); +struct clk_regmap aud_tdmin_lb_sclk_post_en =3D + AUD_TDM_SCLK_POST_EN(tdmin_lb_sclk, AUDIO_CLK_TDMIN_LB_CTRL); +struct clk_regmap aud_tdmin_lb_sclk =3D + AUD_TDM_SCLK_WS(tdmin_lb_sclk, AUDIO_CLK_TDMIN_LB_CTRL); +struct clk_regmap aud_tdmin_lb_lrclk =3D + AUD_TDM_LRLCK(tdmin_lb_lrclk, AUDIO_CLK_TDMIN_LB_CTRL); + +struct clk_regmap aud_tdmout_a_sclk_sel =3D + AUD_TDM_SCLK_MUX(tdmout_a_sclk, AUDIO_CLK_TDMOUT_A_CTRL); +struct clk_regmap aud_tdmout_a_sclk_pre_en =3D + AUD_TDM_SCLK_PRE_EN(tdmout_a_sclk, AUDIO_CLK_TDMOUT_A_CTRL); +struct clk_regmap aud_tdmout_a_sclk_post_en =3D + AUD_TDM_SCLK_POST_EN(tdmout_a_sclk, AUDIO_CLK_TDMOUT_A_CTRL); +struct clk_regmap aud_tdmout_a_sclk =3D + AUD_TDM_SCLK_WS(tdmout_a_sclk, AUDIO_CLK_TDMOUT_A_CTRL); +struct clk_regmap aud_tdmout_a_lrclk =3D + AUD_TDM_LRLCK(tdmout_a_lrclk, AUDIO_CLK_TDMOUT_A_CTRL); + +struct clk_regmap aud_tdmout_b_sclk_sel =3D + AUD_TDM_SCLK_MUX(tdmout_b_sclk, AUDIO_CLK_TDMOUT_B_CTRL); +struct clk_regmap aud_tdmout_b_sclk_pre_en =3D + AUD_TDM_SCLK_PRE_EN(tdmout_b_sclk, AUDIO_CLK_TDMOUT_B_CTRL); +struct clk_regmap aud_tdmout_b_sclk_post_en =3D + AUD_TDM_SCLK_POST_EN(tdmout_b_sclk, AUDIO_CLK_TDMOUT_B_CTRL); +struct clk_regmap aud_tdmout_b_sclk =3D + AUD_TDM_SCLK_WS(tdmout_b_sclk, AUDIO_CLK_TDMOUT_B_CTRL); +struct clk_regmap aud_tdmout_b_lrclk =3D + AUD_TDM_LRLCK(tdmout_b_lrclk, AUDIO_CLK_TDMOUT_B_CTRL); + +static struct clk_hw *a1_audio_clkc_hws[] =3D { + [AUD_CLKID_DDR_ARB] =3D &aud_ddr_arb.hw, + [AUD_CLKID_TDMIN_A] =3D &aud_tdmin_a.hw, + [AUD_CLKID_TDMIN_B] =3D &aud_tdmin_b.hw, + [AUD_CLKID_TDMIN_LB] =3D &aud_tdmin_lb.hw, + [AUD_CLKID_LOOPBACK] =3D &aud_loopback.hw, + [AUD_CLKID_TDMOUT_A] =3D &aud_tdmout_a.hw, + [AUD_CLKID_TDMOUT_B] =3D &aud_tdmout_b.hw, + [AUD_CLKID_FRDDR_A] =3D &aud_frddr_a.hw, + [AUD_CLKID_FRDDR_B] =3D &aud_frddr_b.hw, + [AUD_CLKID_TODDR_A] =3D &aud_toddr_a.hw, + [AUD_CLKID_TODDR_B] =3D &aud_toddr_b.hw, + [AUD_CLKID_SPDIFIN] =3D &aud_spdifin.hw, + [AUD_CLKID_RESAMPLE] =3D &aud_resample.hw, + [AUD_CLKID_EQDRC] =3D &aud_eqdrc.hw, + [AUD_CLKID_LOCKER] =3D &aud_audiolocker.hw, + [AUD_CLKID_MST_A_MCLK_SEL] =3D &aud_mst_a_mclk_sel.hw, + [AUD_CLKID_MST_A_MCLK_DIV] =3D &aud_mst_a_mclk_div.hw, + [AUD_CLKID_MST_A_MCLK] =3D &aud_mst_a_mclk.hw, + [AUD_CLKID_MST_B_MCLK_SEL] =3D &aud_mst_b_mclk_sel.hw, + [AUD_CLKID_MST_B_MCLK_DIV] =3D &aud_mst_b_mclk_div.hw, + [AUD_CLKID_MST_B_MCLK] =3D &aud_mst_b_mclk.hw, + [AUD_CLKID_MST_C_MCLK_SEL] =3D &aud_mst_c_mclk_sel.hw, + [AUD_CLKID_MST_C_MCLK_DIV] =3D &aud_mst_c_mclk_div.hw, + [AUD_CLKID_MST_C_MCLK] =3D &aud_mst_c_mclk.hw, + [AUD_CLKID_MST_D_MCLK_SEL] =3D &aud_mst_d_mclk_sel.hw, + [AUD_CLKID_MST_D_MCLK_DIV] =3D &aud_mst_d_mclk_div.hw, + [AUD_CLKID_MST_D_MCLK] =3D &aud_mst_d_mclk.hw, + [AUD_CLKID_RESAMPLE_CLK_SEL] =3D &aud_resample_clk_sel.hw, + [AUD_CLKID_RESAMPLE_CLK_DIV] =3D &aud_resample_clk_div.hw, + [AUD_CLKID_RESAMPLE_CLK] =3D &aud_resample_clk.hw, + [AUD_CLKID_LOCKER_IN_CLK_SEL] =3D &aud_locker_in_clk_sel.hw, + [AUD_CLKID_LOCKER_IN_CLK_DIV] =3D &aud_locker_in_clk_div.hw, + [AUD_CLKID_LOCKER_IN_CLK] =3D &aud_locker_in_clk.hw, + [AUD_CLKID_LOCKER_OUT_CLK_SEL] =3D &aud_locker_out_clk_sel.hw, + [AUD_CLKID_LOCKER_OUT_CLK_DIV] =3D &aud_locker_out_clk_div.hw, + [AUD_CLKID_LOCKER_OUT_CLK] =3D &aud_locker_out_clk.hw, + [AUD_CLKID_SPDIFIN_CLK_SEL] =3D &aud_spdifin_clk_sel.hw, + [AUD_CLKID_SPDIFIN_CLK_DIV] =3D &aud_spdifin_clk_div.hw, + [AUD_CLKID_SPDIFIN_CLK] =3D &aud_spdifin_clk.hw, + [AUD_CLKID_EQDRC_CLK_SEL] =3D &aud_eqdrc_clk_sel.hw, + [AUD_CLKID_EQDRC_CLK_DIV] =3D &aud_eqdrc_clk_div.hw, + [AUD_CLKID_EQDRC_CLK] =3D &aud_eqdrc_clk.hw, + [AUD_CLKID_MST_A_SCLK_PRE_EN] =3D &aud_mst_a_sclk_pre_en.hw, + [AUD_CLKID_MST_A_SCLK_DIV] =3D &aud_mst_a_sclk_div.hw, + [AUD_CLKID_MST_A_SCLK_POST_EN] =3D &aud_mst_a_sclk_post_en.hw, + [AUD_CLKID_MST_A_SCLK] =3D &aud_mst_a_sclk.hw, + [AUD_CLKID_MST_B_SCLK_PRE_EN] =3D &aud_mst_b_sclk_pre_en.hw, + [AUD_CLKID_MST_B_SCLK_DIV] =3D &aud_mst_b_sclk_div.hw, + [AUD_CLKID_MST_B_SCLK_POST_EN] =3D &aud_mst_b_sclk_post_en.hw, + [AUD_CLKID_MST_B_SCLK] =3D &aud_mst_b_sclk.hw, + [AUD_CLKID_MST_C_SCLK_PRE_EN] =3D &aud_mst_c_sclk_pre_en.hw, + [AUD_CLKID_MST_C_SCLK_DIV] =3D &aud_mst_c_sclk_div.hw, + [AUD_CLKID_MST_C_SCLK_POST_EN] =3D &aud_mst_c_sclk_post_en.hw, + [AUD_CLKID_MST_C_SCLK] =3D &aud_mst_c_sclk.hw, + [AUD_CLKID_MST_D_SCLK_PRE_EN] =3D &aud_mst_d_sclk_pre_en.hw, + [AUD_CLKID_MST_D_SCLK_DIV] =3D &aud_mst_d_sclk_div.hw, + [AUD_CLKID_MST_D_SCLK_POST_EN] =3D &aud_mst_d_sclk_post_en.hw, + [AUD_CLKID_MST_D_SCLK] =3D &aud_mst_d_sclk.hw, + [AUD_CLKID_MST_A_LRCLK_DIV] =3D &aud_mst_a_lrclk_div.hw, + [AUD_CLKID_MST_A_LRCLK] =3D &aud_mst_a_lrclk.hw, + [AUD_CLKID_MST_B_LRCLK_DIV] =3D &aud_mst_b_lrclk_div.hw, + [AUD_CLKID_MST_B_LRCLK] =3D &aud_mst_b_lrclk.hw, + [AUD_CLKID_MST_C_LRCLK_DIV] =3D &aud_mst_c_lrclk_div.hw, + [AUD_CLKID_MST_C_LRCLK] =3D &aud_mst_c_lrclk.hw, + [AUD_CLKID_MST_D_LRCLK_DIV] =3D &aud_mst_d_lrclk_div.hw, + [AUD_CLKID_MST_D_LRCLK] =3D &aud_mst_d_lrclk.hw, + [AUD_CLKID_TDMIN_A_SCLK_SEL] =3D &aud_tdmin_a_sclk_sel.hw, + [AUD_CLKID_TDMIN_A_SCLK_PRE_EN] =3D &aud_tdmin_a_sclk_pre_en.hw, + [AUD_CLKID_TDMIN_A_SCLK_POST_EN] =3D &aud_tdmin_a_sclk_post_en.hw, + [AUD_CLKID_TDMIN_A_SCLK] =3D &aud_tdmin_a_sclk.hw, + [AUD_CLKID_TDMIN_A_LRCLK] =3D &aud_tdmin_a_lrclk.hw, + [AUD_CLKID_TDMIN_B_SCLK_SEL] =3D &aud_tdmin_b_sclk_sel.hw, + [AUD_CLKID_TDMIN_B_SCLK_PRE_EN] =3D &aud_tdmin_b_sclk_pre_en.hw, + [AUD_CLKID_TDMIN_B_SCLK_POST_EN] =3D &aud_tdmin_b_sclk_post_en.hw, + [AUD_CLKID_TDMIN_B_SCLK] =3D &aud_tdmin_b_sclk.hw, + [AUD_CLKID_TDMIN_B_LRCLK] =3D &aud_tdmin_b_lrclk.hw, + [AUD_CLKID_TDMIN_LB_SCLK_SEL] =3D &aud_tdmin_lb_sclk_sel.hw, + [AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] =3D &aud_tdmin_lb_sclk_pre_en.hw, + [AUD_CLKID_TDMIN_LB_SCLK_POST_EN] =3D &aud_tdmin_lb_sclk_post_en.hw, + [AUD_CLKID_TDMIN_LB_SCLK] =3D &aud_tdmin_lb_sclk.hw, + [AUD_CLKID_TDMIN_LB_LRCLK] =3D &aud_tdmin_lb_lrclk.hw, + [AUD_CLKID_TDMOUT_A_SCLK_SEL] =3D &aud_tdmout_a_sclk_sel.hw, + [AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] =3D &aud_tdmout_a_sclk_pre_en.hw, + [AUD_CLKID_TDMOUT_A_SCLK_POST_EN] =3D &aud_tdmout_a_sclk_post_en.hw, + [AUD_CLKID_TDMOUT_A_SCLK] =3D &aud_tdmout_a_sclk.hw, + [AUD_CLKID_TDMOUT_A_LRCLK] =3D &aud_tdmout_a_lrclk.hw, + [AUD_CLKID_TDMOUT_B_SCLK_SEL] =3D &aud_tdmout_b_sclk_sel.hw, + [AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] =3D &aud_tdmout_b_sclk_pre_en.hw, + [AUD_CLKID_TDMOUT_B_SCLK_POST_EN] =3D &aud_tdmout_b_sclk_post_en.hw, + [AUD_CLKID_TDMOUT_B_SCLK] =3D &aud_tdmout_b_sclk.hw, + [AUD_CLKID_TDMOUT_B_LRCLK] =3D &aud_tdmout_b_lrclk.hw, +}; + +struct a1_audio_data a1_audio_clkc =3D { + .hw_clks =3D { + .hws =3D a1_audio_clkc_hws, + .num =3D ARRAY_SIZE(a1_audio_clkc_hws), + }, + .rst_drvname =3D "rst-a1", +}; diff --git a/drivers/clk/meson/a1-audio-drv.c b/drivers/clk/meson/a1-audio-= drv.c new file mode 100644 index 000000000000..879a9d7bed72 --- /dev/null +++ b/drivers/clk/meson/a1-audio-drv.c @@ -0,0 +1,104 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (c) 2024, SaluteDevices. All Rights Reserved. + * + * Author: Jan Dakinevich + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "a1-audio.h" + +static const struct regmap_config a1_audio_regmap_cfg =3D { + .reg_bits =3D 32, + .val_bits =3D 32, + .reg_stride =3D 4, +}; + +static int a1_audio_clkc_probe(struct platform_device *pdev) +{ + const struct a1_audio_data *data; + struct regmap *map; + void __iomem *base; + struct clk *clk; + unsigned int i; + int ret; + + data =3D device_get_match_data(&pdev->dev); + if (!data) + return -EINVAL; + + clk =3D devm_clk_get_enabled(&pdev->dev, "pclk"); + if (IS_ERR(clk)) + return PTR_ERR(clk); + + base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + map =3D devm_regmap_init_mmio(&pdev->dev, base, &a1_audio_regmap_cfg); + if (IS_ERR(map)) + return PTR_ERR(map); + + ret =3D device_reset(&pdev->dev); + if (ret) + return dev_err_probe(&pdev->dev, ret, "failed to reset device"); + + for (i =3D 0; i < data->hw_clks.num; i++) { + struct clk_hw *hw =3D data->hw_clks.hws[i]; + struct clk_regmap *clk_regmap =3D to_clk_regmap(hw); + + if (!hw) + continue; + + clk_regmap->map =3D map; + + ret =3D devm_clk_hw_register(&pdev->dev, hw); + if (ret) + return ret; + } + + ret =3D devm_of_clk_add_hw_provider(&pdev->dev, meson_clk_hw_get, + (void *)&data->hw_clks); + if (ret) + return ret; + + if (!data->rst_drvname) + return 0; + + return devm_meson_rst_aux_register(&pdev->dev, map, data->rst_drvname); +} + +static const struct of_device_id a1_audio_clkc_match_table[] =3D { + { + .compatible =3D "amlogic,a1-audio-clkc", + .data =3D &a1_audio_clkc, + }, + { + .compatible =3D "amlogic,a1-audio-vad-clkc", + .data =3D &a1_audio_vad_clkc, + }, + {} +}; +MODULE_DEVICE_TABLE(of, a1_audio_clkc_match_table); + +static struct platform_driver a1_audio_clkc_driver =3D { + .probe =3D a1_audio_clkc_probe, + .driver =3D { + .name =3D "a1-audio-clkc", + .of_match_table =3D a1_audio_clkc_match_table, + }, +}; +module_platform_driver(a1_audio_clkc_driver); + +MODULE_DESCRIPTION("Amlogic A1 Audio Clock driver"); +MODULE_AUTHOR("Jan Dakinevich "); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/meson/a1-audio-vad-clkc.c b/drivers/clk/meson/a1-a= udio-vad-clkc.c new file mode 100644 index 000000000000..0b1365d30ce1 --- /dev/null +++ b/drivers/clk/meson/a1-audio-vad-clkc.c @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (c) 2024, SaluteDevices. All Rights Reserved. + * + * Author: Jan Dakinevich + */ + +#include + +#include "a1-audio.h" + +#define AUDIO_VAD_CLK_GATE_EN0 0x00c +#define AUDIO_VAD_MCLK_CTRL 0x040 +#define AUDIO_VAD_CLK_CTRL 0x044 +#define AUDIO_VAD_CLK_PDMIN_CTRL0 0x058 +#define AUDIO_CLK_VAD_PDMIN_CTRL1 0x05c + +struct clk_regmap aud_vad_ddr_arb =3D + AUD_PCLK_GATE(vad_ddr_arb, AUDIO_VAD_CLK_GATE_EN0, 0); +struct clk_regmap aud_vad_pdm =3D + AUD_PCLK_GATE(vad_pdm, AUDIO_VAD_CLK_GATE_EN0, 1); +struct clk_regmap aud_vad_tdmin_vad =3D + AUD_PCLK_GATE(vad_tdmin_vad, AUDIO_VAD_CLK_GATE_EN0, 2); +struct clk_regmap aud_vad_toddr_vad =3D + AUD_PCLK_GATE(vad_toddr_vad, AUDIO_VAD_CLK_GATE_EN0, 3); +struct clk_regmap aud_vad =3D + AUD_PCLK_GATE(vad, AUDIO_VAD_CLK_GATE_EN0, 4); +struct clk_regmap aud_vad_audiotop =3D + AUD_PCLK_GATE(vad_audiotop, AUDIO_VAD_CLK_GATE_EN0, 7); + +struct clk_regmap aud_vad_mclk_sel =3D + AUD_MST_MCLK_MUX(vad_mclk, AUDIO_VAD_MCLK_CTRL); +struct clk_regmap aud_vad_mclk_div =3D + AUD_MST_MCLK_DIV(vad_mclk, AUDIO_VAD_MCLK_CTRL); +struct clk_regmap aud_vad_mclk =3D + AUD_MST_MCLK_GATE(vad_mclk, AUDIO_VAD_MCLK_CTRL); + +struct clk_regmap aud_vad_clk_sel =3D + AUD_MST_MCLK_MUX(vad_clk, AUDIO_VAD_CLK_CTRL); +struct clk_regmap aud_vad_clk_div =3D + AUD_MST_MCLK_DIV(vad_clk, AUDIO_VAD_CLK_CTRL); +struct clk_regmap aud_vad_clk =3D + AUD_MST_MCLK_GATE(vad_clk, AUDIO_VAD_CLK_CTRL); + +struct clk_regmap aud_vad_pdm_dclk_sel =3D + AUD_MST_MCLK_MUX(vad_pdm_dclk, AUDIO_VAD_CLK_PDMIN_CTRL0); +struct clk_regmap aud_vad_pdm_dclk_div =3D + AUD_MST_MCLK_DIV(vad_pdm_dclk, AUDIO_VAD_CLK_PDMIN_CTRL0); +struct clk_regmap aud_vad_pdm_dclk =3D + AUD_MST_MCLK_GATE(vad_pdm_dclk, AUDIO_VAD_CLK_PDMIN_CTRL0); + +struct clk_regmap aud_vad_pdm_sysclk_sel =3D + AUD_MST_MCLK_MUX(vad_pdm_sysclk, AUDIO_CLK_VAD_PDMIN_CTRL1); +struct clk_regmap aud_vad_pdm_sysclk_div =3D + AUD_MST_MCLK_DIV(vad_pdm_sysclk, AUDIO_CLK_VAD_PDMIN_CTRL1); +struct clk_regmap aud_vad_pdm_sysclk =3D + AUD_MST_MCLK_GATE(vad_pdm_sysclk, AUDIO_CLK_VAD_PDMIN_CTRL1); + +static struct clk_hw *a1_audio_vad_clkc_hws[] =3D { + [AUD_CLKID_VAD_DDR_ARB] =3D &aud_vad_ddr_arb.hw, + [AUD_CLKID_VAD_PDM] =3D &aud_vad_pdm.hw, + [AUD_CLKID_VAD_TDMIN] =3D &aud_vad_tdmin_vad.hw, + [AUD_CLKID_VAD_TODDR] =3D &aud_vad_toddr_vad.hw, + [AUD_CLKID_VAD] =3D &aud_vad.hw, + [AUD_CLKID_VAD_AUDIOTOP] =3D &aud_vad_audiotop.hw, + [AUD_CLKID_VAD_MCLK_SEL] =3D &aud_vad_mclk_sel.hw, + [AUD_CLKID_VAD_MCLK_DIV] =3D &aud_vad_mclk_div.hw, + [AUD_CLKID_VAD_MCLK] =3D &aud_vad_mclk.hw, + [AUD_CLKID_VAD_CLK_SEL] =3D &aud_vad_clk_sel.hw, + [AUD_CLKID_VAD_CLK_DIV] =3D &aud_vad_clk_div.hw, + [AUD_CLKID_VAD_CLK] =3D &aud_vad_clk.hw, + [AUD_CLKID_VAD_PDM_DCLK_SEL] =3D &aud_vad_pdm_dclk_sel.hw, + [AUD_CLKID_VAD_PDM_DCLK_DIV] =3D &aud_vad_pdm_dclk_div.hw, + [AUD_CLKID_VAD_PDM_DCLK] =3D &aud_vad_pdm_dclk.hw, + [AUD_CLKID_VAD_PDM_SYSCLK_SEL] =3D &aud_vad_pdm_sysclk_sel.hw, + [AUD_CLKID_VAD_PDM_SYSCLK_DIV] =3D &aud_vad_pdm_sysclk_div.hw, + [AUD_CLKID_VAD_PDM_SYSCLK] =3D &aud_vad_pdm_sysclk.hw, +}; + +struct a1_audio_data a1_audio_vad_clkc =3D { + .hw_clks =3D { + .hws =3D a1_audio_vad_clkc_hws, + .num =3D ARRAY_SIZE(a1_audio_vad_clkc_hws), + }, +}; diff --git a/drivers/clk/meson/a1-audio.h b/drivers/clk/meson/a1-audio.h new file mode 100644 index 000000000000..ecd0b1ea4aea --- /dev/null +++ b/drivers/clk/meson/a1-audio.h @@ -0,0 +1,131 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Copyright (c) 2024, SaluteDevices. All Rights Reserved. + * + * Author: Jan Dakinevich + */ + +#ifndef __MESON_CLK_A1_AUDIO_H +#define __MESON_CLK_A1_AUDIO_H + +#include "clk-phase.h" +#include "clk-regmap.h" +#include "meson-audio.h" +#include "meson-clkc-utils.h" +#include "sclk-div.h" + +#define AUD_PCLK_GATE(_name, _reg, _bit) { \ + .data =3D &(struct clk_regmap_gate_data){ \ + .offset =3D (_reg), \ + .bit_idx =3D (_bit), \ + }, \ + .hw.init =3D &(struct clk_init_data) { \ + .name =3D "aud_"#_name, \ + .ops =3D &clk_regmap_gate_ops, \ + .parent_data =3D &(const struct clk_parent_data) { \ + .fw_name =3D "pclk" \ + }, \ + .num_parents =3D 1, \ + }, \ +} + +#define AUD_MST_MCLK_PDATA ((const struct clk_parent_data[]) { \ + { .fw_name =3D "mst_in0" }, \ + { .fw_name =3D "mst_in1" }, \ + { .fw_name =3D "mst_in2" }, \ + { .fw_name =3D "mst_in3" }, \ + { .fw_name =3D "mst_in4" }, \ +}) +#define AUD_MST_MCLK_MUX(_name, _reg) \ + AUD_MUX(_name##_sel, (_reg), 0x7, 24, CLK_MUX_ROUND_CLOSEST, \ + AUD_MST_MCLK_PDATA, 0) +#define AUD_MST_MCLK_DIV(_name, _reg) \ + AUD_DIV(_name##_div, (_reg), 0, 16, CLK_DIVIDER_ROUND_CLOSEST, \ + aud_##_name##_sel, CLK_SET_RATE_PARENT) +#define AUD_MST_MCLK_GATE(_name, _reg) \ + AUD_GATE(_name, (_reg), 31, \ + aud_##_name##_div, CLK_SET_RATE_PARENT) + +#define AUD_MST_SCLK_PRE_EN(_name, _reg, _pname) \ + AUD_GATE(_name##_pre_en, (_reg), 31, \ + aud_##_pname, 0) +#define AUD_MST_SCLK_DIV(_name, _reg) \ + AUD_SCLK_DIV(_name##_div, (_reg), 20, 10, 0, 0, \ + aud_##_name##_pre_en, CLK_SET_RATE_PARENT) +#define AUD_MST_SCLK_POST_EN(_name, _reg) \ + AUD_GATE(_name##_post_en, (_reg), 30, \ + aud_##_name##_div, CLK_SET_RATE_PARENT) +#define AUD_MST_SCLK(_name, _reg) \ + AUD_TRIPHASE(_name, (_reg), 1, 0, 2, 4, \ + aud_##_name##_post_en, CLK_SET_RATE_PARENT) + +#define AUD_MST_LRCLK_DIV(_name, _reg, _pname) \ + AUD_SCLK_DIV(_name##_div, (_reg), 0, 10, 10, 10, \ + aud_##_pname, 0) +#define AUD_MST_LRCLK(_name, _reg) \ + AUD_TRIPHASE(_name, (_reg), 1, 1, 3, 5, \ + aud_##_name##_div, CLK_SET_RATE_PARENT) + +#define AUD_MST_SCLK_PDATA ((const struct clk_parent_data[]) { \ + { .hw =3D &aud_mst_a_sclk.hw, .index =3D -1 }, \ + { .hw =3D &aud_mst_b_sclk.hw, .index =3D -1 }, \ + { .hw =3D &aud_mst_c_sclk.hw, .index =3D -1 }, \ + { .hw =3D &aud_mst_d_sclk.hw, .index =3D -1 }, \ + { .hw =3D NULL }, \ + { .hw =3D NULL }, \ + { .fw_name =3D "slv_sclk0" }, \ + { .fw_name =3D "slv_sclk1" }, \ + { .fw_name =3D "slv_sclk2" }, \ + { .fw_name =3D "slv_sclk3" }, \ + { .fw_name =3D "slv_sclk4" }, \ + { .fw_name =3D "slv_sclk5" }, \ + { .fw_name =3D "slv_sclk6" }, \ + { .fw_name =3D "slv_sclk7" }, \ + { .fw_name =3D "slv_sclk8" }, \ + { .fw_name =3D "slv_sclk9" }, \ +}) +#define AUD_TDM_SCLK_MUX(_name, _reg) \ + AUD_MUX(_name##_sel, (_reg), 0xf, 24, CLK_MUX_ROUND_CLOSEST, \ + AUD_MST_SCLK_PDATA, 0) +#define AUD_TDM_SCLK_PRE_EN(_name, _reg) \ + AUD_GATE(_name##_pre_en, (_reg), 31, \ + aud_##_name##_sel, CLK_SET_RATE_PARENT) +#define AUD_TDM_SCLK_POST_EN(_name, _reg) \ + AUD_GATE(_name##_post_en, (_reg), 30, \ + aud_##_name##_pre_en, CLK_SET_RATE_PARENT) +#define AUD_TDM_SCLK_WS(_name, _reg) \ + AUD_SCLK_WS(_name, (_reg), 1, 29, 28, \ + aud_##_name##_post_en, \ + CLK_DUTY_CYCLE_PARENT | CLK_SET_RATE_PARENT) + +#define AUD_MST_LRCLK_PDATA ((const struct clk_parent_data[]) { \ + { .hw =3D &aud_mst_a_lrclk.hw, .index =3D -1 }, \ + { .hw =3D &aud_mst_b_lrclk.hw, .index =3D -1 }, \ + { .hw =3D &aud_mst_c_lrclk.hw, .index =3D -1 }, \ + { .hw =3D &aud_mst_d_lrclk.hw, .index =3D -1 }, \ + { .hw =3D NULL }, \ + { .hw =3D NULL }, \ + { .fw_name =3D "slv_lrclk0" }, \ + { .fw_name =3D "slv_lrclk1" }, \ + { .fw_name =3D "slv_lrclk2" }, \ + { .fw_name =3D "slv_lrclk3" }, \ + { .fw_name =3D "slv_lrclk4" }, \ + { .fw_name =3D "slv_lrclk5" }, \ + { .fw_name =3D "slv_lrclk6" }, \ + { .fw_name =3D "slv_lrclk7" }, \ + { .fw_name =3D "slv_lrclk8" }, \ + { .fw_name =3D "slv_lrclk9" }, \ +}) +#define AUD_TDM_LRLCK(_name, _reg) \ + AUD_MUX(_name, (_reg), 0xf, 20, CLK_MUX_ROUND_CLOSEST, \ + AUD_MST_LRCLK_PDATA, CLK_SET_RATE_PARENT) + +struct a1_audio_data { + struct meson_clk_hw_data hw_clks; + const char *rst_drvname; +}; + +extern struct a1_audio_data a1_audio_clkc; +extern struct a1_audio_data a1_audio_vad_clkc; + +#endif /* __MESON_CLK_A1_AUDIO_H */ --=20 2.34.1 From nobody Sat Nov 30 01:00:51 2024 Received: from mx1.sberdevices.ru (mx2.sberdevices.ru [45.89.224.132]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4B6BD1DA108; Fri, 13 Sep 2024 12:14:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.89.224.132 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726229647; cv=none; b=J/gLD8zvSxD4QGREQqa6g64KOfMNL3BUoMLpjK/K/mRoR8uUiD68uIf2fSxF8FIuq5K8QS+e77IKgFAAfYNEiQnOnUiyVLXJM/RTrRnH6taMw3F8i9UfOulZzhuiZBYxXt6W39I7FRs8ZE7QQUrbM6z53dQ0ZhDvAJgVN/FEBDg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726229647; c=relaxed/simple; bh=YptXm1pdutJEYoAwHFHCNY1So2+7HjXqhrl7NsdFzNI=; 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charset="utf-8" Add the bus and audio clock controllers' device tree nodes. Signed-off-by: Jan Dakinevich --- arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 48 +++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dt= s/amlogic/meson-a1.dtsi index e5366d4239b1..b22cd5330606 100644 --- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi @@ -5,6 +5,7 @@ =20 #include #include +#include #include #include #include @@ -448,6 +449,53 @@ sd_emmc: mmc@10000 { power-domains =3D <&pwrc PWRC_SD_EMMC_ID>; status =3D "disabled"; }; + + audio: bus@50000 { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges =3D <0x0 0x0 0x0 0x50000 0 0x4980>; + power-domains =3D <&pwrc PWRC_AUDIO_ID>; + + clkc_audio: clock-controller@0 { + compatible =3D "amlogic,a1-audio-clkc"; + reg =3D <0x0 0x0 0x0 0xb0>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + clocks =3D <&clkc_audio_vad AUD_CLKID_VAD_AUDIOTOP>, + <&clkc_periphs CLKID_DDS_IN>, + <&clkc_pll CLKID_FCLK_DIV2>, + <&clkc_pll CLKID_FCLK_DIV3>, + <&clkc_pll CLKID_HIFI_PLL>, + <&xtal>; + clock-names =3D "pclk", + "mst_in0", + "mst_in1", + "mst_in2", + "mst_in3", + "mst_in4"; + resets =3D <&reset RESET_AUDIO>; + }; + + clkc_audio_vad: clock-controller@4800 { + compatible =3D "amlogic,a1-audio-vad-clkc"; + reg =3D <0x0 0x4800 0x0 0x20>; + #clock-cells =3D <1>; + clocks =3D <&clkc_periphs CLKID_AUDIO>, + <&clkc_periphs CLKID_DDS_IN>, + <&clkc_pll CLKID_FCLK_DIV2>, + <&clkc_pll CLKID_FCLK_DIV3>, + <&clkc_pll CLKID_HIFI_PLL>, + <&xtal>; + clock-names =3D "pclk", + "mst_in0", + "mst_in1", + "mst_in2", + "mst_in3", + "mst_in4"; + resets =3D <&reset RESET_AUDIO_VAD>; + }; + }; }; =20 usb: usb@fe004400 { --=20 2.34.1