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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Sep 2024 11:40:26.1923 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b8aab8c8-a45b-48a5-7acb-08dcd3e8dc61 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099DF.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB8093 Content-Type: text/plain; charset="utf-8" From: Kishon Vijay Abraham I Secure AVIC has introduced a new field in the APIC backing page "NmiReq" that has to be set by the guest to request a NMI IPI. Add support to set NmiReq appropriately to send NMI IPI. This also requires Virtual NMI feature to be enabled in VINTRL_CTRL field in the VMSA. However this would be added by a later commit after adding support for injecting NMI from the hypervisor. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Neeraj Upadhyay --- arch/x86/kernel/apic/x2apic_savic.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/arch/x86/kernel/apic/x2apic_savic.c b/arch/x86/kernel/apic/x2a= pic_savic.c index 2eab9a773005..5502a828a795 100644 --- a/arch/x86/kernel/apic/x2apic_savic.c +++ b/arch/x86/kernel/apic/x2apic_savic.c @@ -183,7 +183,7 @@ static void x2apic_savic_write(u32 reg, u32 data) } } =20 -static void send_ipi(int cpu, int vector) +static void send_ipi(int cpu, int vector, bool nmi) { void *backing_page; int reg_off; @@ -195,16 +195,20 @@ static void send_ipi(int cpu, int vector) * IRR updates such as during VMRUN and during CPU interrupt handling flo= w. */ test_and_set_bit(VEC_POS(vector), (unsigned long *)((char *)backing_page = + reg_off)); + if (nmi) + set_reg(backing_page, SAVIC_NMI_REQ_OFFSET, nmi); } =20 static void send_ipi_dest(u64 icr_data) { int vector, cpu; + bool nmi; =20 vector =3D icr_data & APIC_VECTOR_MASK; cpu =3D icr_data >> 32; + nmi =3D ((icr_data & APIC_DM_FIXED_MASK) =3D=3D APIC_DM_NMI); =20 - send_ipi(cpu, vector); + send_ipi(cpu, vector, nmi); } =20 static void send_ipi_target(u64 icr_data) @@ -222,11 +226,13 @@ static void send_ipi_allbut(u64 icr_data) const struct cpumask *self_cpu_mask =3D get_cpu_mask(smp_processor_id()); unsigned long flags; int vector, cpu; + bool nmi; =20 vector =3D icr_data & APIC_VECTOR_MASK; + nmi =3D ((icr_data & APIC_DM_FIXED_MASK) =3D=3D APIC_DM_NMI); local_irq_save(flags); for_each_cpu_andnot(cpu, cpu_present_mask, self_cpu_mask) - send_ipi(cpu, vector); + send_ipi(cpu, vector, nmi); write_msr_to_hv(APIC_ICR, icr_data); local_irq_restore(flags); } --=20 2.34.1