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charset="utf-8" The pipediv2_clk's source from the same mux as pipe clock. So they have same limitation, which is that the PHY sequence requires to enable these local CBCs before the PHY is actually outputting a clock to them. This means the clock won't actually turn on when we vote them. Hence, let's skip the halt bit check of the pipediv2_clk, otherwise pipediv2_clk may stuck at off state during bootup. Suggested-by: Mike Tipton Signed-off-by: Qiang Yu Reviewed-by: Konrad Dybcio --- drivers/clk/qcom/gcc-x1e80100.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/clk/qcom/gcc-x1e80100.c b/drivers/clk/qcom/gcc-x1e8010= 0.c index 0f578771071f..81ba5ceab342 100644 --- a/drivers/clk/qcom/gcc-x1e80100.c +++ b/drivers/clk/qcom/gcc-x1e80100.c @@ -3123,7 +3123,7 @@ static struct clk_branch gcc_pcie_3_pipe_clk =3D { =20 static struct clk_branch gcc_pcie_3_pipediv2_clk =3D { .halt_reg =3D 0x58060, - .halt_check =3D BRANCH_HALT_VOTED, + .halt_check =3D BRANCH_HALT_SKIP, .clkr =3D { .enable_reg =3D 0x52020, .enable_mask =3D BIT(5), @@ -3248,7 +3248,7 @@ static struct clk_branch gcc_pcie_4_pipe_clk =3D { =20 static struct clk_branch gcc_pcie_4_pipediv2_clk =3D { .halt_reg =3D 0x6b054, - .halt_check =3D BRANCH_HALT_VOTED, + .halt_check =3D BRANCH_HALT_SKIP, .clkr =3D { .enable_reg =3D 0x52010, .enable_mask =3D BIT(27), @@ -3373,7 +3373,7 @@ static struct clk_branch gcc_pcie_5_pipe_clk =3D { =20 static struct clk_branch gcc_pcie_5_pipediv2_clk =3D { .halt_reg =3D 0x2f054, - .halt_check =3D BRANCH_HALT_VOTED, + .halt_check =3D BRANCH_HALT_SKIP, .clkr =3D { .enable_reg =3D 0x52018, .enable_mask =3D BIT(19), @@ -3511,7 +3511,7 @@ static struct clk_branch gcc_pcie_6a_pipe_clk =3D { =20 static struct clk_branch gcc_pcie_6a_pipediv2_clk =3D { .halt_reg =3D 0x31060, - .halt_check =3D BRANCH_HALT_VOTED, + .halt_check =3D BRANCH_HALT_SKIP, .clkr =3D { .enable_reg =3D 0x52018, .enable_mask =3D BIT(28), @@ -3649,7 +3649,7 @@ static struct clk_branch gcc_pcie_6b_pipe_clk =3D { =20 static struct clk_branch gcc_pcie_6b_pipediv2_clk =3D { .halt_reg =3D 0x8d060, - .halt_check =3D BRANCH_HALT_VOTED, + .halt_check =3D BRANCH_HALT_SKIP, .clkr =3D { .enable_reg =3D 0x52010, .enable_mask =3D BIT(28), --=20 2.34.1