From nobody Sat Nov 30 00:45:21 2024 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7C9271D6C4E for ; Fri, 13 Sep 2024 08:26:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726215976; cv=none; b=pFpgdzGvVGrwO2Ek6/HO5agP84ve7dvDdFbWH4wH8rFQ/R+PLi2bKbeom1DOU3YYWuVZyJ/DZDggV1C2H9BVLChpfJ2RgXc77KV0xBb5s0Px1wpJ6NX3e/w3//TydONTXjoZKwhFBWRVmb1wwG761JvLDSO0CD5zQUqQivAgybA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726215976; c=relaxed/simple; bh=34DMiNqCXssyBrnitnU+1cTTFyON1eU082vWM8USQn8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=fwxDsub2aizMdQRzOUBqvBYlHatw41kTGBbJcxj9AXCKT7lUV57WDU5S2sGqk7JSrp61Po5gMSan4Uo8pw2GoMXvxnp/9i0Eb9mHTL2lZN5e9OaFa0BJ808sCMLNwys/C2HJIV1Z9bYCmR+ZSnowFMmAJUTdFEL4KcVLDaGu/08= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=SIqcbdQN; arc=none smtp.client-ip=198.175.65.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="SIqcbdQN" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1726215974; x=1757751974; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=34DMiNqCXssyBrnitnU+1cTTFyON1eU082vWM8USQn8=; b=SIqcbdQNbpoLBNFmKgg1cBCuQ7H3loSV3go/69YVY2oFAwmLS1cIyiab Yc6lmVc71nEjj539zhS1Uns6v/hVfUfkqtW9lE5fQARvfufO/1/IWZKkr +R2FzndDRbdCxsfXHmm+fMBU4v6QH0YBQmE8ENSWj4uMoKxpbQ3tO+IYV fJQyAyg8KZMc+JPgR24f5weiOeEcvJSBlxkpuNCXS6P2uX78ZOevBcuNY hw3hLHCXNyAb8p216BrWldfap/6wUkMZ0g4cWBP6feLxsk9eKiIxPax+t CaZxnPbeJ+yPCIR9bAX4zfbp3w7HtUCj7RQ41Z/zV09H/1ygkPnC43OM8 g==; X-CSE-ConnectionGUID: 8VTxC5ElRYW+/NR1hzUoiw== X-CSE-MsgGUID: kJNihpRlQgy389iUu3k35A== X-IronPort-AV: E=McAfee;i="6700,10204,11193"; a="24977570" X-IronPort-AV: E=Sophos;i="6.10,225,1719903600"; d="scan'208";a="24977570" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Sep 2024 01:26:13 -0700 X-CSE-ConnectionGUID: m3R6K8O3SYKiw2uceiW++Q== X-CSE-MsgGUID: IkexIDuhQr+tqyI9xMz/8A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,225,1719903600"; d="scan'208";a="68485429" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by orviesa007.jf.intel.com with ESMTP; 13 Sep 2024 01:26:12 -0700 From: Ricardo Neri To: x86@kernel.org Cc: Andreas Herrmann , Catalin Marinas , Chen Yu , Len Brown , Radu Rendec , Pierre Gondois , Pu Wen , "Rafael J. Wysocki" , Sudeep Holla , Srinivas Pandruvada , Will Deacon , Zhang Rui , Nikolay Borisov , Huang Ying , Ricardo Neri , linux-kernel@vger.kernel.org Subject: [PATCH v7 1/3] cacheinfo: Allocate memory during CPU hotplug if not done from the primary CPU Date: Fri, 13 Sep 2024 01:31:53 -0700 Message-Id: <20240913083155.9783-2-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240913083155.9783-1-ricardo.neri-calderon@linux.intel.com> References: <20240913083155.9783-1-ricardo.neri-calderon@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Commit 5944ce092b97 ("arch_topology: Build cacheinfo from primary CPU") adds functionality that architectures can use to optionally allocate and build cacheinfo early during boot. Commit 6539cffa9495 ("cacheinfo: Add arch specific early level initializer") lets secondary CPUs correct (and reallocate memory) cacheinfo data if needed. If the early build functionality is not used and cacheinfo does not need correction, memory for cacheinfo is never allocated. x86 does not use the early build functionality. Consequently, during the cacheinfo CPU hotplug callback, last_level_cache_is_valid() attempts to dereference a NULL pointer: BUG: kernel NULL pointer dereference, address: 0000000000000100 #PF: supervisor read access in kernel mode #PF: error_code(0x0000) - not present page PGD 0 P4D 0 Oops: 0000 [#1] PREEPMT SMP NOPTI CPU: 0 PID 19 Comm: cpuhp/0 Not tainted 6.4.0-rc2 #1 RIP: 0010: last_level_cache_is_valid+0x95/0xe0a Allocate memory for cacheinfo during the cacheinfo CPU hotplug callback if not done earlier. Moreover, before determining the validity of the last-level cache info, ensure that it has been allocated. Simply checking for non-zero cache_leaves() is not sufficient, as some architectures (e.g., Intel processors) have non-zero cache_leaves() before allocation. Dereferencing NULL cacheinfo can occur in update_per_cpu_data_slice_size(). This function iterates over all online CPUs. However, a CPU may have come online recently, but its cacheinfo may not have been allocated yet. While here, remove an unnecessary indentation in allocate_cache_info(). Reviewed-by: Andreas Herrmann Reviewed-by: Nikolay Borisov Reviewed-by: Radu Rendec Reviewed-by: Sudeep Holla Tested-by: Andreas Herrmann Fixes: 6539cffa9495 ("cacheinfo: Add arch specific early level initializer") Signed-off-by: Ricardo Neri --- Cc: Andreas Herrmann Cc: Catalin Marinas Cc: Chen Yu Cc: Huang Ying Cc: Len Brown Cc: Nikolay Borisov Cc: Radu Rendec Cc: Pierre Gondois Cc: Pu Wen Cc: "Rafael J. Wysocki" Cc: Sudeep Holla Cc: Srinivas Pandruvada Cc: Will Deacon Cc: Zhang Rui Cc: linux-arm-kernel@lists.infradead.org Cc: stable@vger.kernel.org # 6.3+ --- Changes since v6: * Merged patches 1 and 2 of v6 into one. (Borislav) * Merged the history of patches 1 and 2 into this patch. * Kept the Reviewed-by and Tested-by tags from the two merged patches. * Fixed a formatting issue in allocate_cache_info(). (Borislav) Changes since v5: * Fixed nonsensical subject (Nikolay). * Added Reviewed-by and Tested-by tags from Andreas. Thanks! * Added Reviewed-by tag from Nikolay. Thanks! Changes since v4: * Combined checks for per_cpu_cacheinfo() and cache_leaves() in a single line. (Sudeep) * Added Reviewed-by tag from Sudeep. Thanks! Changes since v3: * Added Reviewed-by tag from Radu and Sudeep. Thanks! Changes since v2: * Introduced this patch. Changes since v1: * N/A --- The motivation for commit 5944ce092b97 was to prevent a BUG splat in PREEMPT_RT kernels during memory allocation. This splat is not observed on x86 because the memory allocation for cacheinfo happens in detect_cache_attributes() from the cacheinfo CPU hotplug callback. The dereference of a NULL cacheinfo is not observed today because cache_leaves(cpu) is zero until after init_cache_level() is called (during the CPU hotplug callback). A subsequent changeset will set the number of cache leaves earlier and the NULL-pointer dereference will be observed. --- drivers/base/cacheinfo.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/base/cacheinfo.c b/drivers/base/cacheinfo.c index 23b8cba4a2a3..5f35a76cba2a 100644 --- a/drivers/base/cacheinfo.c +++ b/drivers/base/cacheinfo.c @@ -58,7 +58,7 @@ bool last_level_cache_is_valid(unsigned int cpu) { struct cacheinfo *llc; =20 - if (!cache_leaves(cpu)) + if (!cache_leaves(cpu) || !per_cpu_cacheinfo(cpu)) return false; =20 llc =3D per_cpu_cacheinfo_idx(cpu, cache_leaves(cpu) - 1); @@ -481,8 +481,7 @@ int __weak populate_cache_leaves(unsigned int cpu) static inline int allocate_cache_info(int cpu) { - per_cpu_cacheinfo(cpu) =3D kcalloc(cache_leaves(cpu), - sizeof(struct cacheinfo), GFP_ATOMIC); + per_cpu_cacheinfo(cpu) =3D kcalloc(cache_leaves(cpu), sizeof(struct cache= info), GFP_ATOMIC); if (!per_cpu_cacheinfo(cpu)) { cache_leaves(cpu) =3D 0; return -ENOMEM; @@ -554,7 +553,11 @@ static inline int init_level_allocate_ci(unsigned int = cpu) */ ci_cacheinfo(cpu)->early_ci_levels =3D false; =20 - if (cache_leaves(cpu) <=3D early_leaves) + /* + * Some architectures (e.g., x86) do not use early initialization. + * Allocate memory now in such case. + */ + if (cache_leaves(cpu) <=3D early_leaves && per_cpu_cacheinfo(cpu)) return 0; =20 kfree(per_cpu_cacheinfo(cpu)); --=20 2.34.1 From nobody Sat Nov 30 00:45:21 2024 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F0F091D67B4 for ; Fri, 13 Sep 2024 08:26:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726215976; cv=none; b=KC6UE722ZYKxaAAr3jkgu2iPQFECFzJXoZo0bChsbXoebMPXhZo8i2Ta4bzeC8dlfX+N5XV1TTQDVTk/SsG+d3TLpNTjc/NRYPaNGuFksZdIZ8+/dssQDKy7Pev852S1n+FlTMFXXDLUdSZxlJRWytCqXFKr5Trld6WuDWPEqso= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726215976; c=relaxed/simple; bh=PcJl2+cEF+bRzQuqeAjuEPnGZ6EOblSbeWsQbeMWdEI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=uG9InoelVINFSafU8SuTV4IPw40hqmEbZWvM/sVp09y7XP/PUxEIm+C0e5lKDqQqSLVxWYm6v2aV/RQfSleenchXpoKt4lGz02+AjVtXQrY4Y9w2UB84x1EYqhHpr0fq7ygwAcdb2lqTlASVKdttBEjHb6kIFHI1DUzBB06CglU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=jK9e4af6; arc=none smtp.client-ip=198.175.65.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="jK9e4af6" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1726215975; x=1757751975; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=PcJl2+cEF+bRzQuqeAjuEPnGZ6EOblSbeWsQbeMWdEI=; b=jK9e4af6TxKbHGSf10z+STm3dA/IITDTWoBbZ+QYY1MlUE7PYM1iTo8T 6RskEVEVVDfon8aiY3fbRJaqFShQRxTbkWbVvSAe1ZZIC/b3NIzu/jC/3 nyLvoeadyCYKITc77jmB7svL31lw+kguIAh63QtugLcYkDf+365c58Ma2 QII435SWe9G3RB8Ait0DYcNmIlkAx4KVeDSDqr05H8ClqkgT9K2W/NtQb njs2r/5I6vQAr2EmRjbk77W3G9U8uaJhBAGiiJKtj1G6Xuo8XP8ckOoMl YhbRTsM5jCMIUM49kKggaNK7lw4B9jTRCPOXxRTDmGZmdEjLnwGzdWeBB w==; X-CSE-ConnectionGUID: 1um7ID9nQSaNkG3w+VVmDA== X-CSE-MsgGUID: GBeChEkAR1m1/hyaYEDgQg== X-IronPort-AV: E=McAfee;i="6700,10204,11193"; a="24977577" X-IronPort-AV: E=Sophos;i="6.10,225,1719903600"; d="scan'208";a="24977577" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Sep 2024 01:26:13 -0700 X-CSE-ConnectionGUID: Q+eoR1T9QpuzLoxhH++z5g== X-CSE-MsgGUID: 5qz4hpHkQvC2PUWaTB8gLw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,225,1719903600"; d="scan'208";a="68485435" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by orviesa007.jf.intel.com with ESMTP; 13 Sep 2024 01:26:13 -0700 From: Ricardo Neri To: x86@kernel.org Cc: Andreas Herrmann , Catalin Marinas , Chen Yu , Len Brown , Radu Rendec , Pierre Gondois , Pu Wen , "Rafael J. Wysocki" , Sudeep Holla , Srinivas Pandruvada , Will Deacon , Zhang Rui , Nikolay Borisov , Huang Ying , Ricardo Neri , linux-kernel@vger.kernel.org Subject: [PATCH v7 2/3] x86/cacheinfo: Delete global num_cache_leaves Date: Fri, 13 Sep 2024 01:31:54 -0700 Message-Id: <20240913083155.9783-3-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240913083155.9783-1-ricardo.neri-calderon@linux.intel.com> References: <20240913083155.9783-1-ricardo.neri-calderon@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Linux remembers cpu_cachinfo::num_leaves per CPU, but x86 initializes all CPUs from the same global "num_cache_leaves". This is erroneous on systems such as Meteor Lake, where each CPU has a distinct num_leaves value. Delete the global "num_cache_leaves" and initialize num_leaves on each CPU. Reviewed-by: Andreas Herrmann Reviewed-by: Len Brown Reviewed-by: Nikolay Borisov Tested-by: Andreas Herrmann Signed-off-by: Ricardo Neri --- Cc: Andreas Herrmann Cc: Catalin Marinas Cc: Chen Yu Cc: Huang Ying Cc: Len Brown Cc: Nikolay Borisov Cc: Radu Rendec Cc: Pierre Gondois Cc: Pu Wen Cc: "Rafael J. Wysocki" Cc: Sudeep Holla Cc: Srinivas Pandruvada Cc: Will Deacon Cc: Zhang Rui Cc: linux-arm-kernel@lists.infradead.org Cc: stable@vger.kernel.org # 6.3+ --- After this change, all CPUs will traverse CPUID leaf 0x4 when booted for the first time. On systems with symmetric cache topologies this is useless work. Creating a list of processor models that have asymmetric cache topologies was considered. The burden of maintaining such list would outweigh the performance benefit of skipping this extra step. --- Changes since v5: * Reordered the arguments of set_num_cache_leaves() for readability. (Nikolay) * Added Reviewed-by tag from Nikolay and Andreas. Thanks! * Added Tested-by tag from Andreas. Thanks! Changes since v4: * None Changes since v3: * Rebased on v6.7-rc5. Changes since v2: * None Changes since v1: * Do not make num_cache_leaves a per-CPU variable. Instead, reuse the existing per-CPU ci_cpu_cacheinfo variable. (Dave Hansen) --- arch/x86/kernel/cpu/cacheinfo.c | 44 +++++++++++++++++++-------------- 1 file changed, 26 insertions(+), 18 deletions(-) diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinf= o.c index 392d09c936d6..182cacd772b8 100644 --- a/arch/x86/kernel/cpu/cacheinfo.c +++ b/arch/x86/kernel/cpu/cacheinfo.c @@ -178,7 +178,16 @@ struct _cpuid4_info_regs { struct amd_northbridge *nb; }; =20 -static unsigned short num_cache_leaves; +static inline unsigned int get_num_cache_leaves(unsigned int cpu) +{ + return get_cpu_cacheinfo(cpu)->num_leaves; +} + +static inline void +set_num_cache_leaves(unsigned int cpu, unsigned int nr_leaves) +{ + get_cpu_cacheinfo(cpu)->num_leaves =3D nr_leaves; +} =20 /* AMD doesn't have CPUID4. Emulate it here to report the same information to the user. This makes some assumptions about the machine: @@ -718,19 +727,21 @@ void cacheinfo_hygon_init_llc_id(struct cpuinfo_x86 *= c) void init_amd_cacheinfo(struct cpuinfo_x86 *c) { =20 + unsigned int cpu =3D c->cpu_index; + if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { - num_cache_leaves =3D find_num_cache_leaves(c); + set_num_cache_leaves(cpu, find_num_cache_leaves(c)); } else if (c->extended_cpuid_level >=3D 0x80000006) { if (cpuid_edx(0x80000006) & 0xf000) - num_cache_leaves =3D 4; + set_num_cache_leaves(cpu, 4); else - num_cache_leaves =3D 3; + set_num_cache_leaves(cpu, 3); } } =20 void init_hygon_cacheinfo(struct cpuinfo_x86 *c) { - num_cache_leaves =3D find_num_cache_leaves(c); + set_num_cache_leaves(c->cpu_index, find_num_cache_leaves(c)); } =20 void init_intel_cacheinfo(struct cpuinfo_x86 *c) @@ -742,19 +753,19 @@ void init_intel_cacheinfo(struct cpuinfo_x86 *c) unsigned int l2_id =3D 0, l3_id =3D 0, num_threads_sharing, index_msb; =20 if (c->cpuid_level > 3) { - static int is_initialized; - - if (is_initialized =3D=3D 0) { - /* Init num_cache_leaves from boot CPU */ - num_cache_leaves =3D find_num_cache_leaves(c); - is_initialized++; - } + /* + * There should be at least one leaf. A non-zero value means + * that the number of leaves has been initialized. + */ + if (!get_num_cache_leaves(c->cpu_index)) + set_num_cache_leaves(c->cpu_index, + find_num_cache_leaves(c)); =20 /* * Whenever possible use cpuid(4), deterministic cache * parameters cpuid leaf to find the cache details */ - for (i =3D 0; i < num_cache_leaves; i++) { + for (i =3D 0; i < get_num_cache_leaves(c->cpu_index); i++) { struct _cpuid4_info_regs this_leaf =3D {}; int retval; =20 @@ -790,14 +801,14 @@ void init_intel_cacheinfo(struct cpuinfo_x86 *c) * Don't use cpuid2 if cpuid4 is supported. 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Wysocki" , Sudeep Holla , Srinivas Pandruvada , Will Deacon , Zhang Rui , Nikolay Borisov , Huang Ying , Ricardo Neri , linux-kernel@vger.kernel.org Subject: [PATCH v7 3/3] x86/cacheinfo: Clean out init_cache_level() Date: Fri, 13 Sep 2024 01:31:55 -0700 Message-Id: <20240913083155.9783-4-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240913083155.9783-1-ricardo.neri-calderon@linux.intel.com> References: <20240913083155.9783-1-ricardo.neri-calderon@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" init_cache_level() no longer has a purpose on x86. It no longer needs to set num_leaves, and it never had to set num_levels, which was unnecessary on x86. Replace it with "return 0" simply to override the weak function, which would return an error. Reviewed-by: Andreas Herrmann Reviewed-by: Len Brown Reviewed-by: Nikolay Borisov Tested-by: Andreas Herrmann Signed-off-by: Ricardo Neri --- Cc: Andreas Herrmann Cc: Catalin Marinas Cc: Chen Yu CC: Huang Ying Cc: Len Brown Cc: Nikolay Borisov Cc: Radu Rendec Cc: Pierre Gondois Cc: Pu Wen Cc: "Rafael J. Wysocki" Cc: Sudeep Holla Cc: Srinivas Pandruvada Cc: Will Deacon Cc: Zhang Rui Cc: linux-arm-kernel@lists.infradead.org Cc: stable@vger.kernel.org # 6.3+ --- Changes since v5: * Added Reviewed-by tag from Nikolay and Andreas. Thanks! Changes since v4: * None Changes since v3: * Rebased on v6.7-rc5. Changes since v2: * None Changes since v1: * Introduced this patch. --- arch/x86/kernel/cpu/cacheinfo.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinf= o.c index 182cacd772b8..2a37f14cc6b1 100644 --- a/arch/x86/kernel/cpu/cacheinfo.c +++ b/arch/x86/kernel/cpu/cacheinfo.c @@ -1002,11 +1002,6 @@ static void ci_leaf_init(struct cacheinfo *this_leaf, =20 int init_cache_level(unsigned int cpu) { - struct cpu_cacheinfo *this_cpu_ci =3D get_cpu_cacheinfo(cpu); - - if (!this_cpu_ci) - return -EINVAL; - this_cpu_ci->num_levels =3D 3; return 0; } =20 --=20 2.34.1