From nobody Sat Nov 30 02:57:23 2024 Received: from mail-ej1-f46.google.com (mail-ej1-f46.google.com [209.85.218.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B57DC84D25; Fri, 13 Sep 2024 15:08:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726240115; cv=none; b=miDYzmwvqujydIfC7Q/guDCFrWzIBmOrU4V7TTAR+2GFeCnnvqhmPKT/8Rb5Ch2dee8rs6qXXM3X/ZzagusKsboQI1SpwPh7Dd7qafs3iXiotXOoY+SsoaQSx3M297k2ddRm08+aK4BbpoOdgpP6ww08X1OO9LU6oycGO14Qcyw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726240115; c=relaxed/simple; bh=6bnUnN2fjqbjQHrlo2uvWKZSiDrU+DiVQwIgC/N9EP4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=O8sqIQ9tvwOJtKD9GiLFZmDURitbit405ZVHoEtGZE8aFUBV6aoRnaz/6+99BV1tcFxWvtZgPYWk7TMmX9Pvd9tXuOoFrrYXqiw04Up3XwXMkpxDrAe3QEXazviz8AUNO1z0ooxGgrr2GSfao/5CTI2GK0qHcjGKLGuGDb8NzrY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=Y6Xs0gXA; arc=none smtp.client-ip=209.85.218.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Y6Xs0gXA" Received: by mail-ej1-f46.google.com with SMTP id a640c23a62f3a-a8a837cec81so56832866b.2; Fri, 13 Sep 2024 08:08:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1726240110; x=1726844910; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=QIGDGMW2gV7nFgzFY99SH3Qqk1xbwMk6ylQkR/yKW3M=; b=Y6Xs0gXA0S3rSU1lk35UQjiysk+2lpXHdVHYM9Pk9pc58PiZs4X0wCzU8zRUK/PUMi BkSB8SjPcUsjwhJIWwhXwVd/bGZXigtcP47kAiRRQb8tdkXUQeZ12eeqtDKUlnWLgX7G O17bHbPqujmNDTwiVAQgA15JVzyKOjuAYLElIPjg3kjbM9fximI4lmvPcN1yfPEc/zr3 cM2qsGXn6TxB7dcxK758YG18yMqpmeZsA0+BnRD70WGIWQ1Lo23URaPL6GR+2PQFNDMN t1aoIU4Yg2pkTpanYb0a+ZzCQUCK1vhtpB/t0HRtOMgfJRxnSrxc5M6wqk7lbmGmJVWx 4mcg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726240110; x=1726844910; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QIGDGMW2gV7nFgzFY99SH3Qqk1xbwMk6ylQkR/yKW3M=; b=TYdm0ht1yU1VpxLf9KvX/W7MgLN60/L+UI1XRop9yaX8YeFhuOTAVwv1bZeUjoLlCG FT7Dn8w5+mu3Nej8WShonm+Xp8LzNPtYYSNDxX1j5LoNTikokpAl0RCuTIQy7uCxzPiu D3Cr4b+lbNmTUXkw4Pey2uiqIBQzPLNevf+B1tEOXGK3wBslYXn1SmKY48vyN8rZgTfM SgtqLDSEthngi2/hhTOsejXj2rLKw+p8+9FyffnfXQJCM3UPFA3l3/+v6Q3tKic6QLXk o9uQAdVObdhzK8pjS+wX6q5orgF9+uWyDA8WhHhqiAeH/NICDSImP3mmqs1p34L+9jDU Xvsw== X-Forwarded-Encrypted: i=1; AJvYcCVEsDMxC0xErrzZJJbt58YzlvSZVrWD5l4jpIwU0SduyRjx8ft5Ada5PVj8X5A7FLBL8cLrv85kENz8eYU=@vger.kernel.org, AJvYcCVewab+GPPdGoI7y73ka98kClUVxZ/GTOsgEtlJCARqM6nEq4kOq3IxyHYePHYyxg9zwbFTHPpXa4SqeAKkCkQ4uko=@vger.kernel.org, AJvYcCVrDqMEkGT6YVuqbqoRqLHDDK9AVd0N+zVedQZdxL+pcnnKOrySBAK8/c13h9imyOXqKgHZP0tidI22S47++A==@vger.kernel.org, AJvYcCWXge/th7DE6EA/85pzwxmGXQzZIxpn2bOE2qWBbLpL0AMSca0ZHJrb6/wTdYXVzEAT4QWMVh6FSn6e@vger.kernel.org, AJvYcCXK3zsZTbbnPv6cr9q5HhyfvQ7wXXSUaQ4x4mezbIp7GpVWqXMiYYSVyvzGj6pzx8UaHGLJQo5Tn87lHQ==@vger.kernel.org, AJvYcCXlBbuu/4DA4QIXDsGfDNFeQ2HCDaWZfY+IYyEenhsIpj1OQxzJQJ+1BuI+o7NHXPcHRE4CHg/aCp3Z@vger.kernel.org, AJvYcCXoymf8o0seYn6FK+1+y7d19ko8CO4APeEocV0pcajWaQdwep0XQo2f54c9P/NSjiKDUAtJqmnDSSe3@vger.kernel.org, AJvYcCXyjwNVgRyga/CUBbrlD7N/+jIT3EGrs2SgGhzUAz/dl0/I6QBDeml/dFXMiLP2YwF0wwewArgj0htDxvEr@vger.kernel.org X-Gm-Message-State: AOJu0YxETjZUDMCSOOXz79ElRWGhYTTJ8uQIuSxmg2wJtEMxRI6EmZnu vcwu1rFXfOacQ9F0RI0VtlX+s+5F/1dyxFeFUXtTugOV4ENBArXwVeF3eg== X-Google-Smtp-Source: AGHT+IHRjTy9SjhA50SvwZIPFaLCaWiSjrjxv0c+LROAPsqJ6y+hjHvz4rJM3p62I3MY9mHr/MrHFg== X-Received: by 2002:a05:6402:2551:b0:5c2:6d13:c583 with SMTP id 4fb4d7f45d1cf-5c41e1b5354mr2952918a12.28.1726240109559; Fri, 13 Sep 2024 08:08:29 -0700 (PDT) Received: from [127.0.1.1] ([178.127.153.210]) by smtp.googlemail.com with ESMTPSA id 4fb4d7f45d1cf-5c3ebd523b4sm7774318a12.51.2024.09.13.08.08.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Sep 2024 08:08:28 -0700 (PDT) From: Dzmitry Sankouski Date: Fri, 13 Sep 2024 18:07:50 +0300 Subject: [PATCH v4 07/27] drm/panel: Add support for S6E3HA8 panel driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240913-starqltechn_integration_upstream-v4-7-2d2efd5c5877@gmail.com> References: <20240913-starqltechn_integration_upstream-v4-0-2d2efd5c5877@gmail.com> In-Reply-To: <20240913-starqltechn_integration_upstream-v4-0-2d2efd5c5877@gmail.com> To: Sebastian Reichel , Bjorn Andersson , Michael Turquette , Stephen Boyd , Neil Armstrong , Jessica Zhang , Sam Ravnborg , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lee Jones , Dmitry Torokhov , Pavel Machek , Liam Girdwood , Mark Brown , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Krzysztof Kozlowski , Chanwoo Choi , Simona Vetter , cros-qcom-dts-watchers@chromium.org, Konrad Dybcio , Simona Vetter , Konrad Dybcio Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-input@vger.kernel.org, linux-leds@vger.kernel.org, linux-pwm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, Dzmitry Sankouski X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1726240085; l=14348; i=dsankouski@gmail.com; s=20240618; h=from:subject:message-id; bh=6bnUnN2fjqbjQHrlo2uvWKZSiDrU+DiVQwIgC/N9EP4=; b=w2p2aGFyl/zOnE3M+Z/e2o8rBr01lm95qewF0CbbCQ/D/TjYUjivbXqHPOq3+a5o7xU89T8al ySh2IjbpAazBcAo1mf9HrpHFa27LL2o89jv6H3q1+nth5UmE7UuRusz X-Developer-Key: i=dsankouski@gmail.com; a=ed25519; pk=6pMMVVDDReSiRgPCbMOUauN5nS3ty4Sf5b7a2gi4x0M= Add support for MIPI-DSI based S6E3HA8 AMOLED panel driver. This panel has 1440x2960 resolution, 5.8-inch physical size, and can be found in starqltechn device. Brightness regulation is not yet supported. Signed-off-by: Dzmitry Sankouski Changes in v4: - inline power related functions - rework driver using new mipi_dsi_dcs_write_seq_multi macro - use drm_connector_helper_get_modes_fixed for modes - remove excessive compression setting --- MAINTAINERS | 1 + drivers/gpu/drm/panel/Kconfig | 7 + drivers/gpu/drm/panel/Makefile | 1 + drivers/gpu/drm/panel/panel-samsung-s6e3ha8.c | 350 ++++++++++++++++++++++= ++++ 4 files changed, 359 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 92135252264a..65cb2511ba22 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -7385,6 +7385,7 @@ DRM DRIVER FOR SAMSUNG S6E3HA8 PANELS M: Dzmitry Sankouski S: Maintained F: Documentation/devicetree/bindings/display/panel/samsung,s6e3ha8.yaml +F: drivers/gpu/drm/panel/panel-samsung-s6e3ha8.c =20 DRM DRIVER FOR SITRONIX ST7586 PANELS M: David Lechner diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig index d3a9a9fafe4e..65fb3a466e39 100644 --- a/drivers/gpu/drm/panel/Kconfig +++ b/drivers/gpu/drm/panel/Kconfig @@ -689,6 +689,13 @@ config DRM_PANEL_SAMSUNG_S6E3HA2 depends on BACKLIGHT_CLASS_DEVICE select VIDEOMODE_HELPERS =20 +config DRM_PANEL_SAMSUNG_S6E3HA8 + tristate "Samsung S6E3HA8 DSI video mode panel" + depends on OF + depends on DRM_MIPI_DSI + depends on BACKLIGHT_CLASS_DEVICE + select VIDEOMODE_HELPERS + config DRM_PANEL_SAMSUNG_S6E63J0X03 tristate "Samsung S6E63J0X03 DSI command mode panel" depends on OF diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile index 987a08702410..8ee28f5a2213 100644 --- a/drivers/gpu/drm/panel/Makefile +++ b/drivers/gpu/drm/panel/Makefile @@ -70,6 +70,7 @@ obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6D27A1) +=3D panel-samsun= g-s6d27a1.o obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6D7AA0) +=3D panel-samsung-s6d7aa0.o obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6E3FA7) +=3D panel-samsung-s6e3fa7.o obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2) +=3D panel-samsung-s6e3ha2.o +obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6E3HA8) +=3D panel-samsung-s6e3ha8.o obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03) +=3D panel-samsung-s6e63j0x03.o obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6E63M0) +=3D panel-samsung-s6e63m0.o obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6E63M0_SPI) +=3D panel-samsung-s6e63m0-spi= .o diff --git a/drivers/gpu/drm/panel/panel-samsung-s6e3ha8.c b/drivers/gpu/dr= m/panel/panel-samsung-s6e3ha8.c new file mode 100644 index 000000000000..e69943f0527e --- /dev/null +++ b/drivers/gpu/drm/panel/panel-samsung-s6e3ha8.c @@ -0,0 +1,350 @@ +// SPDX-License-Identifier: GPL-2.0-only +// +// Generated with linux-mdss-dsi-panel-driver-generator from vendor device= tree: +// Copyright (c) 2013, The Linux Foundation. All rights reserved. +// Copyright (c) 2024 Dzmitry Sankouski + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +struct s6e3ha8 { + struct drm_panel panel; + struct mipi_dsi_device *dsi; + struct drm_dsc_config dsc; + struct gpio_desc *reset_gpio; + struct regulator_bulk_data supplies[3]; +}; + +static inline +struct s6e3ha8 *to_s6e3ha8_amb577px01_wqhd(struct drm_panel *panel) +{ + return container_of(panel, struct s6e3ha8, panel); +} + +#define s6e3ha8_test_key_on_lvl2(ctx) \ + mipi_dsi_dcs_write_seq_multi(ctx, 0xf0, 0x5a, 0x5a) +#define s6e3ha8_test_key_off_lvl2(ctx) \ + mipi_dsi_dcs_write_seq_multi(ctx, 0xf0, 0xa5, 0xa5) +#define s6e3ha8_test_key_on_lvl3(ctx) \ + mipi_dsi_dcs_write_seq_multi(ctx, 0xfc, 0x5a, 0x5a) +#define s6e3ha8_test_key_off_lvl3(ctx) \ + mipi_dsi_dcs_write_seq_multi(ctx, 0xfc, 0xa5, 0xa5) +#define s6e3ha8_test_key_on_lvl1(ctx) \ + mipi_dsi_dcs_write_seq_multi(ctx, 0x9f, 0xa5, 0xa5) +#define s6e3ha8_test_key_off_lvl1(ctx) \ + mipi_dsi_dcs_write_seq_multi(ctx, 0x9f, 0x5a, 0x5a) +#define s6e3ha8_afc_off(ctx) \ + mipi_dsi_dcs_write_seq_multi(ctx, 0xe2, 0x00, 0x00) + +static void s6e3ha8_amb577px01_wqhd_reset(struct s6e3ha8 *priv) +{ + gpiod_set_value_cansleep(priv->reset_gpio, 1); + usleep_range(5000, 6000); + gpiod_set_value_cansleep(priv->reset_gpio, 0); + usleep_range(5000, 6000); + gpiod_set_value_cansleep(priv->reset_gpio, 1); + usleep_range(5000, 6000); +} + +static int s6e3ha8_amb577px01_wqhd_on(struct s6e3ha8 *priv) +{ + struct mipi_dsi_device *dsi =3D priv->dsi; + struct device *dev =3D &dsi->dev; + struct mipi_dsi_multi_context ctx =3D { .dsi =3D dsi }; + int ret; + + dsi->mode_flags |=3D MIPI_DSI_MODE_LPM; + + s6e3ha8_test_key_on_lvl1(&ctx); + s6e3ha8_test_key_on_lvl2(&ctx); + + ret =3D mipi_dsi_compression_mode(dsi, true); + if (ret < 0) { + dev_err(dev, "Failed to set compression mode: %d\n", ret); + return ret; + } + + s6e3ha8_test_key_off_lvl2(&ctx); + + ret =3D mipi_dsi_dcs_exit_sleep_mode(dsi); + if (ret < 0) { + dev_err(dev, "Failed to exit sleep mode: %d\n", ret); + return ret; + } + usleep_range(5000, 6000); + + s6e3ha8_test_key_on_lvl2(&ctx); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xf2, 0x13); + s6e3ha8_test_key_off_lvl2(&ctx); + + usleep_range(10000, 11000); + + s6e3ha8_test_key_on_lvl2(&ctx); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xf2, 0x13); + s6e3ha8_test_key_off_lvl2(&ctx); + + /* OMOK setting 1 (Initial setting) - Scaler Latch Setting Guide */ + s6e3ha8_test_key_on_lvl2(&ctx); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xb0, 0x07); + /* latch setting 1 : Scaler on/off & address setting & PPS setting -> Ima= ge update latch */ + mipi_dsi_dcs_write_seq_multi(&ctx, 0xf2, 0x3c, 0x10); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xb0, 0x0b); + /* latch setting 2 : Ratio change mode -> Image update latch */ + mipi_dsi_dcs_write_seq_multi(&ctx, 0xf2, 0x30); + /* OMOK setting 2 - Seamless setting guide : WQHD */ + mipi_dsi_dcs_write_seq_multi(&ctx, 0x2a, 0x00, 0x00, 0x05, 0x9f); /* CASE= T */ + mipi_dsi_dcs_write_seq_multi(&ctx, 0x2b, 0x00, 0x00, 0x0b, 0x8f); /* PASE= T */ + mipi_dsi_dcs_write_seq_multi(&ctx, 0xba, 0x01); /* scaler setup : scaler = off */ + s6e3ha8_test_key_off_lvl2(&ctx); + mipi_dsi_dcs_write_seq_multi(&ctx, 0x35, 0x00); /* TE Vsync ON */ + s6e3ha8_test_key_on_lvl2(&ctx); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xed, 0x4c); /* ERR_FG */ + s6e3ha8_test_key_off_lvl2(&ctx); + s6e3ha8_test_key_on_lvl3(&ctx); + /* FFC Setting 897.6Mbps */ + mipi_dsi_dcs_write_seq_multi(&ctx, 0xc5, 0x0d, 0x10, 0xb4, 0x3e, 0x01); + s6e3ha8_test_key_off_lvl3(&ctx); + s6e3ha8_test_key_on_lvl2(&ctx); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xb9, + 0x00, 0xb0, 0x81, 0x09, 0x00, 0x00, 0x00, + 0x11, 0x03); /* TSP HSYNC Setting */ + s6e3ha8_test_key_off_lvl2(&ctx); + s6e3ha8_test_key_on_lvl2(&ctx); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xb0, 0x03); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xf6, 0x43); + s6e3ha8_test_key_off_lvl2(&ctx); + s6e3ha8_test_key_on_lvl2(&ctx); + /* Brightness condition set */ + mipi_dsi_dcs_write_seq_multi(&ctx, 0xca, + 0x07, 0x00, 0x00, 0x00, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x00, 0x00, 0x00); + mipi_dsi_dcs_write_seq_multi(&ctx, 0xb1, 0x00, 0x0c); /* AID Set : 0% */ + mipi_dsi_dcs_write_seq_multi(&ctx, 0xb5, + 0x19, 0xdc, 0x16, 0x01, 0x34, 0x67, 0x9a, + 0xcd, 0x01, 0x22, 0x33, 0x44, 0x00, 0x00, + 0x05, 0x55, 0xcc, 0x0c, 0x01, 0x11, 0x11, + 0x10); /* MPS/ELVSS Setting */ + mipi_dsi_dcs_write_seq_multi(&ctx, 0xf4, 0xeb, 0x28); /* VINT */ + mipi_dsi_dcs_write_seq_multi(&ctx, 0xf7, 0x03); /* Gamma, LTPS(AID) updat= e */ + s6e3ha8_test_key_off_lvl2(&ctx); + s6e3ha8_test_key_off_lvl1(&ctx); + + return 0; +} + +static int s6e3ha8_enable(struct drm_panel *panel) +{ + struct s6e3ha8 *priv =3D to_s6e3ha8_amb577px01_wqhd(panel); + struct mipi_dsi_device *dsi =3D priv->dsi; + struct mipi_dsi_multi_context ctx =3D { .dsi =3D dsi }; + + s6e3ha8_test_key_on_lvl1(&ctx); + ctx.accum_err =3D mipi_dsi_dcs_set_display_on(dsi); + s6e3ha8_test_key_off_lvl1(&ctx); + + return ctx.accum_err; +} + +static int s6e3ha8_disable(struct drm_panel *panel) +{ + struct s6e3ha8 *priv =3D to_s6e3ha8_amb577px01_wqhd(panel); + struct mipi_dsi_device *dsi =3D priv->dsi; + struct mipi_dsi_multi_context ctx =3D { .dsi =3D dsi }; + + s6e3ha8_test_key_on_lvl1(&ctx); + ctx.accum_err =3D mipi_dsi_dcs_set_display_off(dsi); + s6e3ha8_test_key_off_lvl1(&ctx); + msleep(20); + + s6e3ha8_test_key_on_lvl2(&ctx); + s6e3ha8_afc_off(&ctx); + s6e3ha8_test_key_off_lvl2(&ctx); + + msleep(160); + + return 0; +} + +static int s6e3ha8_amb577px01_wqhd_prepare(struct drm_panel *panel) +{ + struct s6e3ha8 *priv =3D to_s6e3ha8_amb577px01_wqhd(panel); + struct mipi_dsi_device *dsi =3D priv->dsi; + struct device *dev =3D &dsi->dev; + struct mipi_dsi_multi_context ctx =3D { .dsi =3D dsi }; + struct drm_dsc_picture_parameter_set pps; + int ret; + + ret =3D regulator_bulk_enable(ARRAY_SIZE(priv->supplies), priv->supplies); + if (ret < 0) + return ret; + msleep(120); + s6e3ha8_amb577px01_wqhd_reset(priv); + ret =3D s6e3ha8_amb577px01_wqhd_on(priv); + + if (ret < 0) { + dev_err(dev, "Failed to initialize panel: %d\n", ret); + gpiod_set_value_cansleep(priv->reset_gpio, 1); + goto err; + } + + drm_dsc_pps_payload_pack(&pps, &priv->dsc); + + s6e3ha8_test_key_on_lvl1(&ctx); + ret =3D mipi_dsi_picture_parameter_set(priv->dsi, &pps); + if (ret < 0) { + dev_err(panel->dev, "failed to transmit PPS: %d\n", ret); + return ret; + } + s6e3ha8_test_key_off_lvl1(&ctx); + + msleep(28); + + return 0; +err: + regulator_bulk_disable(ARRAY_SIZE(priv->supplies), priv->supplies); + return ret; +} + +static int s6e3ha8_amb577px01_wqhd_unprepare(struct drm_panel *panel) +{ + struct s6e3ha8 *priv =3D to_s6e3ha8_amb577px01_wqhd(panel); + + return regulator_bulk_disable(ARRAY_SIZE(priv->supplies), priv->supplies); +} + +static const struct drm_display_mode s6e3ha8_amb577px01_wqhd_mode =3D { + .clock =3D (1440 + 116 + 44 + 120) * (2960 + 120 + 80 + 124) * 60 / 1000, + .hdisplay =3D 1440, + .hsync_start =3D 1440 + 116, + .hsync_end =3D 1440 + 116 + 44, + .htotal =3D 1440 + 116 + 44 + 120, + .vdisplay =3D 2960, + .vsync_start =3D 2960 + 120, + .vsync_end =3D 2960 + 120 + 80, + .vtotal =3D 2960 + 120 + 80 + 124, + .width_mm =3D 64, + .height_mm =3D 132, +}; + +static int s6e3ha8_amb577px01_wqhd_get_modes(struct drm_panel *panel, + struct drm_connector *connector) +{ + return drm_connector_helper_get_modes_fixed(connector, &s6e3ha8_amb577px0= 1_wqhd_mode); +} + +static const struct drm_panel_funcs s6e3ha8_amb577px01_wqhd_panel_funcs = =3D { + .prepare =3D s6e3ha8_amb577px01_wqhd_prepare, + .unprepare =3D s6e3ha8_amb577px01_wqhd_unprepare, + .get_modes =3D s6e3ha8_amb577px01_wqhd_get_modes, + .enable =3D s6e3ha8_enable, + .disable =3D s6e3ha8_disable, +}; + +static int s6e3ha8_amb577px01_wqhd_probe(struct mipi_dsi_device *dsi) +{ + struct device *dev =3D &dsi->dev; + struct s6e3ha8 *priv; + int ret; + + priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->supplies[0].supply =3D "vdd3"; + priv->supplies[1].supply =3D "vci"; + priv->supplies[2].supply =3D "vddr"; + + ret =3D devm_regulator_bulk_get(dev, ARRAY_SIZE(priv->supplies), + priv->supplies); + if (ret < 0) { + dev_err(dev, "failed to get regulators: %d\n", ret); + return ret; + } + + priv->reset_gpio =3D devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH); + if (IS_ERR(priv->reset_gpio)) + return dev_err_probe(dev, PTR_ERR(priv->reset_gpio), + "Failed to get reset-gpios\n"); + + priv->dsi =3D dsi; + mipi_dsi_set_drvdata(dsi, priv); + + dsi->lanes =3D 4; + dsi->format =3D MIPI_DSI_FMT_RGB888; + dsi->mode_flags =3D MIPI_DSI_CLOCK_NON_CONTINUOUS | + MIPI_DSI_MODE_VIDEO_NO_HFP | MIPI_DSI_MODE_VIDEO_NO_HBP | + MIPI_DSI_MODE_VIDEO_NO_HSA | MIPI_DSI_MODE_NO_EOT_PACKET; + + drm_panel_init(&priv->panel, dev, &s6e3ha8_amb577px01_wqhd_panel_funcs, + DRM_MODE_CONNECTOR_DSI); + priv->panel.prepare_prev_first =3D true; + + drm_panel_add(&priv->panel); + + /* This panel only supports DSC; unconditionally enable it */ + dsi->dsc =3D &priv->dsc; + + priv->dsc.dsc_version_major =3D 1; + priv->dsc.dsc_version_minor =3D 1; + + priv->dsc.slice_height =3D 40; + priv->dsc.slice_width =3D 720; + WARN_ON(1440 % priv->dsc.slice_width); + priv->dsc.slice_count =3D 1440 / priv->dsc.slice_width; + priv->dsc.bits_per_component =3D 8; + priv->dsc.bits_per_pixel =3D 8 << 4; /* 4 fractional bits */ + priv->dsc.block_pred_enable =3D true; + + ret =3D mipi_dsi_attach(dsi); + if (ret < 0) { + dev_err(dev, "Failed to attach to DSI host: %d\n", ret); + drm_panel_remove(&priv->panel); + return ret; + } + + return 0; +} + +static void s6e3ha8_amb577px01_wqhd_remove(struct mipi_dsi_device *dsi) +{ + struct s6e3ha8 *priv =3D mipi_dsi_get_drvdata(dsi); + int ret; + + ret =3D mipi_dsi_detach(dsi); + if (ret < 0) + dev_err(&dsi->dev, "Failed to detach from DSI host: %d\n", ret); + + drm_panel_remove(&priv->panel); +} + +static const struct of_device_id s6e3ha8_amb577px01_wqhd_of_match[] =3D { + { .compatible =3D "samsung,s6e3ha8" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, s6e3ha8_amb577px01_wqhd_of_match); + +static struct mipi_dsi_driver s6e3ha8_amb577px01_wqhd_driver =3D { + .probe =3D s6e3ha8_amb577px01_wqhd_probe, + .remove =3D s6e3ha8_amb577px01_wqhd_remove, + .driver =3D { + .name =3D "panel-s6e3ha8", + .of_match_table =3D s6e3ha8_amb577px01_wqhd_of_match, + }, +}; +module_mipi_dsi_driver(s6e3ha8_amb577px01_wqhd_driver); + +MODULE_AUTHOR("Dzmitry Sankouski "); +MODULE_DESCRIPTION("DRM driver for S6E3HA8 panel"); +MODULE_LICENSE("GPL"); --=20 2.39.2