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Fri, 13 Sep 2024 16:32:32 -0400 (EDT) From: Jiaxun Yang Date: Fri, 13 Sep 2024 21:32:04 +0100 Subject: [PATCH v3 1/4] LoongArch: Probe more CPU features from CPUCFG Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240913-iocsr-v3-1-81a57f60350d@flygoat.com> References: <20240913-iocsr-v3-0-81a57f60350d@flygoat.com> In-Reply-To: <20240913-iocsr-v3-0-81a57f60350d@flygoat.com> To: Huacai Chen , WANG Xuerui , "Rafael J. Wysocki" , Viresh Kumar , Thomas Gleixner , Thomas Bogendoerfer Cc: loongarch@lists.linux.dev, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-mips@vger.kernel.org, kvm@vger.kernel.org, Jiaxun Yang X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=5981; i=jiaxun.yang@flygoat.com; h=from:subject:message-id; bh=R3vGKKP2k/8FDG76DaGfeG84fWyFmyAZsDiDvQedQFE=; b=owGbwMvMwCXmXMhTe71c8zDjabUkhrQnC6M/3C8vnRJiedr55pnM5BU1v/lYfdT3XGc5GLsw2 FmhS0Oko5SFQYyLQVZMkSVEQKlvQ+PFBdcfZP2BmcPKBDKEgYtTACby35SRYes8R400jk+v1r0Q 28hV8Tox1Dw9dPs3ie8BPxLu7IplbGZk+NKRIP2ph3m2Q+2sWc8ELjv//n9t0Z/D6Zyvf/s95fB X5QIA X-Developer-Key: i=jiaxun.yang@flygoat.com; a=openpgp; fpr=980379BEFEBFBF477EA04EF9C111949073FC0F67 Probe ISA level, TLB, IOCSR information from CPUCFG to improve kernel resilience to different core implementations. Signed-off-by: Jiaxun Yang --- arch/loongarch/include/asm/cpu.h | 4 ++ arch/loongarch/include/asm/loongarch.h | 3 +- arch/loongarch/kernel/cpu-probe.c | 70 +++++++++++++++++++++---------= ---- 3 files changed, 49 insertions(+), 28 deletions(-) diff --git a/arch/loongarch/include/asm/cpu.h b/arch/loongarch/include/asm/= cpu.h index 843f9c4ec980..251a15439cff 100644 --- a/arch/loongarch/include/asm/cpu.h +++ b/arch/loongarch/include/asm/cpu.h @@ -100,6 +100,8 @@ enum cpu_type_enum { #define CPU_FEATURE_HYPERVISOR 25 /* CPU has hypervisor (running in VM) */ #define CPU_FEATURE_PTW 26 /* CPU has hardware page table walker */ #define CPU_FEATURE_AVECINT 27 /* CPU has avec interrupt */ +#define CPU_FEATURE_IOCSR 28 /* CPU has IOCSR */ +#define CPU_FEATURE_LSPW 29 /* CPU has LSPW */ =20 #define LOONGARCH_CPU_CPUCFG BIT_ULL(CPU_FEATURE_CPUCFG) #define LOONGARCH_CPU_LAM BIT_ULL(CPU_FEATURE_LAM) @@ -129,5 +131,7 @@ enum cpu_type_enum { #define LOONGARCH_CPU_HYPERVISOR BIT_ULL(CPU_FEATURE_HYPERVISOR) #define LOONGARCH_CPU_PTW BIT_ULL(CPU_FEATURE_PTW) #define LOONGARCH_CPU_AVECINT BIT_ULL(CPU_FEATURE_AVECINT) +#define LOONGARCH_CPU_IOCSR BIT_ULL(CPU_FEATURE_IOCSR) +#define LOONGARCH_CPU_LSPW BIT_ULL(CPU_FEATURE_LSPW) =20 #endif /* _ASM_CPU_H */ diff --git a/arch/loongarch/include/asm/loongarch.h b/arch/loongarch/includ= e/asm/loongarch.h index 631d249b3ef2..23af28f00c3c 100644 --- a/arch/loongarch/include/asm/loongarch.h +++ b/arch/loongarch/include/asm/loongarch.h @@ -60,8 +60,7 @@ #define CPUCFG0_PRID GENMASK(31, 0) =20 #define LOONGARCH_CPUCFG1 0x1 -#define CPUCFG1_ISGR32 BIT(0) -#define CPUCFG1_ISGR64 BIT(1) +#define CPUCFG1_ISA GENMASK(1, 0) #define CPUCFG1_PAGING BIT(2) #define CPUCFG1_IOCSR BIT(3) #define CPUCFG1_PABITS GENMASK(11, 4) diff --git a/arch/loongarch/kernel/cpu-probe.c b/arch/loongarch/kernel/cpu-= probe.c index 14f0449f5452..a5473bb673e5 100644 --- a/arch/loongarch/kernel/cpu-probe.c +++ b/arch/loongarch/kernel/cpu-probe.c @@ -92,11 +92,29 @@ static void cpu_probe_common(struct cpuinfo_loongarch *= c) unsigned long asid_mask; =20 c->options =3D LOONGARCH_CPU_CPUCFG | LOONGARCH_CPU_CSR | - LOONGARCH_CPU_TLB | LOONGARCH_CPU_VINT | LOONGARCH_CPU_WATCH; + LOONGARCH_CPU_VINT | LOONGARCH_CPU_WATCH; =20 elf_hwcap =3D HWCAP_LOONGARCH_CPUCFG; =20 config =3D read_cpucfg(LOONGARCH_CPUCFG1); + + switch (config & CPUCFG1_ISA) { + case 0: + set_isa(c, LOONGARCH_CPU_ISA_LA32R); + break; + case 1: + set_isa(c, LOONGARCH_CPU_ISA_LA32S); + break; + case 2: + set_isa(c, LOONGARCH_CPU_ISA_LA64); + break; + default: + pr_warn("Warning: unknown ISA level\n"); + } + if (config & CPUCFG1_PAGING) + c->options |=3D LOONGARCH_CPU_TLB; + if (config & CPUCFG1_IOCSR) + c->options |=3D LOONGARCH_CPU_IOCSR; if (config & CPUCFG1_UAL) { c->options |=3D LOONGARCH_CPU_UAL; elf_hwcap |=3D HWCAP_LOONGARCH_UAL; @@ -157,6 +175,8 @@ static void cpu_probe_common(struct cpuinfo_loongarch *= c) elf_hwcap |=3D HWCAP_LOONGARCH_LBT_MIPS; } #endif + if (config & CPUCFG2_LSPW) + c->options |=3D LOONGARCH_CPU_LSPW; =20 config =3D read_cpucfg(LOONGARCH_CPUCFG6); if (config & CPUCFG6_PMP) @@ -222,6 +242,7 @@ static inline void cpu_probe_loongson(struct cpuinfo_lo= ongarch *c, unsigned int { uint64_t *vendor =3D (void *)(&cpu_full_name[VENDOR_OFFSET]); uint64_t *cpuname =3D (void *)(&cpu_full_name[CPUNAME_OFFSET]); + const char *core_name =3D "Unknown"; =20 if (!__cpu_full_name[cpu]) __cpu_full_name[cpu] =3D cpu_full_name; @@ -229,43 +250,40 @@ static inline void cpu_probe_loongson(struct cpuinfo_= loongarch *c, unsigned int *vendor =3D iocsr_read64(LOONGARCH_IOCSR_VENDOR); *cpuname =3D iocsr_read64(LOONGARCH_IOCSR_CPUNAME); =20 - switch (c->processor_id & PRID_SERIES_MASK) { - case PRID_SERIES_LA132: + switch (BIT(fls(c->isa_level) - 1)) { + case LOONGARCH_CPU_ISA_LA32R: c->cputype =3D CPU_LOONGSON32; - set_isa(c, LOONGARCH_CPU_ISA_LA32S); - __cpu_family[cpu] =3D "Loongson-32bit"; - pr_info("32-bit Loongson Processor probed (LA132 Core)\n"); + __cpu_family[cpu] =3D "Loongson-32bit Reduced"; break; - case PRID_SERIES_LA264: + case LOONGARCH_CPU_ISA_LA32S: + c->cputype =3D CPU_LOONGSON32; + __cpu_family[cpu] =3D "Loongson-32bit Standard"; + break; + case LOONGARCH_CPU_ISA_LA64: c->cputype =3D CPU_LOONGSON64; - set_isa(c, LOONGARCH_CPU_ISA_LA64); __cpu_family[cpu] =3D "Loongson-64bit"; - pr_info("64-bit Loongson Processor probed (LA264 Core)\n"); + break; + } + + switch (c->processor_id & PRID_SERIES_MASK) { + case PRID_SERIES_LA132: + core_name =3D "LA132"; + break; + case PRID_SERIES_LA264: + core_name =3D "LA264"; break; case PRID_SERIES_LA364: - c->cputype =3D CPU_LOONGSON64; - set_isa(c, LOONGARCH_CPU_ISA_LA64); - __cpu_family[cpu] =3D "Loongson-64bit"; - pr_info("64-bit Loongson Processor probed (LA364 Core)\n"); + core_name =3D "LA364"; break; case PRID_SERIES_LA464: - c->cputype =3D CPU_LOONGSON64; - set_isa(c, LOONGARCH_CPU_ISA_LA64); - __cpu_family[cpu] =3D "Loongson-64bit"; - pr_info("64-bit Loongson Processor probed (LA464 Core)\n"); + core_name =3D "LA464"; break; case PRID_SERIES_LA664: - c->cputype =3D CPU_LOONGSON64; - set_isa(c, LOONGARCH_CPU_ISA_LA64); - __cpu_family[cpu] =3D "Loongson-64bit"; - pr_info("64-bit Loongson Processor probed (LA664 Core)\n"); + core_name =3D "LA664"; break; - default: /* Default to 64 bit */ - c->cputype =3D CPU_LOONGSON64; - set_isa(c, LOONGARCH_CPU_ISA_LA64); - __cpu_family[cpu] =3D "Loongson-64bit"; - pr_info("64-bit Loongson Processor probed (Unknown Core)\n"); } + + pr_info("%s Processor probed (%s Core)\n", __cpu_family[cpu], core_name); } =20 #ifdef CONFIG_64BIT --=20 2.46.0