From nobody Sat Nov 30 04:37:45 2024 Received: from mail-pj1-f51.google.com (mail-pj1-f51.google.com [209.85.216.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B779E1CFEBC for ; Thu, 12 Sep 2024 23:18:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726183107; cv=none; b=Ml44fOip7DP3JzM4TZD2TwLnRBFAdkXSgJKNM+IOLzvS2B3TdTQ/znogAhk/EZkc1IFrFnZlnGzqCWkRF2zsipOH0raxgYEuQh9dDxKLSDyyCHBt9Pn8Om4G+KqO2Mags5L0sneFSRKBaa96weTdQ5vv9FMpKCsGmlKP/kU2y9E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726183107; c=relaxed/simple; bh=MHg57NEd08ao1KxrRWOEic7Svy2JshSBZmUSR8/f4z8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=EXjdEIN0bNnB/WyouO0aomDssBA/rIvhfJr646DPQg6KZklpwXdsiMi4/+/WCeVBTKp16G6EdMb8lYZkQH86D94q5Zu8bzFI157AbMjwW7uh2AoYMzx2Y3AN3O/zQp2ZJdeMIgvHmq2J68zLzf8ALS+vGXolhqZE46ktUmSRTv4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=qByMt0Cm; arc=none smtp.client-ip=209.85.216.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="qByMt0Cm" Received: by mail-pj1-f51.google.com with SMTP id 98e67ed59e1d1-2d87176316eso1958170a91.0 for ; Thu, 12 Sep 2024 16:18:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1726183105; x=1726787905; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Tr63COK+U+RGXsHvnwpQo9tUUF56AGnmex8wAUb47lI=; b=qByMt0CmYfYa9ZDoWoahwdu0x++GxPncyM+Xyj48wMgJFDKuxuC3hNBnxrLt7N8TYb NRggY4lRBwKGl+fBk4uB52kj0OOJ1xisrJZO+cbYAaGwBBVWjgXs17AKn9c2arDyPoZw pe3qGlFa0hL9bVANAUAiAU1mZ6KHuTefRf9Lr7wEtKuOxCdrTqnPypv+VaN1PR7ShKK4 ftnaIk6+nN9QoX/BwNJ834wPxNJmVVxx/YmObpjxqj/qEirMSkDAAXlUAO3NlqJO7tIH X0Byn3yyK90s0MUAzDF4nHxFOkYx8x44W/KtXSeLJ7EZ6Z2EWNaOvbUDgIWsDL49kOx1 3P9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726183105; x=1726787905; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Tr63COK+U+RGXsHvnwpQo9tUUF56AGnmex8wAUb47lI=; b=oAeip9QwZ14ZUV4wSxlZV7r7rHDn/BaqE/7ljldBB6XM4XlTH7FiVVgb21r4EUvk2f K5p/CCouEPRqDM6+MCiwzyzIXGAp/EjYf0fqqmYnThD3BD4CDtenRG+R4Jd+TFgb66L6 Y/QBBFUs/DKe2cVJCVHK0kSlmX1C0rXgJj2xpcLfAitPUGX7w690iWkGqj22fXVG6EKG AXy/ntdhEsuWvkErJ1cDvhG/uX/H40xutm3ZMmmppQ2GlRvumfP5fLVjCtgaTY0OcVXi ESNfggDwnkhxdSkNT04cD1sOb77DSr9HEVyVIM+sD5zgbeW8q09+h97EPjTBgrk2rVwK ODgw== X-Forwarded-Encrypted: i=1; AJvYcCX0r9FHL33T+HVpcwz6s8MBqDTDEa9nKjA22x0Dx/5Yonge3+HzX+KOV+z19QdCIrgMzIPt0xfcC+Zp3TA=@vger.kernel.org X-Gm-Message-State: AOJu0Yyi1iHaECcCuLaO/UZ2YiSe2OOu32HKE/wePeFj2W/FWikbmNpB VCoh5nr6H02WDM7cLyRSiRjOB7zFPRpNJBSuSFvwaDm0QSQyPPV1COXVy22jeqfZNkBUHZbOD10 4 X-Google-Smtp-Source: AGHT+IEDlbanVmMoBHXIDtdzRNuiWJ0Gl4K78KpM2NYaBdsrPCDFJdZTucI/ImbEr5mpj8z5f/pv1g== X-Received: by 2002:a17:90a:62ca:b0:2d8:9fbe:6727 with SMTP id 98e67ed59e1d1-2db9fc1adabmr6645974a91.4.1726183104748; Thu, 12 Sep 2024 16:18:24 -0700 (PDT) Received: from debug.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2db6c1ac69asm3157591a91.0.2024.09.12.16.18.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Sep 2024 16:18:24 -0700 (PDT) From: Deepak Gupta To: paul.walmsley@sifive.com, palmer@sifive.com, conor@kernel.org, linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-fsdevel@vger.kernel.org, linux-mm@kvack.org, linux-arch@vger.kernel.org, linux-kselftest@vger.kernel.org Cc: corbet@lwn.net, palmer@dabbelt.com, aou@eecs.berkeley.edu, robh@kernel.org, krzk+dt@kernel.org, oleg@redhat.com, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, peterz@infradead.org, akpm@linux-foundation.org, arnd@arndb.de, ebiederm@xmission.com, kees@kernel.org, Liam.Howlett@oracle.com, vbabka@suse.cz, lorenzo.stoakes@oracle.com, shuah@kernel.org, brauner@kernel.org, samuel.holland@sifive.com, debug@rivosinc.com, andy.chiu@sifive.com, jerry.shih@sifive.com, greentime.hu@sifive.com, charlie@rivosinc.com, evan@rivosinc.com, cleger@rivosinc.com, xiao.w.wang@intel.com, ajones@ventanamicro.com, anup@brainfault.org, mchitale@ventanamicro.com, atishp@rivosinc.com, sameo@rivosinc.com, bjorn@rivosinc.com, alexghiti@rivosinc.com, david@redhat.com, libang.li@antgroup.com, jszhang@kernel.org, leobras@redhat.com, guoren@kernel.org, samitolvanen@google.com, songshuaishuai@tinylab.org, costa.shul@redhat.com, bhe@redhat.com, zong.li@sifive.com, puranjay@kernel.org, namcaov@gmail.com, antonb@tenstorrent.com, sorear@fastmail.com, quic_bjorande@quicinc.com, ancientmodern4@gmail.com, ben.dooks@codethink.co.uk, quic_zhonhan@quicinc.com, cuiyunhui@bytedance.com, yang.lee@linux.alibaba.com, ke.zhao@shingroup.cn, sunilvl@ventanamicro.com, tanzhasanwork@gmail.com, schwab@suse.de, dawei.li@shingroup.cn, rppt@kernel.org, willy@infradead.org, usama.anjum@collabora.com, osalvador@suse.de, ryan.roberts@arm.com, andrii@kernel.org, alx@kernel.org, catalin.marinas@arm.com, broonie@kernel.org, revest@chromium.org, bgray@linux.ibm.com, deller@gmx.de, zev@bewilderbeest.net Subject: [PATCH v4 18/30] prctl: arch-agnostic prctl for indirect branch tracking Date: Thu, 12 Sep 2024 16:16:37 -0700 Message-ID: <20240912231650.3740732-19-debug@rivosinc.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20240912231650.3740732-1-debug@rivosinc.com> References: <20240912231650.3740732-1-debug@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Three architectures (x86, aarch64, riscv) have support for indirect branch tracking feature in a very similar fashion. On a very high level, indirect branch tracking is a CPU feature where CPU tracks branches which uses memory operand to perform control transfer in program. As part of this tracking on indirect branches, CPU goes in a state where it expects a landing pad instr on target and if not found then CPU raises some fault (architecture dependent) x86 landing pad instr - `ENDBRANCH` aarch64 landing pad instr - `BTI` riscv landing instr - `lpad` Given that three major arches have support for indirect branch tracking, This patch makes `prctl` for indirect branch tracking arch agnostic. To allow userspace to enable this feature for itself, following prtcls are defined: - PR_GET_INDIR_BR_LP_STATUS: Gets current configured status for indirect branch tracking. - PR_SET_INDIR_BR_LP_STATUS: Sets a configuration for indirect branch tracking. Following status options are allowed - PR_INDIR_BR_LP_ENABLE: Enables indirect branch tracking on user thread. - PR_INDIR_BR_LP_DISABLE; Disables indirect branch tracking on user thread. - PR_LOCK_INDIR_BR_LP_STATUS: Locks configured status for indirect branch tracking for user thread. Signed-off-by: Deepak Gupta --- include/linux/cpu.h | 4 ++++ include/uapi/linux/prctl.h | 27 +++++++++++++++++++++++++++ kernel/sys.c | 30 ++++++++++++++++++++++++++++++ 3 files changed, 61 insertions(+) diff --git a/include/linux/cpu.h b/include/linux/cpu.h index bdcec1732445..eff56aae05d7 100644 --- a/include/linux/cpu.h +++ b/include/linux/cpu.h @@ -203,4 +203,8 @@ static inline bool cpu_mitigations_auto_nosmt(void) } #endif =20 +int arch_get_indir_br_lp_status(struct task_struct *t, unsigned long __use= r *status); +int arch_set_indir_br_lp_status(struct task_struct *t, unsigned long statu= s); +int arch_lock_indir_br_lp_status(struct task_struct *t, unsigned long stat= us); + #endif /* _LINUX_CPU_H_ */ diff --git a/include/uapi/linux/prctl.h b/include/uapi/linux/prctl.h index b8d7b6361754..41ffb53490a4 100644 --- a/include/uapi/linux/prctl.h +++ b/include/uapi/linux/prctl.h @@ -349,4 +349,31 @@ struct prctl_mm_map { */ #define PR_LOCK_SHADOW_STACK_STATUS 76 =20 +/* + * Get the current indirect branch tracking configuration for the current + * thread, this will be the value configured via PR_SET_INDIR_BR_LP_STATUS. + */ +#define PR_GET_INDIR_BR_LP_STATUS 77 + +/* + * Set the indirect branch tracking configuration. PR_INDIR_BR_LP_ENABLE w= ill + * enable cpu feature for user thread, to track all indirect branches and = ensure + * they land on arch defined landing pad instruction. + * x86 - If enabled, an indirect branch must land on `ENDBRANCH` instructi= on. + * arch64 - If enabled, an indirect branch must land on `BTI` instruction. + * riscv - If enabled, an indirect branch must land on `lpad` instruction. + * PR_INDIR_BR_LP_DISABLE will disable feature for user thread and indirect + * branches will no more be tracked by cpu to land on arch defined landing= pad + * instruction. + */ +#define PR_SET_INDIR_BR_LP_STATUS 78 +# define PR_INDIR_BR_LP_ENABLE (1UL << 0) + +/* + * Prevent further changes to the specified indirect branch tracking + * configuration. All bits may be locked via this call, including + * undefined bits. + */ +#define PR_LOCK_INDIR_BR_LP_STATUS 79 + #endif /* _LINUX_PRCTL_H */ diff --git a/kernel/sys.c b/kernel/sys.c index 7e0c10e867cf..5f88d358066d 100644 --- a/kernel/sys.c +++ b/kernel/sys.c @@ -2339,6 +2339,21 @@ int __weak arch_lock_shadow_stack_status(struct task= _struct *t, unsigned long st return -EINVAL; } =20 +int __weak arch_get_indir_br_lp_status(struct task_struct *t, unsigned lon= g __user *status) +{ + return -EINVAL; +} + +int __weak arch_set_indir_br_lp_status(struct task_struct *t, unsigned lon= g status) +{ + return -EINVAL; +} + +int __weak arch_lock_indir_br_lp_status(struct task_struct *t, unsigned lo= ng status) +{ + return -EINVAL; +} + #define PR_IO_FLUSHER (PF_MEMALLOC_NOIO | PF_LOCAL_THROTTLE) =20 #ifdef CONFIG_ANON_VMA_NAME @@ -2812,6 +2827,21 @@ SYSCALL_DEFINE5(prctl, int, option, unsigned long, a= rg2, unsigned long, arg3, return -EINVAL; error =3D arch_lock_shadow_stack_status(me, arg2); break; + case PR_GET_INDIR_BR_LP_STATUS: + if (arg3 || arg4 || arg5) + return -EINVAL; + error =3D arch_get_indir_br_lp_status(me, (unsigned long __user *) arg2); + break; + case PR_SET_INDIR_BR_LP_STATUS: + if (arg3 || arg4 || arg5) + return -EINVAL; + error =3D arch_set_indir_br_lp_status(me, arg2); + break; + case PR_LOCK_INDIR_BR_LP_STATUS: + if (arg3 || arg4 || arg5) + return -EINVAL; + error =3D arch_lock_indir_br_lp_status(me, arg2); + break; default: error =3D -EINVAL; break; --=20 2.45.0