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(unknown [10.28.34.196]) by maili.marvell.com (Postfix) with ESMTP id 99D2C3F7078; Thu, 12 Sep 2024 09:14:56 -0700 (PDT) From: Linu Cherian To: , , , CC: , , , , , , Linu Cherian Subject: [PATCH v2 net-next 1/2] octeontx2-af: Knobs for NPC default rule counters Date: Thu, 12 Sep 2024 21:44:49 +0530 Message-ID: <20240912161450.164402-2-lcherian@marvell.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240912161450.164402-1-lcherian@marvell.com> References: <20240912161450.164402-1-lcherian@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: 59kjHNmb02W9OUnYUgkjtIDYyzX4-3Rt X-Proofpoint-GUID: 59kjHNmb02W9OUnYUgkjtIDYyzX4-3Rt X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 Content-Type: text/plain; charset="utf-8" Add devlink knobs to enable/disable counters on NPC default rule entries. Introduce lowlevel variant of rvu_mcam_remove/add_counter_from/to_rule for better code reuse, which assumes necessary locks are taken at higher level. Sample command to enable default rule counters: devlink dev param set name npc_def_rule_cntr value true cmode runtime Sample command to read the counter: cat /sys/kernel/debug/cn10k/npc/mcam_rules Signed-off-by: Linu Cherian --- Changelog from v1: Removed wrong mutex_unlock invocations. .../net/ethernet/marvell/octeontx2/af/rvu.h | 8 +- .../marvell/octeontx2/af/rvu_devlink.c | 32 +++++ .../ethernet/marvell/octeontx2/af/rvu_npc.c | 134 ++++++++++++++++-- .../marvell/octeontx2/af/rvu_npc_fs.c | 36 ++--- 4 files changed, 171 insertions(+), 39 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h b/drivers/net/= ethernet/marvell/octeontx2/af/rvu.h index 43b1d83686d1..fb4b88e94649 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h @@ -526,6 +526,7 @@ struct rvu { struct mutex alias_lock; /* Serialize bar2 alias access */ int vfs; /* Number of VFs attached to RVU */ u16 vf_devid; /* VF devices id */ + bool def_rule_cntr_en; int nix_blkaddr[MAX_NIX_BLKS]; =20 /* Mbox */ @@ -961,7 +962,11 @@ void rvu_npc_disable_default_entries(struct rvu *rvu, = u16 pcifunc, int nixlf); void rvu_npc_enable_default_entries(struct rvu *rvu, u16 pcifunc, int nixl= f); void rvu_npc_update_flowkey_alg_idx(struct rvu *rvu, u16 pcifunc, int nixl= f, int group, int alg_idx, int mcam_index); - +void __rvu_mcam_remove_counter_from_rule(struct rvu *rvu, u16 pcifunc, + struct rvu_npc_mcam_rule *rule); +void __rvu_mcam_add_counter_to_rule(struct rvu *rvu, u16 pcifunc, + struct rvu_npc_mcam_rule *rule, + struct npc_install_flow_rsp *rsp); void rvu_npc_get_mcam_entry_alloc_info(struct rvu *rvu, u16 pcifunc, int blkaddr, int *alloc_cnt, int *enable_cnt); @@ -986,6 +991,7 @@ void npc_set_mcam_action(struct rvu *rvu, struct npc_mc= am *mcam, void npc_read_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam, int blkaddr, u16 src, struct mcam_entry *entry, u8 *intf, u8 *ena); +int npc_config_cntr_default_entries(struct rvu *rvu, bool enable); bool is_cgx_config_permitted(struct rvu *rvu, u16 pcifunc); bool is_mac_feature_supported(struct rvu *rvu, int pf, int feature); u32 rvu_cgx_get_fifolen(struct rvu *rvu); diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_devlink.c b/driv= ers/net/ethernet/marvell/octeontx2/af/rvu_devlink.c index 7498ab429963..9c26e19a860b 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_devlink.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_devlink.c @@ -1238,6 +1238,7 @@ enum rvu_af_dl_param_id { RVU_AF_DEVLINK_PARAM_ID_DWRR_MTU, RVU_AF_DEVLINK_PARAM_ID_NPC_MCAM_ZONE_PERCENT, RVU_AF_DEVLINK_PARAM_ID_NPC_EXACT_FEATURE_DISABLE, + RVU_AF_DEVLINK_PARAM_ID_NPC_DEF_RULE_CNTR_ENABLE, RVU_AF_DEVLINK_PARAM_ID_NIX_MAXLF, }; =20 @@ -1358,6 +1359,32 @@ static int rvu_af_dl_npc_mcam_high_zone_percent_vali= date(struct devlink *devlink return 0; } =20 +static int rvu_af_dl_npc_def_rule_cntr_get(struct devlink *devlink, u32 id, + struct devlink_param_gset_ctx *ctx) +{ + struct rvu_devlink *rvu_dl =3D devlink_priv(devlink); + struct rvu *rvu =3D rvu_dl->rvu; + + ctx->val.vbool =3D rvu->def_rule_cntr_en; + + return 0; +} + +static int rvu_af_dl_npc_def_rule_cntr_set(struct devlink *devlink, u32 id, + struct devlink_param_gset_ctx *ctx, + struct netlink_ext_ack *extack) +{ + struct rvu_devlink *rvu_dl =3D devlink_priv(devlink); + struct rvu *rvu =3D rvu_dl->rvu; + int err; + + err =3D npc_config_cntr_default_entries(rvu, ctx->val.vbool); + if (!err) + rvu->def_rule_cntr_en =3D ctx->val.vbool; + + return err; +} + static int rvu_af_dl_nix_maxlf_get(struct devlink *devlink, u32 id, struct devlink_param_gset_ctx *ctx) { @@ -1444,6 +1471,11 @@ static const struct devlink_param rvu_af_dl_params[]= =3D { rvu_af_dl_npc_mcam_high_zone_percent_get, rvu_af_dl_npc_mcam_high_zone_percent_set, rvu_af_dl_npc_mcam_high_zone_percent_validate), + DEVLINK_PARAM_DRIVER(RVU_AF_DEVLINK_PARAM_ID_NPC_DEF_RULE_CNTR_ENABLE, + "npc_def_rule_cntr", DEVLINK_PARAM_TYPE_BOOL, + BIT(DEVLINK_PARAM_CMODE_RUNTIME), + rvu_af_dl_npc_def_rule_cntr_get, + rvu_af_dl_npc_def_rule_cntr_set, NULL), DEVLINK_PARAM_DRIVER(RVU_AF_DEVLINK_PARAM_ID_NIX_MAXLF, "nix_maxlf", DEVLINK_PARAM_TYPE_U16, BIT(DEVLINK_PARAM_CMODE_RUNTIME), diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c b/drivers/= net/ethernet/marvell/octeontx2/af/rvu_npc.c index 97722ce8c4cb..9e39c3149a4f 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c @@ -2691,6 +2691,51 @@ void npc_mcam_rsrcs_reserve(struct rvu *rvu, int blk= addr, int entry_idx) npc_mcam_set_bit(mcam, entry_idx); } =20 +int npc_config_cntr_default_entries(struct rvu *rvu, bool enable) +{ + struct npc_install_flow_rsp rsp =3D { 0 }; + struct npc_mcam *mcam =3D &rvu->hw->mcam; + struct rvu_npc_mcam_rule *rule; + int blkaddr; + + blkaddr =3D rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); + if (blkaddr < 0) + return -EINVAL; + + mutex_lock(&mcam->lock); + list_for_each_entry(rule, &mcam->mcam_rules, list) { + if (!is_mcam_entry_enabled(rvu, mcam, blkaddr, rule->entry)) + continue; + if (!rule->default_rule) + continue; + if (enable && !rule->has_cntr) { /* Alloc and map new counter */ + __rvu_mcam_add_counter_to_rule(rvu, rule->owner, + rule, &rsp); + if (rsp.counter < 0) { + dev_err(rvu->dev, "%s: Err to allocate cntr for default rule (err=3D%d= )\n", + __func__, rsp.counter); + break; + } + npc_map_mcam_entry_and_cntr(rvu, mcam, blkaddr, + rule->entry, rsp.counter); + } + + if (enable && rule->has_cntr) /* Reset counter before use */ { + rvu_write64(rvu, blkaddr, + NPC_AF_MATCH_STATX(rule->cntr), 0x0); + continue; + } + + if (!enable && rule->has_cntr) /* Free and unmap counter */ { + __rvu_mcam_remove_counter_from_rule(rvu, rule->owner, + rule); + } + } + mutex_unlock(&mcam->lock); + + return 0; +} + int rvu_mbox_handler_npc_mcam_alloc_entry(struct rvu *rvu, struct npc_mcam_alloc_entry_req *req, struct npc_mcam_alloc_entry_rsp *rsp) @@ -2975,9 +3020,9 @@ int rvu_mbox_handler_npc_mcam_shift_entry(struct rvu = *rvu, return rc; } =20 -int rvu_mbox_handler_npc_mcam_alloc_counter(struct rvu *rvu, - struct npc_mcam_alloc_counter_req *req, - struct npc_mcam_alloc_counter_rsp *rsp) +static int __npc_mcam_alloc_counter(struct rvu *rvu, + struct npc_mcam_alloc_counter_req *req, + struct npc_mcam_alloc_counter_rsp *rsp) { struct npc_mcam *mcam =3D &rvu->hw->mcam; u16 pcifunc =3D req->hdr.pcifunc; @@ -2998,11 +3043,9 @@ int rvu_mbox_handler_npc_mcam_alloc_counter(struct r= vu *rvu, if (!req->contig && req->count > NPC_MAX_NONCONTIG_COUNTERS) return NPC_MCAM_INVALID_REQ; =20 - mutex_lock(&mcam->lock); =20 /* Check if unused counters are available or not */ if (!rvu_rsrc_free_count(&mcam->counters)) { - mutex_unlock(&mcam->lock); return NPC_MCAM_ALLOC_FAILED; } =20 @@ -3035,12 +3078,27 @@ int rvu_mbox_handler_npc_mcam_alloc_counter(struct = rvu *rvu, } } =20 - mutex_unlock(&mcam->lock); return 0; } =20 -int rvu_mbox_handler_npc_mcam_free_counter(struct rvu *rvu, - struct npc_mcam_oper_counter_req *req, struct msg_rsp *rsp) +int rvu_mbox_handler_npc_mcam_alloc_counter(struct rvu *rvu, + struct npc_mcam_alloc_counter_req *req, + struct npc_mcam_alloc_counter_rsp *rsp) +{ + struct npc_mcam *mcam =3D &rvu->hw->mcam; + int err; + + mutex_lock(&mcam->lock); + + err =3D __npc_mcam_alloc_counter(rvu, req, rsp); + + mutex_unlock(&mcam->lock); + return err; +} + +static int __npc_mcam_free_counter(struct rvu *rvu, + struct npc_mcam_oper_counter_req *req, + struct msg_rsp *rsp) { struct npc_mcam *mcam =3D &rvu->hw->mcam; u16 index, entry =3D 0; @@ -3050,10 +3108,8 @@ int rvu_mbox_handler_npc_mcam_free_counter(struct rv= u *rvu, if (blkaddr < 0) return NPC_MCAM_INVALID_REQ; =20 - mutex_lock(&mcam->lock); err =3D npc_mcam_verify_counter(mcam, req->hdr.pcifunc, req->cntr); if (err) { - mutex_unlock(&mcam->lock); return err; } =20 @@ -3077,10 +3133,66 @@ int rvu_mbox_handler_npc_mcam_free_counter(struct r= vu *rvu, index, req->cntr); } =20 - mutex_unlock(&mcam->lock); return 0; } =20 +int rvu_mbox_handler_npc_mcam_free_counter(struct rvu *rvu, + struct npc_mcam_oper_counter_req *req, struct msg_rsp *rsp) +{ + struct npc_mcam *mcam =3D &rvu->hw->mcam; + int err; + + mutex_lock(&mcam->lock); + + err =3D __npc_mcam_free_counter(rvu, req, rsp); + + mutex_unlock(&mcam->lock); + + return err; +} + +void __rvu_mcam_remove_counter_from_rule(struct rvu *rvu, u16 pcifunc, + struct rvu_npc_mcam_rule *rule) +{ + struct npc_mcam_oper_counter_req free_req =3D { 0 }; + struct msg_rsp free_rsp; + + if (!rule->has_cntr) + return; + + free_req.hdr.pcifunc =3D pcifunc; + free_req.cntr =3D rule->cntr; + + __npc_mcam_free_counter(rvu, &free_req, &free_rsp); + rule->has_cntr =3D false; +} + +void __rvu_mcam_add_counter_to_rule(struct rvu *rvu, u16 pcifunc, + struct rvu_npc_mcam_rule *rule, + struct npc_install_flow_rsp *rsp) +{ + struct npc_mcam_alloc_counter_req cntr_req =3D { 0 }; + struct npc_mcam_alloc_counter_rsp cntr_rsp =3D { 0 }; + int err; + + cntr_req.hdr.pcifunc =3D pcifunc; + cntr_req.contig =3D true; + cntr_req.count =3D 1; + + /* we try to allocate a counter to track the stats of this + * rule. If counter could not be allocated then proceed + * without counter because counters are limited than entries. + */ + err =3D __npc_mcam_alloc_counter(rvu, &cntr_req, &cntr_rsp); + if (!err && cntr_rsp.count) { + rule->cntr =3D cntr_rsp.cntr; + rule->has_cntr =3D true; + rsp->counter =3D rule->cntr; + } else { + rsp->counter =3D err; + } +} + int rvu_mbox_handler_npc_mcam_unmap_counter(struct rvu *rvu, struct npc_mcam_unmap_counter_req *req, struct msg_rsp *rsp) { diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c b/drive= rs/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c index 150635de2bd5..7a1c18b1486d 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c @@ -1081,44 +1081,26 @@ static void rvu_mcam_add_rule(struct npc_mcam *mcam, static void rvu_mcam_remove_counter_from_rule(struct rvu *rvu, u16 pcifunc, struct rvu_npc_mcam_rule *rule) { - struct npc_mcam_oper_counter_req free_req =3D { 0 }; - struct msg_rsp free_rsp; + struct npc_mcam *mcam =3D &rvu->hw->mcam; =20 - if (!rule->has_cntr) - return; + mutex_lock(&mcam->lock); =20 - free_req.hdr.pcifunc =3D pcifunc; - free_req.cntr =3D rule->cntr; + __rvu_mcam_remove_counter_from_rule(rvu, pcifunc, rule); =20 - rvu_mbox_handler_npc_mcam_free_counter(rvu, &free_req, &free_rsp); - rule->has_cntr =3D false; + mutex_unlock(&mcam->lock); } =20 static void rvu_mcam_add_counter_to_rule(struct rvu *rvu, u16 pcifunc, struct rvu_npc_mcam_rule *rule, struct npc_install_flow_rsp *rsp) { - struct npc_mcam_alloc_counter_req cntr_req =3D { 0 }; - struct npc_mcam_alloc_counter_rsp cntr_rsp =3D { 0 }; - int err; + struct npc_mcam *mcam =3D &rvu->hw->mcam; =20 - cntr_req.hdr.pcifunc =3D pcifunc; - cntr_req.contig =3D true; - cntr_req.count =3D 1; + mutex_lock(&mcam->lock); =20 - /* we try to allocate a counter to track the stats of this - * rule. If counter could not be allocated then proceed - * without counter because counters are limited than entries. - */ - err =3D rvu_mbox_handler_npc_mcam_alloc_counter(rvu, &cntr_req, - &cntr_rsp); - if (!err && cntr_rsp.count) { - rule->cntr =3D cntr_rsp.cntr; - rule->has_cntr =3D true; - rsp->counter =3D rule->cntr; - } else { - rsp->counter =3D err; - } + __rvu_mcam_add_counter_to_rule(rvu, pcifunc, rule, rsp); + + mutex_unlock(&mcam->lock); } =20 static int npc_mcast_update_action_index(struct rvu *rvu, struct npc_insta= ll_flow_req *req, --=20 2.34.1 From nobody Sat Nov 30 02:35:33 2024 Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A9EEC149C50; Thu, 12 Sep 2024 16:15:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=67.231.148.174 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726157724; cv=none; b=fsMvtovYa+9Gi1CHADn9Y2VHlydxP2pODZXA1bdZL5zsPs9n2QwQRT+0f+FWNUVoEzXcjlJarrJC/WAGbivXKAaWTTYHGbCfbZqMg7OdMIqTuB1BTKpUKmnFLc3V+3HYIWCKqGaaotnTl4KKJ5QmnHrkbMZIEw5ZsI7pcRBFi0U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726157724; c=relaxed/simple; bh=6DixLDMe79fRUKZY2/B+7LSqGAnFPKKPILEqIZ6FtCs=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ryGbB0pr7b2LAFiu0AjiZSF1h/PCXOmAcWMZkOnEWiWJntZ0IXd6v8F+s/r0CtSXEDPgo84lp7y71PgayCcMg/fOV0XZDkpcNsIav2zcoqblx8GAo0B7JkpgdpMMBsMs2jNNBQ+FRMnzamI4YiRCnUDjYIIl0h/ezqcJtHQvn5Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com; spf=pass smtp.mailfrom=marvell.com; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b=bIU+7y45; arc=none smtp.client-ip=67.231.148.174 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=marvell.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b="bIU+7y45" Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 48CCIopp029838; Thu, 12 Sep 2024 09:15:04 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=pfpt0220; bh=S 3bgQqdr8mYs+jODxqTmrfuLs8FRU/YqAfIspUafpbU=; b=bIU+7y45L4eAtldHL MebT6BeB2rL5poAgZp34VNiJpZ29AoUof1nsxEh/k+nVP/okoaq8p2amvJxs+IMa KZHuO2Wqx9BLMU08jIdWmR4VB8X3/ABOFHZosMoFtuysWt2v7d0oj9Z+KKC+ipD6 RcyIyFFfrMFbuJJsjdD0GiQtMpW86o1JHt/cZTng2hze9EQx6DA2j5GSslmqX3N9 FxzvCROmjEpPObEBIQrSpwJuJmwUPs5lipt/d3C7Z3Rl8DvyukfS5NDc//kT5Je8 Nu5MaKdRaXcSLjjSw+vpb1O6A1wxGrF1e6A8hgzu+uskQWpgjnUWhqyyWAh+4lOK oIRqQ== Received: from dc5-exch05.marvell.com ([199.233.59.128]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 41k17vrwep-2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 12 Sep 2024 09:15:04 -0700 (PDT) Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Thu, 12 Sep 2024 09:15:03 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Thu, 12 Sep 2024 09:15:03 -0700 Received: from virtx40.. (unknown [10.28.34.196]) by maili.marvell.com (Postfix) with ESMTP id 361DD3F7078; Thu, 12 Sep 2024 09:14:59 -0700 (PDT) From: Linu Cherian To: , , , CC: , , , , , , Linu Cherian Subject: [PATCH v2 net-next 2/2] octeontx2-af: debugfs: Add Channel info to RPM map Date: Thu, 12 Sep 2024 21:44:50 +0530 Message-ID: <20240912161450.164402-3-lcherian@marvell.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240912161450.164402-1-lcherian@marvell.com> References: <20240912161450.164402-1-lcherian@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: NRzrfN6q-UDagD1sGYHqCqQm53kOxnif X-Proofpoint-ORIG-GUID: NRzrfN6q-UDagD1sGYHqCqQm53kOxnif X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 Content-Type: text/plain; charset="utf-8" Display channel info in the RPM map debugfs output. With this, cat /sys/kernel/debug/cn10k/rvu_pf_rpm_map would display channel number for each device in addition to the existing data. Sample output: PCI dev RVU PF Func NIX block rpm LMAC CHAN 0002:02:00.0 0x400 NIX0 rpm0 LMAC0 256 Signed-off-by: Linu Cherian --- Changelog from v1: No changes .../net/ethernet/marvell/octeontx2/af/rvu_debugfs.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c b/driv= ers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c index 4a4ef5bd9e0b..87ba77e5026a 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c @@ -838,10 +838,10 @@ RVU_DEBUG_FOPS(rsrc_status, rsrc_attach_status, NULL); =20 static int rvu_dbg_rvu_pf_cgx_map_display(struct seq_file *filp, void *unu= sed) { + char cgx[10], lmac[10], chan[10]; struct rvu *rvu =3D filp->private; struct pci_dev *pdev =3D NULL; struct mac_ops *mac_ops; - char cgx[10], lmac[10]; struct rvu_pfvf *pfvf; int pf, domain, blkid; u8 cgx_id, lmac_id; @@ -852,7 +852,7 @@ static int rvu_dbg_rvu_pf_cgx_map_display(struct seq_fi= le *filp, void *unused) /* There can be no CGX devices at all */ if (!mac_ops) return 0; - seq_printf(filp, "PCI dev\t\tRVU PF Func\tNIX block\t%s\tLMAC\n", + seq_printf(filp, "PCI dev\t\tRVU PF Func\tNIX block\t%s\tLMAC\tCHAN\n", mac_ops->name); for (pf =3D 0; pf < rvu->hw->total_pfs; pf++) { if (!is_pf_cgxmapped(rvu, pf)) @@ -876,8 +876,11 @@ static int rvu_dbg_rvu_pf_cgx_map_display(struct seq_f= ile *filp, void *unused) &lmac_id); sprintf(cgx, "%s%d", mac_ops->name, cgx_id); sprintf(lmac, "LMAC%d", lmac_id); - seq_printf(filp, "%s\t0x%x\t\tNIX%d\t\t%s\t%s\n", - dev_name(&pdev->dev), pcifunc, blkid, cgx, lmac); + sprintf(chan, "%d", + rvu_nix_chan_cgx(rvu, cgx_id, lmac_id, 0)); + seq_printf(filp, "%s\t0x%x\t\tNIX%d\t\t%s\t%s\t%s\n", + dev_name(&pdev->dev), pcifunc, blkid, cgx, lmac, + chan); =20 pci_dev_put(pdev); } --=20 2.34.1