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charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-ORIG-GUID: iIinlky0IaAJSWQukaIerbmi5VUT-cWl X-Proofpoint-GUID: iIinlky0IaAJSWQukaIerbmi5VUT-cWl X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 suspectscore=0 adultscore=0 bulkscore=0 priorityscore=1501 spamscore=0 malwarescore=0 mlxlogscore=999 phishscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2408220000 definitions=main-2409120088 Add dt bindings for AD7779 8-channel, simultaneous sampling ADC family with eight full =CE=A3-=CE=94 ADCs on chip and ultra-low input current to allow direct sensor connection. Signed-off-by: Ramona Alexandra Nechita --- .../bindings/iio/adc/adi,ad7779.yaml | 84 +++++++++++++++++++ 1 file changed, 84 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/adc/adi,ad7779.ya= ml diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7779.yaml b/Do= cumentation/devicetree/bindings/iio/adc/adi,ad7779.yaml new file mode 100644 index 000000000000..0ed5ec5dd8fe --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7779.yaml @@ -0,0 +1,84 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/adi,ad7779.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices AD777X family 8-Channel, 24-Bit, Simultaneous Sampli= ng ADCs + +maintainers: + - Ramona Nechita + +description: | + The AD777X family consist of 8-channel, simultaneous sampling analog-to- + digital converter (ADC). Eight full =CE=A3-=CE=94 ADCs are on-chip. The + AD7771 provides an ultralow input current to allow direct sensor + connection. Each input channel has a programmable gain stage + allowing gains of 1, 2, 4, and 8 to map lower amplitude sensor + outputs into the full-scale ADC input range, maximizing the + dynamic range of the signal chain. + + https://www.analog.com/media/en/technical-documentation/data-sheets/ad77= 70.pdf + https://www.analog.com/media/en/technical-documentation/data-sheets/ad77= 71.pdf + https://www.analog.com/media/en/technical-documentation/data-sheets/ad77= 79.pdf + +$ref: /schemas/spi/spi-peripheral-props.yaml# + +properties: + compatible: + enum: + - adi,ad7770 + - adi,ad7771 + - adi,ad7779 + + reg: + maxItems: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + clocks: + maxItems: 1 + + interrupts: + maxItems: 1 + description: + Interrupt line for DRDY signal which indicates the end of conversion + independently of the interface selected to read back the =CE=A3-=E2= =88=86 conversion. + + start-gpios: + description: + Pin that controls start synchronization pulse. + maxItems: 1 + + reset-gpios: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - interrupts + +unevaluatedProperties: false + +examples: + - | + #include + spi { + #address-cells =3D <1>; + #size-cells =3D <0>; + + adc@0 { + compatible =3D "adi,ad7779"; + reg =3D <0>; + vref-supply =3D <&vref>; + start-gpios =3D <&gpio0 87 GPIO_ACTIVE_LOW>; + reset-gpios =3D <&gpio0 93 GPIO_ACTIVE_LOW>; + clocks =3D <&adc_clk>; + }; + }; +... --=20 2.43.0 From nobody Sat Nov 30 02:30:42 2024 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 54D1E1A0BEE; Thu, 12 Sep 2024 12:17:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.135.77 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726143472; cv=none; b=kUC4uMtjyzFkJsRNH/z2B5fXd3QNUDqFLsaD08bDX//6HZ/Yxu/tQolkklgV8bf2HdY45SHEOGim3wgubFK9CI91ZoYYsep+HQhn7SwfzFTgeDTIkDaRSWN+VxP+vwgKBWuIB1iW9qjQzCdSiN9PgCd6FR/wkj32ut8x5SELZL8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; 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charset="utf-8" The filter mode / filter type property is used for ad4130 and ad7779 drivers, therefore the ABI doc file for ad4130 was removed, merging both of them in the sysfs-bus-iio. Signed-off-by: Ramona Alexandra Nechita --- Documentation/ABI/testing/sysfs-bus-iio | 22 +++++++++ .../ABI/testing/sysfs-bus-iio-adc-ad4130 | 46 ------------------- 2 files changed, 22 insertions(+), 46 deletions(-) delete mode 100644 Documentation/ABI/testing/sysfs-bus-iio-adc-ad4130 diff --git a/Documentation/ABI/testing/sysfs-bus-iio b/Documentation/ABI/te= sting/sysfs-bus-iio index 345d58535dc9..aac41e69aa43 100644 --- a/Documentation/ABI/testing/sysfs-bus-iio +++ b/Documentation/ABI/testing/sysfs-bus-iio @@ -2265,6 +2265,28 @@ Description: An example format is 16-bytes, 2-digits-per-byte, HEX-string representing the sensor unique ID number. =20 +What: /sys/bus/iio/devices/iio:deviceX/filter_type_available +What: /sys/bus/iio/devices/iio:deviceX/in_voltage-voltage_filter_mode_ava= ilable +KernelVersion: 6.1 +Contact: linux-iio@vger.kernel.org +Description: + Reading returns a list with the possible filter modes. Options + for the attribute: + * "sinc3" - The digital sinc3 filter. Moderate 1st conversion time. + Good noise performance. + * "sinc4" - Sinc 4. Excellent noise performance. Long + 1st conversion time. + * "sinc5" - The digital sinc5 filter. Excellent noise performance + * "sinc4+sinc1" - Sinc4 + averaging by 8. Low 1st conversion + time. + * "sinc3+rej60" - Sinc3 + 60Hz rejection. + * "sinc3+sinc1" - Sinc3 + averaging by 8. Low 1st conversion + time. + * "sinc3+pf1" - Sinc3 + device specific Post Filter 1. + * "sinc3+pf2" - Sinc3 + device specific Post Filter 2. + * "sinc3+pf3" - Sinc3 + device specific Post Filter 3. + * "sinc3+pf4" - Sinc3 + device specific Post Filter 4. + What: /sys/.../events/in_proximity_thresh_either_runningperiod KernelVersion: 6.6 Contact: linux-iio@vger.kernel.org diff --git a/Documentation/ABI/testing/sysfs-bus-iio-adc-ad4130 b/Documenta= tion/ABI/testing/sysfs-bus-iio-adc-ad4130 deleted file mode 100644 index f24ed6687e90..000000000000 --- a/Documentation/ABI/testing/sysfs-bus-iio-adc-ad4130 +++ /dev/null @@ -1,46 +0,0 @@ -What: /sys/bus/iio/devices/iio:deviceX/in_voltage-voltage_filter_mode_ava= ilable -KernelVersion: 6.2 -Contact: linux-iio@vger.kernel.org -Description: - Reading returns a list with the possible filter modes. - - * "sinc4" - Sinc 4. Excellent noise performance. Long - 1st conversion time. No natural 50/60Hz rejection. - - * "sinc4+sinc1" - Sinc4 + averaging by 8. Low 1st conversion - time. - - * "sinc3" - Sinc3. Moderate 1st conversion time. - Good noise performance. - - * "sinc3+rej60" - Sinc3 + 60Hz rejection. At a sampling - frequency of 50Hz, achieves simultaneous 50Hz and 60Hz - rejection. - - * "sinc3+sinc1" - Sinc3 + averaging by 8. Low 1st conversion - time. Best used with a sampling frequency of at least - 216.19Hz. - - * "sinc3+pf1" - Sinc3 + Post Filter 1. 53dB rejection @ - 50Hz, 58dB rejection @ 60Hz. - - * "sinc3+pf2" - Sinc3 + Post Filter 2. 70dB rejection @ - 50Hz, 70dB rejection @ 60Hz. - - * "sinc3+pf3" - Sinc3 + Post Filter 3. 99dB rejection @ - 50Hz, 103dB rejection @ 60Hz. - - * "sinc3+pf4" - Sinc3 + Post Filter 4. 103dB rejection @ - 50Hz, 109dB rejection @ 60Hz. - -What: /sys/bus/iio/devices/iio:deviceX/in_voltageY-voltageZ_filter_mode -KernelVersion: 6.2 -Contact: linux-iio@vger.kernel.org -Description: - Set the filter mode of the differential channel. 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charset="utf-8" Add support for AD7770, AD7771, AD7779 ADCs. The device is capable of sending out data both on DOUT lines interface,as on the SDO line. The driver currently implements only the SDO data streaming mode. SPI communication is used alternatively for accessing registers and streaming data. Register access are protected by crc8. Signed-off-by: Ramona Alexandra Nechita --- drivers/iio/adc/Kconfig | 11 + drivers/iio/adc/Makefile | 1 + drivers/iio/adc/ad7779.c | 917 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 929 insertions(+) create mode 100644 drivers/iio/adc/ad7779.c diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index 88e8ce2e78b3..fe6d56225fa1 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -267,6 +267,17 @@ config AD7768_1 To compile this driver as a module, choose M here: the module will be called ad7768-1. =20 +config AD7779 + tristate "Analog Devices AD7779 ADC driver" + depends on SPI + select IIO_BUFFER + help + Say yes here to build support for Analog Devices AD777X family + (AD7770, AD7771, AD7779) analog to digital converter (ADC). + + To compile this driver as a module, choose M here: the module will be + called ad7779. + config AD7780 tristate "Analog Devices AD7780 and similar ADCs driver" depends on SPI diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile index 8b80664c6d6b..3d28ea490e01 100644 --- a/drivers/iio/adc/Makefile +++ b/drivers/iio/adc/Makefile @@ -27,6 +27,7 @@ obj-$(CONFIG_AD7606_IFACE_SPI) +=3D ad7606_spi.o obj-$(CONFIG_AD7606) +=3D ad7606.o obj-$(CONFIG_AD7766) +=3D ad7766.o obj-$(CONFIG_AD7768_1) +=3D ad7768-1.o +obj-$(CONFIG_AD7779) +=3D ad7779.o obj-$(CONFIG_AD7780) +=3D ad7780.o obj-$(CONFIG_AD7791) +=3D ad7791.o obj-$(CONFIG_AD7793) +=3D ad7793.o diff --git a/drivers/iio/adc/ad7779.c b/drivers/iio/adc/ad7779.c new file mode 100644 index 000000000000..05ae72257c9e --- /dev/null +++ b/drivers/iio/adc/ad7779.c @@ -0,0 +1,917 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * AD7770, AD7771, AD7779 ADC + * + * Copyright 2023-2024 Analog Devices Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include +#include +#include + +#define AD7779_SPI_READ_CMD BIT(7) + +#define AD7779_DISABLE_SD BIT(7) + +#define AD7779_REG_CH_DISABLE 0x08 +#define AD7779_REG_CH_SYNC_OFFSET(ch) (0x09 + (ch)) +#define AD7779_REG_CH_CONFIG(ch) (0x00 + (ch)) +#define AD7779_REG_GENERAL_USER_CONFIG_1 0x11 +#define AD7779_REG_GENERAL_USER_CONFIG_2 0x12 +#define AD7779_REG_GENERAL_USER_CONFIG_3 0x13 +#define AD7779_REG_DOUT_FORMAT 0x14 +#define AD7779_REG_ADC_MUX_CONFIG 0x15 +#define AD7779_REG_GPIO_CONFIG 0x17 +#define AD7779_REG_BUFFER_CONFIG_1 0x19 +#define AD7779_REG_GLOBAL_MUX_CONFIG 0x16 +#define AD7779_REG_BUFFER_CONFIG_2 0x1A +#define AD7779_REG_GPIO_DATA 0x18 +#define AD7779_REG_CH_OFFSET_UPPER_BYTE(ch) (0x1C + (ch) * 6) +#define AD7779_REG_CH_OFFSET_LOWER_BYTE(ch) (0x1E + (ch) * 6) +#define AD7779_REG_CH_GAIN_UPPER_BYTE(ch) (0x1F + (ch) * 6) +#define AD7779_REG_CH_OFFSET_MID_BYTE(ch) (0x1D + (ch) * 6) +#define AD7779_REG_CH_GAIN_MID_BYTE(ch) (0x20 + (ch) * 6) +#define AD7779_REG_CH_ERR_REG(ch) (0x4C + (ch)) +#define AD7779_REG_CH0_1_SAT_ERR 0x54 +#define AD7779_REG_CH_GAIN_LOWER_BYTE(ch) (0x21 + (ch) * 6) +#define AD7779_REG_CH2_3_SAT_ERR 0x55 +#define AD7779_REG_CH4_5_SAT_ERR 0x56 +#define AD7779_REG_CH6_7_SAT_ERR 0x57 +#define AD7779_REG_CHX_ERR_REG_EN 0x58 +#define AD7779_REG_GEN_ERR_REG_1 0x59 +#define AD7779_REG_GEN_ERR_REG_1_EN 0x5A +#define AD7779_REG_GEN_ERR_REG_2 0x5B +#define AD7779_REG_GEN_ERR_REG_2_EN 0x5C +#define AD7779_REG_STATUS_REG_1 0x5D +#define AD7779_REG_STATUS_REG_2 0x5E +#define AD7779_REG_STATUS_REG_3 0x5F +#define AD7779_REG_SRC_N_MSB 0x60 +#define AD7779_REG_SRC_N_LSB 0x61 +#define AD7779_REG_SRC_IF_MSB 0x62 +#define AD7779_REG_SRC_IF_LSB 0x63 +#define AD7779_REG_SRC_UPDATE 0x64 + +#define AD7779_FILTER_MSK BIT(6) +#define AD7779_MOD_POWERMODE_MSK BIT(6) +#define AD7779_MOD_PDB_REFOUT_MSK BIT(4) +#define AD7779_MOD_SPI_EN_MSK BIT(4) +#define AD7779_USRMOD_INIT_MSK GENMASK(6,4) + +/* AD7779_REG_DOUT_FORMAT */ +#define AD7779_DOUT_FORMAT_MSK GENMASK(7, 6) +#define AD7779_DOUT_HEADER_FORMAT BIT(5) +#define AD7779_DCLK_CLK_DIV_MSK GENMASK(3, 1) + +#define AD7779_REFMUX_CTRL_MSK GENMASK(7, 6) +#define AD7779_SPI_CRC_EN_MSK BIT(0) + +#define AD7779_MAXCLK_LOWPOWER 4096000 +#define AD7779_NUM_CHANNELS 8 +#define AD7779_RESET_BUF_SIZE 8 +#define AD7779_CHAN_DATA_SIZE 4 + +#define AD7779_LOWPOWER_DIV 512 +#define AD7779_HIGHPOWER_DIV 2048 + +#define AD7779_SINC3_MAXFREQ (16 * HZ_PER_KHZ) +#define AD7779_SINC5_MAXFREQ (128 * HZ_PER_KHZ) + +#define AD7779_DEFAULT_SAMPLING_FREQ (8 * HZ_PER_KHZ) +#define AD7779_DEFAULT_SAMPLING_2LINE (4 * HZ_PER_KHZ) +#define AD7779_DEFAULT_SAMPLING_1LINE (2 * HZ_PER_KHZ) + +#define AD7779_SPIMODE_MAX_SAMP_FREQ (16 * HZ_PER_KHZ) + +#define GAIN_REL 0x555555 +#define AD7779_FREQ_MSB_MSK GENMASK(15, 8) +#define AD7779_FREQ_LSB_MSK GENMASK(7, 0) +#define AD7779_UPPER GENMASK(23, 16) +#define AD7779_MID GENMASK(15, 8) +#define AD7779_LOWER GENMASK(7, 0) + +#define AD7779_REG_MSK GENMASK(6, 0) + +#define AD7779_CRC8_POLY 0x07 +DECLARE_CRC8_TABLE(ad7779_crc8_table); + +enum ad7779_filter { + AD7779_SINC3, + AD7779_SINC5, +}; + +enum ad7779_variant { + ad7770, + ad7771, + ad7779, +}; + +enum ad7779_power_mode { + AD7779_LOW_POWER, + AD7779_HIGH_POWER, +}; + +struct ad7779_chip_info { + const char *name; + struct iio_chan_spec const *channels; +}; + +struct ad7779_state { + struct spi_device *spi; + const struct ad7779_chip_info *chip_info; + struct clk *mclk; + struct iio_trigger *trig; + struct completion completion; + unsigned int sampling_freq; + enum ad7779_filter filter_enabled; + /* + * DMA (thus cache coherency maintenance) requires the + * transfer buffers to live in their own cache lines. + */ + u8 reg_rx_buf[3] __aligned(IIO_DMA_MINALIGN); + u8 reg_tx_buf[3]; + u32 spidata_rx[8]; + u32 spidata_tx[8]; + u8 reset_buf[8]; +}; + +static const char * const ad7779_filter_type[] =3D { + [AD7779_SINC3] =3D "sinc3", + [AD7779_SINC5] =3D "sinc5", +}; + +static int ad7779_spi_read(struct ad7779_state *st, u8 reg, u8 *rbuf) +{ + int ret; + int length =3D 3; + u8 crc_buf[2]; + u8 exp_crc =3D 0; + struct spi_transfer reg_read_tr[] =3D { + { + .tx_buf =3D st->reg_tx_buf, + .rx_buf =3D st->reg_rx_buf, + }, + }; + + if (reg =3D=3D AD7779_REG_GEN_ERR_REG_1_EN) + length =3D 2; + reg_read_tr[0].len =3D length; + + st->reg_tx_buf[0] =3D AD7779_SPI_READ_CMD | FIELD_GET(AD7779_REG_MSK, reg= ); + st->reg_tx_buf[1] =3D 0; + st->reg_tx_buf[2] =3D crc8(ad7779_crc8_table, st->reg_tx_buf, 2, 0); + + ret =3D spi_sync_transfer(st->spi, reg_read_tr, ARRAY_SIZE(reg_read_tr)); + if (ret) + return ret; + + crc_buf[0] =3D AD7779_SPI_READ_CMD | FIELD_GET(AD7779_REG_MSK, reg); + crc_buf[1] =3D st->reg_rx_buf[1]; + exp_crc =3D crc8(ad7779_crc8_table, crc_buf, 2, 0); + if (reg !=3D AD7779_REG_GEN_ERR_REG_1_EN && exp_crc !=3D st->reg_rx_buf[2= ]) { + dev_err(&st->spi->dev, "Bad CRC %x, expected %x", + st->reg_rx_buf[2], exp_crc); + return -EINVAL; + } + *rbuf =3D st->reg_rx_buf[1]; + + return 0; +} + +static int ad7779_spi_write(struct ad7779_state *st, u8 reg, u8 val) +{ + int length =3D 3; + + if (reg =3D=3D AD7779_REG_GEN_ERR_REG_1_EN) + length =3D 2; + + st->reg_tx_buf[0] =3D FIELD_GET(AD7779_REG_MSK, reg); + st->reg_tx_buf[1] =3D val; + st->reg_tx_buf[2] =3D crc8(ad7779_crc8_table, st->reg_tx_buf, 2, 0); + + return spi_write(st->spi, st->reg_tx_buf, length); +} + +static int ad7779_spi_write_mask(struct ad7779_state *st, u8 reg, u8 mask, + u8 val) +{ + int ret; + u8 regval, data; + + ret =3D ad7779_spi_read(st, reg, &data); + if (ret) + return ret; + + regval =3D data; + regval &=3D ~mask; + regval |=3D val; + + if (regval =3D=3D data) + return 0; + + return ad7779_spi_write(st, reg, regval); +} + +static int ad7779_reg_access(struct iio_dev *indio_dev, + unsigned int reg, + unsigned int writeval, + unsigned int *readval) +{ + struct ad7779_state *st =3D iio_priv(indio_dev); + + if (readval) + return ad7779_spi_read(st, reg, (u8 *)readval); + + return ad7779_spi_write(st, reg, writeval); +} + +static int ad7779_set_sampling_frequency(struct ad7779_state *st, + unsigned int sampling_freq) +{ + int ret; + unsigned int dec; + unsigned int div; + unsigned int decimal; + int temp; + unsigned int kfreq; + + if (st->filter_enabled =3D=3D AD7779_SINC3 && + sampling_freq > AD7779_SINC3_MAXFREQ) + return -EINVAL; + + if (st->filter_enabled =3D=3D AD7779_SINC5 && + sampling_freq > AD7779_SINC5_MAXFREQ) + return -EINVAL; + + if (sampling_freq > AD7779_SPIMODE_MAX_SAMP_FREQ) + return -EINVAL; + + div =3D AD7779_HIGHPOWER_DIV; + + kfreq =3D sampling_freq / KILO; + dec =3D div / kfreq; + + ret =3D ad7779_spi_write(st, AD7779_REG_SRC_N_MSB, + FIELD_GET(AD7779_FREQ_MSB_MSK, dec)); + if (ret) + return ret; + ret =3D ad7779_spi_write(st, AD7779_REG_SRC_N_LSB, + FIELD_GET(AD7779_FREQ_LSB_MSK, dec)); + if (ret) + return ret; + + if (div % kfreq) { + temp =3D (div * KILO) / kfreq; + decimal =3D ((temp - dec * KILO) << 16) / KILO; + ret =3D ad7779_spi_write(st, AD7779_REG_SRC_N_MSB, + FIELD_GET(AD7779_FREQ_MSB_MSK, decimal)); + if (ret) + return ret; + ret =3D ad7779_spi_write(st, AD7779_REG_SRC_N_LSB, + FIELD_GET(AD7779_FREQ_LSB_MSK, decimal)); + if (ret) + return ret; + } else { + ret =3D ad7779_spi_write(st, AD7779_REG_SRC_N_MSB, + FIELD_GET(AD7779_FREQ_MSB_MSK, 0x0)); + if (ret) + return ret; + ret =3D ad7779_spi_write(st, AD7779_REG_SRC_N_LSB, + FIELD_GET(AD7779_FREQ_LSB_MSK, 0x0)); + if (ret) + return ret; + } + ret =3D ad7779_spi_write(st, AD7779_REG_SRC_UPDATE, 0x1); + if (ret) + return ret; + + /* SRC update settling time */ + fsleep(15); + ret =3D ad7779_spi_write(st, AD7779_REG_SRC_UPDATE, 0x0); + if (ret) + return ret; + + /* SRC update settling time */ + fsleep(15); + + st->sampling_freq =3D sampling_freq; + + return 0; +} + +static int ad7779_get_filter(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan) +{ + struct ad7779_state *st =3D iio_priv(indio_dev); + u8 temp; + int ret; + + ret =3D ad7779_spi_read(st, AD7779_REG_GENERAL_USER_CONFIG_2, &temp); + if (ret) + return ret; + + return FIELD_GET(AD7779_FILTER_MSK, temp); +} + +static int ad7779_set_filter(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + unsigned int mode) +{ + struct ad7779_state *st =3D iio_priv(indio_dev); + int ret; + + ret =3D ad7779_spi_write_mask(st, + AD7779_REG_GENERAL_USER_CONFIG_2, + AD7779_FILTER_MSK, + FIELD_PREP(AD7779_FILTER_MSK, mode)); + if (ret < 0) + return ret; + + ret =3D ad7779_set_sampling_frequency(st, st->sampling_freq); + if (ret < 0) + return ret; + + st->filter_enabled =3D mode; + + return 0; +} + +static int ad7779_get_calibscale(struct ad7779_state *st, int channel) +{ + int ret; + u8 calibscale[3]; + + ret =3D ad7779_spi_read(st, AD7779_REG_CH_GAIN_LOWER_BYTE(channel), &cali= bscale[0]); + if (ret) + return ret; + + ret =3D ad7779_spi_read(st, AD7779_REG_CH_GAIN_MID_BYTE(channel), &calibs= cale[1]); + if (ret) + return ret; + + ret =3D ad7779_spi_read(st, AD7779_REG_CH_GAIN_UPPER_BYTE(channel), &cali= bscale[2]); + if (ret) + return ret; + + return get_unaligned_be24(calibscale); +} + +static int ad7779_set_calibscale(struct ad7779_state *st, int channel, int= val) +{ + int ret; + unsigned int gain; + unsigned long long tmp; + u8 gain_bytes[3]; + + tmp =3D val * 5592405LL; + gain =3D DIV_ROUND_CLOSEST_ULL(tmp, MEGA); + put_unaligned_be24(gain, gain_bytes); + ret =3D ad7779_spi_write(st, + AD7779_REG_CH_GAIN_UPPER_BYTE(channel), + gain_bytes[0]); + if (ret) + return ret; + + ret =3D ad7779_spi_write(st, + AD7779_REG_CH_GAIN_MID_BYTE(channel), + gain_bytes[1]); + if (ret) + return ret; + + return ad7779_spi_write(st, + AD7779_REG_CH_GAIN_LOWER_BYTE(channel), + gain_bytes[2]); +} + +static int ad7779_get_calibbias(struct ad7779_state *st, int channel) +{ + int ret; + u8 calibbias[3]; + + ret =3D ad7779_spi_read(st, AD7779_REG_CH_OFFSET_LOWER_BYTE(channel), + &calibbias[0]); + if (ret) + return ret; + + ret =3D ad7779_spi_read(st, AD7779_REG_CH_OFFSET_MID_BYTE(channel), + &calibbias[1]); + if (ret) + return ret; + + ret =3D ad7779_spi_read(st, + AD7779_REG_CH_OFFSET_UPPER_BYTE(channel), + &calibbias[2]); + if (ret) + return ret; + + return get_unaligned_be24(calibbias); +} + +static int ad7779_set_calibbias(struct ad7779_state *st, int channel, int = val) +{ + int ret; + u8 calibbias[3]; + + put_unaligned_be24(val, calibbias); + ret =3D ad7779_spi_write(st, + AD7779_REG_CH_OFFSET_UPPER_BYTE(channel), + calibbias[0]); + if (ret) + return ret; + + ret =3D ad7779_spi_write(st, + AD7779_REG_CH_OFFSET_MID_BYTE(channel), + calibbias[1]); + if (ret) + return ret; + + return ad7779_spi_write(st, + AD7779_REG_CH_OFFSET_LOWER_BYTE(channel), + calibbias[2]); +} + +static int ad7779_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, int *val, + int *val2, long mask) +{ + struct ad7779_state *st =3D iio_priv(indio_dev); + + iio_device_claim_direct_scoped(return -EBUSY, indio_dev) { + switch (mask) { + case IIO_CHAN_INFO_CALIBSCALE: + *val =3D ad7779_get_calibscale(st, chan->channel); + if (*val < 0) + return -EINVAL; + *val2 =3D GAIN_REL; + return IIO_VAL_FRACTIONAL; + case IIO_CHAN_INFO_CALIBBIAS: + *val =3D ad7779_get_calibbias(st, chan->channel); + if (*val < 0) + return -EINVAL; + return IIO_VAL_INT; + case IIO_CHAN_INFO_SAMP_FREQ: + *val =3D st->sampling_freq; + if (*val < 0) + return -EINVAL; + return IIO_VAL_INT; + } + return -EINVAL; + } + unreachable(); +} + +static int ad7779_write_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, int val, int val2, + long mask) +{ + struct ad7779_state *st =3D iio_priv(indio_dev); + + iio_device_claim_direct_scoped(return -EBUSY, indio_dev) { + switch (mask) { + case IIO_CHAN_INFO_CALIBSCALE: + return ad7779_set_calibscale(st, chan->channel, val2); + case IIO_CHAN_INFO_CALIBBIAS: + return ad7779_set_calibbias(st, chan->channel, val); + case IIO_CHAN_INFO_SAMP_FREQ: + return ad7779_set_sampling_frequency(st, val); + default: + return -EINVAL; + } + } + unreachable(); +} + +static int ad7779_buffer_preenable(struct iio_dev *indio_dev) +{ + int ret; + struct ad7779_state *st =3D iio_priv(indio_dev); + + ret =3D ad7779_spi_write_mask(st, + AD7779_REG_GENERAL_USER_CONFIG_3, + AD7779_MOD_SPI_EN_MSK, + FIELD_PREP(AD7779_MOD_SPI_EN_MSK, 1)); + if (ret) + return ret; + + /* + * DRDY output cannot be disabled at device level therefore we mask + * the irq at host end. + */ + enable_irq(st->spi->irq); + + return 0; +} + +static int ad7779_buffer_postdisable(struct iio_dev *indio_dev) +{ + struct ad7779_state *st =3D iio_priv(indio_dev); + + disable_irq(st->spi->irq); + + return ad7779_spi_write(st, AD7779_REG_GENERAL_USER_CONFIG_3, + AD7779_DISABLE_SD); +} + +static irqreturn_t ad7779_trigger_handler(int irq, void *p) +{ + struct iio_poll_func *pf =3D p; + struct iio_dev *indio_dev =3D pf->indio_dev; + struct ad7779_state *st =3D iio_priv(indio_dev); + int ret; + int bit; + int k =3D 0; + /* + * Each channel shifts out HEADER + 24 bits of data therefore 8 * u32 + * for the data and 64 bits for the timestamp + */ + u32 tmp[10]; + + struct spi_transfer sd_readback_tr[] =3D { + { + .rx_buf =3D st->spidata_rx, + .tx_buf =3D st->spidata_tx, + .len =3D AD7779_NUM_CHANNELS * AD7779_CHAN_DATA_SIZE, + } + }; + + if (!iio_buffer_enabled(indio_dev)) + goto exit_handler; + + st->spidata_tx[0] =3D AD7779_SPI_READ_CMD; + ret =3D spi_sync_transfer(st->spi, sd_readback_tr, + ARRAY_SIZE(sd_readback_tr)); + if (ret) { + dev_err(&st->spi->dev, + "spi transfer error in irq handler"); + goto exit_handler; + } + + for_each_set_bit(bit, indio_dev->active_scan_mask, AD7779_NUM_CHANNELS - = 1) + tmp[k++] =3D st->spidata_rx[bit]; + + iio_push_to_buffers_with_timestamp(indio_dev, &tmp[0], pf->timestamp); + +exit_handler: + iio_trigger_notify_done(indio_dev->trig); + return IRQ_HANDLED; +} + +static int ad7779_reset(struct iio_dev *indio_dev, struct gpio_desc *reset= _gpio) +{ + struct ad7779_state *st =3D iio_priv(indio_dev); + int ret; + struct spi_transfer reg_read_tr[] =3D { + { + .tx_buf =3D st->reset_buf, + .len =3D 8, + }, + }; + + memset(st->reset_buf, 0xff, sizeof(st->reset_buf)); + + if (reset_gpio) { + /* Delay for reset to occur is 225 microseconds*/ + gpiod_set_value(reset_gpio, 1); + fsleep(230); + return 0; + } + + ret =3D spi_sync_transfer(st->spi, reg_read_tr, + ARRAY_SIZE(reg_read_tr)); + if (ret) + return ret; + + /* Delay for reset to occur is 225 microseconds*/ + fsleep(230); + + return 0; +} + +static const struct iio_info ad7779_info =3D { + .read_raw =3D ad7779_read_raw, + .write_raw =3D ad7779_write_raw, + .debugfs_reg_access =3D &ad7779_reg_access, +}; + +static const struct iio_enum ad7779_filter_enum =3D { + .items =3D ad7779_filter_type, + .num_items =3D ARRAY_SIZE(ad7779_filter_type), + .get =3D ad7779_get_filter, + .set =3D ad7779_set_filter, +}; + +static const struct iio_chan_spec_ext_info ad7779_ext_filter[] =3D { + IIO_ENUM("filter_type", IIO_SHARED_BY_ALL, &ad7779_filter_enum), + IIO_ENUM_AVAILABLE("filter_type", IIO_SHARED_BY_ALL, + &ad7779_filter_enum), + { } +}; + +#define AD777x_CHAN_S(index, _ext_info) \ + { \ + .type =3D IIO_VOLTAGE, \ + .info_mask_separate =3D BIT(IIO_CHAN_INFO_CALIBSCALE) | \ + BIT(IIO_CHAN_INFO_CALIBBIAS), \ + .info_mask_shared_by_all =3D BIT(IIO_CHAN_INFO_SAMP_FREQ), \ + .address =3D (index), \ + .indexed =3D 1, \ + .channel =3D (index), \ + .scan_index =3D (index), \ + .ext_info =3D (_ext_info), \ + .scan_type =3D { \ + .sign =3D 's', \ + .realbits =3D 24, \ + .storagebits =3D 32, \ + .endianness =3D IIO_BE, \ + }, \ + } + +#define AD777x_CHAN_NO_FILTER_S(index) \ + AD777x_CHAN_S(index, NULL) + +#define AD777x_CHAN_FILTER_S(index) \ + AD777x_CHAN_S(index, ad7779_ext_filter) +static const struct iio_chan_spec ad7779_channels[] =3D { + AD777x_CHAN_NO_FILTER_S(0), + AD777x_CHAN_NO_FILTER_S(1), + AD777x_CHAN_NO_FILTER_S(2), + AD777x_CHAN_NO_FILTER_S(3), + AD777x_CHAN_NO_FILTER_S(4), + AD777x_CHAN_NO_FILTER_S(5), + AD777x_CHAN_NO_FILTER_S(6), + AD777x_CHAN_NO_FILTER_S(7), + IIO_CHAN_SOFT_TIMESTAMP(8), +}; + +static const struct iio_chan_spec ad7779_channels_filter[] =3D { + AD777x_CHAN_FILTER_S(0), + AD777x_CHAN_FILTER_S(1), + AD777x_CHAN_FILTER_S(2), + AD777x_CHAN_FILTER_S(3), + AD777x_CHAN_FILTER_S(4), + AD777x_CHAN_FILTER_S(5), + AD777x_CHAN_FILTER_S(6), + AD777x_CHAN_FILTER_S(7), + IIO_CHAN_SOFT_TIMESTAMP(8), +}; + +static const struct iio_buffer_setup_ops ad7779_buffer_setup_ops =3D { + .preenable =3D ad7779_buffer_preenable, + .postdisable =3D ad7779_buffer_postdisable, +}; + +static const struct iio_trigger_ops ad7779_trigger_ops =3D { + .validate_device =3D iio_trigger_validate_own_device, +}; + +static int ad7779_powerup(struct ad7779_state *st, struct gpio_desc *start= _gpio) +{ + int ret; + + ret =3D ad7779_spi_write_mask(st, AD7779_REG_GEN_ERR_REG_1_EN, + AD7779_SPI_CRC_EN_MSK, + FIELD_PREP(AD7779_SPI_CRC_EN_MSK, 1)); + if (ret) + return ret; + + ret =3D ad7779_spi_write_mask(st, AD7779_REG_GENERAL_USER_CONFIG_1, + AD7779_USRMOD_INIT_MSK, + FIELD_PREP(AD7779_USRMOD_INIT_MSK, 5)); + if (ret) + return ret; + + ret =3D ad7779_spi_write_mask(st, AD7779_REG_DOUT_FORMAT, + AD7779_DCLK_CLK_DIV_MSK, + FIELD_PREP(AD7779_DCLK_CLK_DIV_MSK, 1)); + if (ret) + return ret; + + ret =3D ad7779_spi_write_mask(st, AD7779_REG_ADC_MUX_CONFIG, + AD7779_REFMUX_CTRL_MSK, + FIELD_PREP(AD7779_REFMUX_CTRL_MSK, 1)); + if (ret) + return ret; + + ret =3D ad7779_set_sampling_frequency(st, AD7779_DEFAULT_SAMPLING_FREQ); + if (ret) + return ret; + + gpiod_set_value(start_gpio, 0); + /* Start setup time */ + fsleep(15); + gpiod_set_value(start_gpio, 1); + fsleep(15); + gpiod_set_value(start_gpio, 0); + fsleep(15); + + return 0; +} + +static int ad7779_probe(struct spi_device *spi) +{ + struct iio_dev *indio_dev; + struct ad7779_state *st; + struct gpio_desc *reset_gpio, *start_gpio; + int ret; + + indio_dev =3D devm_iio_device_alloc(&spi->dev, sizeof(*st)); + if (!indio_dev) + return -ENOMEM; + + st =3D iio_priv(indio_dev); + + st->mclk =3D devm_clk_get_enabled(&spi->dev, "mclk"); + if (IS_ERR(st->mclk)) + return PTR_ERR(st->mclk); + + if (!spi->irq) + return dev_err_probe(&spi->dev, ret, + "DRDY irq not present\n"); + + reset_gpio =3D devm_gpiod_get_optional(&spi->dev, "reset", GPIOD_OUT_LOW); + if (IS_ERR(reset_gpio)) + return PTR_ERR(reset_gpio); + + start_gpio =3D devm_gpiod_get(&spi->dev, "start", GPIOD_OUT_HIGH); + if (IS_ERR(start_gpio)) + return PTR_ERR(start_gpio); + + crc8_populate_msb(ad7779_crc8_table, AD7779_CRC8_POLY); + st->spi =3D spi; + + st->chip_info =3D spi_get_device_match_data(spi); + if (!st->chip_info) + return -ENODEV; + + ret =3D ad7779_reset(indio_dev, reset_gpio); + if (ret) + return ret; + + ad7779_powerup(st, start_gpio); + if (ret) + return ret; + + indio_dev->name =3D st->chip_info->name; + indio_dev->info =3D &ad7779_info; + indio_dev->modes =3D INDIO_DIRECT_MODE; + indio_dev->channels =3D st->chip_info->channels; + indio_dev->num_channels =3D ARRAY_SIZE(ad7779_channels); + + st->trig =3D devm_iio_trigger_alloc(&spi->dev, "%s-dev%d", + indio_dev->name, iio_device_id(indio_dev)); + if (!st->trig) + return -ENOMEM; + + st->trig->ops =3D &ad7779_trigger_ops; + + iio_trigger_set_drvdata(st->trig, st); + + ret =3D devm_request_irq(&spi->dev, spi->irq, + iio_trigger_generic_data_rdy_poll, + IRQF_ONESHOT | IRQF_NO_AUTOEN, + indio_dev->name, st->trig); + if (ret) + return dev_err_probe(&spi->dev, ret, "request irq %d failed\n", + st->spi->irq); + + ret =3D devm_iio_trigger_register(&spi->dev, st->trig); + if (ret) + return ret; + + indio_dev->trig =3D iio_trigger_get(st->trig); + + init_completion(&st->completion); + + ret =3D devm_iio_triggered_buffer_setup(&spi->dev, indio_dev, + &iio_pollfunc_store_time, + &ad7779_trigger_handler, + &ad7779_buffer_setup_ops); + if (ret) + return ret; + + ret =3D ad7779_spi_write_mask(st, AD7779_REG_DOUT_FORMAT, + AD7779_DCLK_CLK_DIV_MSK, + FIELD_PREP(AD7779_DCLK_CLK_DIV_MSK, 7)); + if (ret) + return ret; + + return devm_iio_device_register(&spi->dev, indio_dev); +} + +static int ad7779_suspend(struct device *dev) +{ + struct iio_dev *indio_dev =3D dev_get_drvdata(dev); + struct ad7779_state *st =3D iio_priv(indio_dev); + int ret; + + ret =3D ad7779_spi_write_mask(st, AD7779_REG_GENERAL_USER_CONFIG_1, + AD7779_MOD_POWERMODE_MSK, + FIELD_PREP(AD7779_MOD_POWERMODE_MSK, + AD7779_LOW_POWER)); + if (ret) + return ret; + + return 0; +} + +static int ad7779_resume(struct device *dev) +{ + struct iio_dev *indio_dev =3D dev_get_drvdata(dev); + struct ad7779_state *st =3D iio_priv(indio_dev); + int ret; + + ret =3D ad7779_spi_write_mask(st, AD7779_REG_GENERAL_USER_CONFIG_1, + AD7779_MOD_POWERMODE_MSK, + FIELD_PREP(AD7779_MOD_POWERMODE_MSK, + AD7779_HIGH_POWER)); + if (ret) + return ret; + + return 0; +} + +static DEFINE_SIMPLE_DEV_PM_OPS(ad7779_pm_ops, ad7779_suspend, ad7779_resu= me); + +static const struct ad7779_chip_info ad7770_chip_info =3D { + .name =3D "ad7770", + .channels =3D ad7779_channels, +}; + +static const struct ad7779_chip_info ad7771_chip_info =3D { + .name =3D "ad7771", + .channels =3D ad7779_channels_filter, +}; + +static const struct ad7779_chip_info ad7779_chip_info =3D { + .name =3D "ad7779", + .channels =3D ad7779_channels, +}; + +static const struct spi_device_id ad7779_id[] =3D { + { + .name =3D "ad7770", + .driver_data =3D (kernel_ulong_t)&ad7770_chip_info + }, + { + .name =3D "ad7771", + .driver_data =3D (kernel_ulong_t)&ad7771_chip_info + }, + { + .name =3D "ad7779", + .driver_data =3D (kernel_ulong_t)&ad7779_chip_info + }, + { } +}; +MODULE_DEVICE_TABLE(spi, ad7779_id); + +static const struct of_device_id ad7779_of_table[] =3D { + { + .compatible =3D "adi,ad7770", + .data =3D &ad7770_chip_info, + }, + { + .compatible =3D "adi,ad7771", + .data =3D &ad7771_chip_info, + }, + { + .compatible =3D "adi,ad7779", + .data =3D &ad7779_chip_info, + }, + { } +}; +MODULE_DEVICE_TABLE(of, ad7779_of_table); + +static struct spi_driver ad7779_driver =3D { + .driver =3D { + .name =3D "ad7779", + .pm =3D pm_sleep_ptr(&ad7779_pm_ops), + .of_match_table =3D ad7779_of_table, + }, + .probe =3D ad7779_probe, + .id_table =3D ad7779_id, +}; +module_spi_driver(ad7779_driver); + +MODULE_AUTHOR("Ramona Alexandra Nechita "); +MODULE_DESCRIPTION("Analog Devices AD7779 ADC"); +MODULE_LICENSE("GPL"); --=20 2.43.0