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[24.56.189.226]) by smtp.gmail.com with ESMTPSA id e9e14a558f8ab-3a05900e618sm32570135ab.55.2024.09.12.10.39.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Sep 2024 10:39:09 -0700 (PDT) From: Raul E Rangel To: linux-serial@vger.kernel.org Cc: pmladek@suse.com, rafael.j.wysocki@intel.com, ribalda@chromium.org, Raul E Rangel , Len Brown , "Rafael J. Wysocki" , Robert Moore , acpica-devel@lists.linux.dev, linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/3] ACPI: SPCR: Add support for rev 3 Date: Thu, 12 Sep 2024 11:36:21 -0600 Message-ID: <20240912113616.3.I1b7a5033a2191cb0cdbadc2d51666a97f16cc663@changeid> X-Mailer: git-send-email 2.46.0.662.g92d0881bb0-goog In-Reply-To: <20240912173901.3969597-1-rrangel@chromium.org> References: <20240912173901.3969597-1-rrangel@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Revision 3 supports specifying the UART input clock. This allows for proper computation of the UART divisor when the baud rate is specified. The earlycon code can accept the following format (See `parse_options` in `earlycon.c`.): * ,io|mmio|mmio32|mmio32be,,,, This change makes it so the uartclk is passed along if it's defined in the SPCR table. Booting with `earlycon` and a SPCR v3 table that has the uartclk and baud defined: [ 0.028251] ACPI: SPCR: console: uart,mmio32,0xfedc9000,115200,48000000 [ 0.028267] earlycon: uart0 at MMIO32 0x00000000fedc9000 (options '11520= 0,48000000') [ 0.028272] printk: legacy bootconsole [uart0] enabled Link: https://learn.microsoft.com/en-us/windows-hardware/drivers/serports/s= erial-port-console-redirection-table Signed-off-by: Raul E Rangel Reviewed-by: Petr Mladek --- drivers/acpi/spcr.c | 5 ++++- include/acpi/actbl3.h | 6 +++--- 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/acpi/spcr.c b/drivers/acpi/spcr.c index cd36a97b0ea2c7..67ae42afcc59ef 100644 --- a/drivers/acpi/spcr.c +++ b/drivers/acpi/spcr.c @@ -209,9 +209,12 @@ int __init acpi_parse_spcr(bool enable_earlycon, bool = enable_console) if (!baud_rate) { snprintf(opts, sizeof(opts), "%s,%s,0x%llx", uart, iotype, table->serial_port.address); - } else { + } else if (table->header.revision <=3D 2 || !table->uartclk) { snprintf(opts, sizeof(opts), "%s,%s,0x%llx,%d", uart, iotype, table->serial_port.address, baud_rate); + } else { + snprintf(opts, sizeof(opts), "%s,%s,0x%llx,%d,%d", uart, iotype, + table->serial_port.address, baud_rate, table->uartclk); } =20 pr_info("console: %s\n", opts); diff --git a/include/acpi/actbl3.h b/include/acpi/actbl3.h index 8f775e3a08fdfb..afe45a2379866a 100644 --- a/include/acpi/actbl3.h +++ b/include/acpi/actbl3.h @@ -92,10 +92,10 @@ struct acpi_table_slit { /*************************************************************************= ****** * * SPCR - Serial Port Console Redirection table - * Version 2 + * Version 3 * * Conforms to "Serial Port Console Redirection Table", - * Version 1.03, August 10, 2015 + * Version 1.08, October 7, 2021 * *************************************************************************= *****/ =20 @@ -120,7 +120,7 @@ struct acpi_table_spcr { u8 pci_function; u32 pci_flags; u8 pci_segment; - u32 reserved2; + u32 uartclk; }; =20 /* Masks for pci_flags field above */ --=20 2.46.0.662.g92d0881bb0-goog